CN203103284U - Tsop存储装置 - Google Patents

Tsop存储装置 Download PDF

Info

Publication number
CN203103284U
CN203103284U CN2012206613903U CN201220661390U CN203103284U CN 203103284 U CN203103284 U CN 203103284U CN 2012206613903 U CN2012206613903 U CN 2012206613903U CN 201220661390 U CN201220661390 U CN 201220661390U CN 203103284 U CN203103284 U CN 203103284U
Authority
CN
China
Prior art keywords
lead frame
pad
wafer
tsop
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2012206613903U
Other languages
English (en)
Inventor
孙日欣
卢伟
李振华
袁正红
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Biwin Storage Technology Co Ltd
Original Assignee
Biwin Storage Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Biwin Storage Technology Co Ltd filed Critical Biwin Storage Technology Co Ltd
Priority to CN2012206613903U priority Critical patent/CN203103284U/zh
Application granted granted Critical
Publication of CN203103284U publication Critical patent/CN203103284U/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Semiconductor Memories (AREA)

Abstract

本实用新型公开了一种TSOP存储装置，包括塑封件以及封装于所述塑封件内的引线框架和晶圆，所述晶圆上设有电路引出端，所述引线框架外露于所述塑封件形成外部引脚，还包括一转接电路板，所述转接电路板上设有第一焊盘和第二焊盘，所述第一焊盘与所述晶圆的电路引出端电连接，所述第二焊盘与所述引线框架电连接使所述引脚定义相匹配的所述电路引出端电连接。本实用新型通过采用转接电路板进行电路转接，解决了因使用不同的晶圆所引发的通用性问题，使得不必因使用不同的晶圆而要重新设计PCB电路，增强通用性，缩短了产品生产周期，降低开发成本。

Description

TSOP存储装置
技术领域
本实用新型涉及存储技术领域，尤其涉及一种TSOP存储装置。
背景技术
TSOP是“Thin Small Outline Package”的缩写，意思是薄型小尺寸封装。TSOP内存是在芯片的周围做出引脚，采用SMT技术（表面安装技术）直接附着在PCB板的表面。
如图1所示，现有的TSOP存储装置封装形式一般为TSOP48，即48个引脚，外形尺寸为12×20×1.2mm。图2示出了现有TSOP存储装置的内部结构示意图，在塑封件4’内部，通过wire bonding技术，将晶圆3’电路引出端与引线框架1’通过金线2’电路连接，从而做成存储装置，引线框架1’伸出塑封件4’形成外部引脚。参阅图3，晶圆3’上电路引出端与引线框架1’一一对应连接，相应于晶圆3’上电路引出端的功能，引线框架1’外露的引脚具有不同的定义。由于各品牌的存储晶圆的电路引出端设计不同，封装出的TSOP存储装置引脚定义不同。如果固定引脚定义，采用不同的晶圆进行封装时，若晶圆的电路引出端顺序与引线框架的引脚顺序不一致，两者之间连接的金线必然会出现交叉，例如参阅图4，引线框架1’从上而下的顺序为A、B、C、D、E、F、G、H，而晶圆3’上电路引出端的顺序从上而下分别为B1、C1、F1、G1、H1、A1、D1、E1，相同字母代表具有相同属性，此时一一对应连接则发生金线交叉的问题，而金线交叉是不允许出现的。
综上所述，现有的TSOP存储装置中，不同类型晶圆封装的存储装置具有不同的引脚定义，甚至有部分型号的存储晶圆不能直接做成引线框架类别的封装器件，需做成其它高成本类别的封装器件，从而引发终端使用非常繁琐，需要对不同的品牌与型号器件做对应PCB电路设计，通用性能差，拉长产品开发周期。
实用新型内容
本实用新型主要解决现有的TSOP存储装置通用性差的问题，将器件外围引脚定义固定化，避免因使用不用型号的存储装置而需要不断的改变PCB电路设计，从而缩短产品开发周期，降低开发成本。
为解决上述技术问题，本实用新型采用的一个技术方案是：提供一种TSOP存储装置，包括塑封件以及封装于所述塑封件内的引线框架和晶圆，所述晶圆上设有电路引出端，所述引线框架外露于所述塑封件形成外部引脚，还包括一转接电路板，所述转接电路板上设有第一焊盘和第二焊盘，所述第一焊盘与所述晶圆的电路引出端电连接，所述第二焊盘与所述引线框架电连接使所述引脚定义相匹配的所述电路引出端电连接。
其中，所述第一焊盘与所述晶圆的电路引出端通过金线连接，所述第二焊盘与所述引线框架通过金线连接，所述第一焊盘与所述第二焊盘通过转接电路板内部走线电连接而使所述外部引脚和与其引脚定义相匹配的所述电路引出端电连接。
其中，所述转接电路板、所述晶圆及所述引线框架层叠设置。
其中，所述转接电路板与所述晶圆粘贴固定。
其中，所述晶圆贴装在所述引线框架上。
本实用新型的有益效果是：本实用新型中，将晶圆上的电路引出端连接至转接电路板上，再将转接电路板上的相应接点连接至引线框架上对应的引脚，转接电路板承接一个桥梁作用。这种模式下，可固定引线框架的引脚位置，不需要去匹配晶圆的电路引出端位置，从而可实现存储装置引脚定义固定化与引线框架电路设计固定化。本实用新型通过采用转接电路板进行电路转接，解决了因使用不同的存储晶圆所引发的通用性问题，使得不必因使用不同的存储晶圆而要重新设计PCB电路，增强通用性，缩短了产品生产周期，降低开发成本。
附图说明
图1是现有技术的TSOP存储装置的封装结构形式；
图2是现有技术的TSOP存储装置的内部结构示意图；
图3是现有技术的TSOP存储装置中引线框架与晶圆连接的示意图；
图4是现有技术采用图3中引线框架配合另一种晶圆时的连接示意图；
图5是本实用新型的TSOP存储装置实施例的结构示意图；
图6是本实用新型的TSOP存储装置实施例的电路连接结构图。
标号说明：
1’、引线框架；2’、金线；3’、晶圆；4’、塑封件；
1、引线框架；11、外部引脚；2、金线；3、晶圆；31、电路引出端；4、塑封件；5、转接电路板；51、第一焊盘；52、第二焊盘。
具体实施方式
为详细说明本实用新型的技术内容、构造特征、所实现目的及效果，以下结合实施方式并配合附图详予说明。
请参阅图5以及图6，本实施方式的TSOP存储装置包括塑封件4以及封装于塑封件4内的引线框架1、晶圆3和转接电路板5。
引线框架1端部外露于塑封件4形成外部引脚11，考虑到通用化，先定义各外部引脚11的功能例如电源输入输出、数据输入输出、控制命令接口等等，图6中示意性地表示了不同功能定义的引线框架1的排布，其中按从上而下的顺序依次排列有A、B、C、D、E、F、G、H。
晶圆3上具有多个电路引出端31，各电路引出端31具有相应的功能，电路引出端31的排布顺序根据晶圆3的结构设计而定，图6中示意地给出了电路引出端31的排布结构，按图中从上而下的顺序分别排布有电路引出端B1、C1、F1、G1、H1、A1、D1、E1。
其中，用同样字母表示的引线框架1与电路引出端31具有相同的功能定义，两者之间应对应电连接。
转接电路板5粘贴固定于晶圆3上表面，转接电路板5上设有第一焊盘51和第二焊盘52，第一焊盘51和第二焊盘52均设置有多个。如图6，第一焊盘51按从上而下的顺序依次排布有B2、C2、F2、G2、H2、A2、D2、E2，各第一焊盘51分别对应地与电路引出端B1、C1、F1、G1、H1、A1、D1、E1一一对应通过金线2连接；第二焊盘52按从上而下的顺序依次排布有A3、B3、C3、D3、E3、F3、G3、H3，各第二焊盘52分别对应地与引线框架A、B、C、D、E、F、G、H通过金线2连接；各金线之间互不交叉。转接电路板5上通过内部走线将相应的第一焊盘51和第二焊盘52连接在一起，以实现引线框架1和与其引脚定义匹配的电路引出端31电连接。例如对于A定义外部引脚11，其应该电连接A1的电路引出端31，晶圆3上电路引出端A1通过金线2连接转接电路板5上的焊盘A2，转接电路板5上通过内部走线使焊盘A2与焊盘A3连接，而焊盘A3再与引线框架A通过金线2连接，这样通过转接电路板5的转接即实现了电路引出端A1与引线框架A的对应电连接。其他的引脚之间的电连接亦是相同的方式。
本实用新型中，将晶圆上的电路引出端连接至转接电路板上，再将转接电路板上的相应接点连接至引线框架上对应的引脚，转接电路板承接一个桥梁作用。这种模式下，可固定引线框架的引脚位置，不需要去匹配晶圆的电路引出端位置，从而可实现存储装置引脚定义固定化与引线框架电路设计固定化。本实用新型通过采用转接电路板进行电路转接，解决了因使用不同的存储晶圆所引发的通用性问题，使得不必因使用不同的存储晶圆而要重新设计PCB电路，增强通用性，缩短了产品生产周期，降低开发成本。
需要说明的是，上述实施例中，转接电路板粘贴于晶圆表面，主要是为了固定转接电路板的位置，方便晶圆和引线框架与其的连接，也方便在进行塑封封装时内部器件之间位置的一致性。转接电路板也可以是先不与晶圆相对固定，在塑封时由夹具固定其位置再塑封固定。转接电路板亦可粘贴于晶圆的下表面或是与引线框架贴装。
以上所述仅为本实用新型的实施例，并非因此限制本实用新型的专利范围，凡是利用本实用新型说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本实用新型的专利保护范围内。

Claims (5)

1.一种TSOP存储装置，包括塑封件以及封装于所述塑封件内的引线框架和晶圆，所述晶圆上设有电路引出端，所述引线框架外露于所述塑封件形成外部引脚，其特征在于，还包括一转接电路板，所述转接电路板上设有第一焊盘和第二焊盘，所述第一焊盘与所述晶圆的电路引出端电连接，所述第二焊盘与所述引线框架电连接，使所述引线框架和与其引脚定义相匹配的所述电路引出端电连接。
2.根据权利要求1所述的TSOP存储装置，其特征在于：所述第一焊盘与所述晶圆的电路引出端通过金线连接，所述第二焊盘与所述引线框架通过金线连接，所述第一焊盘与所述第二焊盘通过转接电路板内部走线电连接而使所述外部引脚和与其引脚定义相匹配的所述电路引出端电连接。
3.根据权利要求1所述的TSOP存储装置，其特征在于：所述转接电路板、所述晶圆及所述引线框架层叠设置。
4.根据权利要求3所述的TSOP存储装置，其特征在于：所述转接电路板与所述晶圆粘贴固定。
5.根据权利要求3所述的TSOP存储装置，其特征在于：所述晶圆贴装在所述引线框架上。
CN2012206613903U 2012-12-05 2012-12-05 Tsop存储装置 Expired - Fee Related CN203103284U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012206613903U CN203103284U (zh) 2012-12-05 2012-12-05 Tsop存储装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012206613903U CN203103284U (zh) 2012-12-05 2012-12-05 Tsop存储装置

Publications (1)

Publication Number Publication Date
CN203103284U true CN203103284U (zh) 2013-07-31

Family

ID=48854668

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012206613903U Expired - Fee Related CN203103284U (zh) 2012-12-05 2012-12-05 Tsop存储装置

Country Status (1)

Country Link
CN (1) CN203103284U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108012441A (zh) * 2017-12-25 2018-05-08 中国航空工业集团公司洛阳电光设备研究所 一种双列直插集成电路的原位替代实现方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108012441A (zh) * 2017-12-25 2018-05-08 中国航空工业集团公司洛阳电光设备研究所 一种双列直插集成电路的原位替代实现方法

Similar Documents

Publication Publication Date Title
CN105428334B (zh) 半导体封装结构
CN104124223B (zh) 电子系统及其核心模块
TW447059B (en) Multi-chip module integrated circuit package
CN103117263A (zh) 一种集成电路封装
CN102739069A (zh) 一种功率半导体模块以及应用其的电力电子设备
CN203103284U (zh) Tsop存储装置
CN102937663B (zh) 智能电表核心模块的封装结构及封装方法
CN103928431B (zh) 一种倒装封装装置
CN205508861U (zh) 一种led器件
CN101714544A (zh) 一种集成三极管及其制造方法
US20090091008A1 (en) Semiconductor device
KR102559874B1 (ko) 박형 시스템 인 패키지
KR20140148273A (ko) 반도체 패키지 및 그 제조 방법
CN101271725A (zh) 闪存存储卡
CN202374566U (zh) 一种多模块pcb封装及通讯终端
CN201732781U (zh) 一种引线框架
CN201436681U (zh) 一种新型芯片
CN110600447A (zh) 一种新型引线框架结构及封装结构
CN217306497U (zh) 一种u盘主控封装
CN201549504U (zh) 一种集成三极管
CN201655779U (zh) 层叠的封装件和包括该层叠的封装件的双界面智能卡
CN204271072U (zh) 引线框架封装结构
CN203733774U (zh) 半导体叠层封装结构
CN220731184U (zh) 封装模组和存储装置
CN102376666B (zh) 一种球栅阵列封装结构及其制造方法

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130731

Termination date: 20141205

EXPY Termination of patent right or utility model