CN202995614U - Electronic equipment - Google Patents
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- CN202995614U CN202995614U CN 201220719557 CN201220719557U CN202995614U CN 202995614 U CN202995614 U CN 202995614U CN 201220719557 CN201220719557 CN 201220719557 CN 201220719557 U CN201220719557 U CN 201220719557U CN 202995614 U CN202995614 U CN 202995614U
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Abstract
The utility model provides electronic equipment which comprises a reset circuit and a processor. The processor can be in a normal working state or a crash state, the reset circuit comprises a keyboard module and a reset control module, the keyboard module comprises multiple keys, the processor responds to pressing down of each key to execute preset corresponding operations, and when N preset keys in the keyboard module are pressed down simultaneously, the reset control module outputs a crash reset signal to the processor to enable the processor to perform resetting and restore to the normal working state, wherein N is a natural member larger than or equal to 2. Compared with the prior art, the electronic equipment can realize crash reset control on a system through key combination, so that cost for independently setting crash reset keys is saved, and better user experience is brought to clients.
Description
[technical field]
The utility model relates to circuit design field, particularly a kind of electronic equipment with deadlock reset function.
[background technology]
Various intelligence system of the prior art, bluetooth earphone for example, panel computer, smart mobile phone, intelligent television, PC, notebook computer, individual Medical Devices etc., the processors that adopt are controlled more.At present, widely used processor has low-power consumption ARM (Advanced RISC Machine, be called for short ARM) core, Intel CPU (Center Processor Unit), AMD CPU or MIPS (Million Instructions PerSecond) system etc., such as, ARM-A8.These processors may occur crashing when some abnormality.For example, when occurring serious lower a jumping on its supply voltage, when during perhaps due to variations such as neighbourhood noise or temperature, error in address appearred in access memory, perhaps owing to falling when causing some circuit moment loose contact, processor all may crash.And after the processor deadlock, need to start shooting again and could recover by the plug battery.And the smart machines such as existing bluetooth earphone, panel computer, because volume is very little, the very tight exquisiteness of its physical arrangement, the dismounting of inconvenient domestic consumer, unloading process very easily causes the physical unit loss, and therefore, domestic consumer generally can't dismantle battery.Although it is very little that the probability of deadlock occurs, if occur, consequence is very serious.Because battery is built-in, be inconvenient to dismantle, system is in the deadlock state always like this, until after the electric weight of battery depleted fully, then charge, the deadlock state could be resetted like this.Due to popular low power dissipation design all at present, battery is given out light voluntarily and is taken for a long time, makes like this customer experience very bad.
Therefore, be necessary to provide a kind of improved technical scheme to overcome the problems referred to above.
[utility model content]
The purpose of this utility model is to provide a kind of electronic equipment, and it can realize deadlock to the system control that resets by Macintosh, has not only saved the cost that the deadlock reset key is set separately, and has brought better user to experience to the client.
In order to address the above problem, the utility model provides a kind of electronic equipment, and it comprises reset circuit and processor,
Described processor comprises normal operating conditions and deadlock state; Described reset circuit comprises Keysheet module and the control module that resets, and described Keysheet module comprises a plurality of buttons, and described processor responds pressing of each button and carries out predetermined corresponding operating; When the predetermined key of the N in described Keysheet module was pressed simultaneously, the described control module output deadlock reset signal that resets was to described processor, so that described processor resets and recovers normal operating conditions, wherein, N is the natural number more than or equal to 2.
Further, the described control module that resets comprises timing unit, when the predetermined key of the N in described Keysheet module is pressed simultaneously, described timing unit begins timing, if timing reaches a time threshold, the described control module that resets is just exported the deadlock reset signal, otherwise the described control module that resets is exported non-deadlock reset signal.
Further, each button and the resistance string in N predetermined key in described key-press module is coupled between VDD-to-VSS; The described control module that resets also comprises arithmetic logic unit and N comparing unit, in N predetermined key in the corresponding described key-press module of each comparing unit one, each comparing unit compares with the button of correspondence with node voltage and predetermined voltage threshold between resistance that this button is connected, output the first comparison signal when the button of correspondence is not pressed, output the second comparison signal when the button of correspondence is pressed; Described arithmetic logic unit is used for the comparison signal of N comparing unit output is carried out logical operation, when a described N comparing unit is all exported the second comparison signal, described arithmetic logic unit output combination button signal, when described arithmetic logic unit output combination button signal, described timing unit begins timing.
Further, the normal phase input end of each comparing unit and corresponding button and be connected with node between resistance that this button is connected, the described predetermined voltage threshold of negative-phase input input.
Further, described electronic equipment also comprises electrify restoration circuit and the first logical operation circuit, and described electrify restoration circuit is exported power-on reset signal when system boot, when system boot is completed, export non-power-on reset signal; Or/and described resetting during control module output deadlock reset signal, described the first logical operation circuit is all exported new reset signal to the reset terminal of described processor, so that described processor reset when described electrify restoration circuit output power-on reset signal.
Further, the normal phase input end of each comparing unit and corresponding button and be connected with node between resistance that this button is connected, the described predetermined voltage of negative-phase input input, described arithmetic logic unit be first with the door, described first comprises N input end with door, and wherein each input end is connected with the output terminal of a comparing unit; The reset terminal of described timing unit is connected with the output terminal of door with first, its clock end input clock signal, its output terminal output deadlock reset signal; Described the first logical operation circuit be second with the door, an input end of described the first logical operation circuit is connected with the reset signal output terminal of described electrify restoration circuit, another input end is connected with the deadlock reset signal output terminal of the described control module that resets, and its output terminal is connected with the reset terminal of described processor.
Further, described electronic equipment also comprises the second logical operation circuit and electric power management circuit, described electric power management circuit provides power supply for described processor, when system produces power enable signal or the described control module that resets and exports the deadlock reset signal, described the second new power enable signal of logical operation circuit output is given described electric power management circuit, so that offering the power supply of described processor, described electric power management circuit restarts, so that described processor recovers normal operating conditions.
Further, the normal phase input end of each comparing unit and corresponding button and be connected with node between resistance that this button is connected, the described predetermined voltage of negative-phase input input, described arithmetic logic unit be first with the door, described first comprises N input end with door, and wherein each input end is connected with the output terminal of a comparing unit; The reset terminal of described timing unit is connected with the output terminal of door with first, its clock end input clock signal, its output terminal output deadlock reset signal; Described the second logical operation circuit be the 3rd with the door, an input end of described the second logical operation circuit is connected with the power enable signal that system produces, another input end is connected with the deadlock reset signal output terminal of the described control module that resets, and its output terminal is connected with the Enable Pin of described electric power management circuit.
Further, N equals 2.
Further, described electronic equipment is bluetooth earphone or panel computer.
Compared with prior art, electronic equipment in the utility model comprises reset circuit and processor, when the predetermined key of the N in described reset circuit is pressed simultaneously, described reset circuit output deadlock reset signal is given described processor, so that described processor resets and recovers normal operating conditions.Like this, not only save the cost that the deadlock reset key is set separately, and brought better user to experience to the client.
[description of drawings]
In order to be illustrated more clearly in the technical scheme of the utility model embodiment, during the below will describe embodiment, the accompanying drawing of required use is done to introduce simply, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.Wherein:
Fig. 1 is the structural representation of the electronic equipment in first embodiment of the present utility model;
Fig. 2 is the structural representation of the electronic equipment in second embodiment of the present utility model;
Fig. 3 is the structural representation of the electronic equipment in the 3rd embodiment of the present utility model; With
Fig. 4 is the structural representation of the electronic equipment in the 4th embodiment of the present utility model.
[embodiment]
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
Alleged " embodiment " or " embodiment " refer to be contained in special characteristic, structure or the characteristic at least one implementation of the utility model herein.Different local in this manual " in one embodiment " that occur not are all to refer to same embodiment, neither be independent or the embodiment mutually exclusive with other embodiment optionally.Unless stated otherwise, herein connection, the word that the expression that is connected, joins is electrically connected all represents directly or indirectly to be electrical connected.
Electronic equipment in the utility model comprises reset circuit and processor, when the predetermined key of the N in described reset circuit is pressed simultaneously, described reset circuit output deadlock reset signal is given described processor, so that described processor resets and recovers normal operating conditions.That is to say, the utility model is realized deadlock to the system control that resets by combination button, like this, has not only saved the cost that the deadlock reset key is set separately, and has brought better user to experience to the client.
Please refer to shown in Figure 1ly, it is the electrical block diagram of the electronic equipment in first embodiment of the present utility model.Described electronic equipment comprises reset circuit 110 and processor 120.
Described processor 120 comprises normal operating conditions and deadlock state.Described reset circuit 110 comprises Keysheet module 112 and the control module 114 that resets.Described Keysheet module 112 comprises a plurality of buttons, described processor 120 responds pressing of each button and carries out predetermined corresponding operating, when N predetermined key in described Keysheet module 112 pressed simultaneously, the described control module 114 output deadlock reset signal DeadRST that reset are to described processor 120, so that described processor 120 is resetted and recovers normal operating conditions, wherein, N is the natural number more than or equal to 2.
It should be noted that a plurality of buttons that described Keysheet module 112 comprises, wherein being set to N the predetermined key that is used as reset operation is not to reset and custom-designed in order to crash usually, and they are all the buttons with normal function.Such as, described key-press module 112 comprises that ON/OFF switch (being also referred to as power button), volume increase key, volume reduces the buttons commonly used such as key, receiving/hang-up button, wherein, can set ON/OFF switch and volume increase key is predetermined key, perhaps setting ON/OFF switch and volume, to reduce key be predetermined key, can set also that ON/OFF switch, volume increase key and the receiving/hang-up button is predetermined key, can set also that ON/OFF switch, volume increase key, volume reduces key and the receiving/hang-up button is predetermined key etc.When processor 120 was in normal operating conditions, described processor 120 can respond each button in described Keysheet module 112 and press action carrying out the predetermined function operation, such as, start, shutdown, volume increase, volume reduces, receiving/hang-up phone etc.Increase key as predetermined key as example to set ON/OFF switch and volume, in the use procedure of the system that adopts described electronic equipment, when if processor 120 is in normal operating conditions, the user can normally use each button of Keysheet module 112, such as, regulate volume, receiving/hang-up phone etc., if the deadlock state appears in processor 120, the user can increase key by ON/OFF switch and the volume of pressing simultaneously in described Keysheet module 112, so that described processor 120 is resetted and recovers normal operating conditions.One of the purpose that Macintosh in the utility model (being N the predetermined key that described Keysheet module 112 comprises) arranges or use are for fear of conflicting mutually with the normal function of these buttons.
In a preferred embodiment, the control module 114 that resets in electronic equipment shown in Figure 1 comprises timing unit, when N predetermined key in described Keysheet module 112 pressed simultaneously, described timing unit begins timing, if timing reaches a time threshold, the described control module 114 that resets is just exported deadlock reset signal DeadRST, otherwise the described control module 114 that resets is exported non-deadlock reset signals.That is to say, N predetermined key in described Keysheet module 112 pressed simultaneously, and after continuing for some time, just described processor 120 resetted.The purpose that timing unit is set is the false triggering that causes for fear of maloperation.The time threshold that general described timing unit arranges (being that Macintosh continues the button time) is 0.5S-100S, and the time is oversize, and it is not too convenient to use concerning the user.
Please refer to shown in Figure 2ly, it is the electrical block diagram of the electronic equipment in second embodiment of the present utility model.Also can say, it is a particular circuit configurations schematic diagram embodiment illustrated in fig. 1.
In this embodiment, described electronic equipment comprises reset circuit 210 and processor 220, and described reset circuit 210 comprises Keysheet module 212 and the control module 214 that resets.Described Keysheet module 212 comprises two predetermined key (being to suppose N=2 in this example), be respectively the first button Key1, the second button Key2, described the first button Key1 and the first resistance R pl1 are series between power supply VH and ground, described the second button Key2 and the second resistance R pl2 are series between power supply VH and ground, connected node between described the first button Key1 and the first resistance R pl1 is K1, and the connected node between described the second button Key2 and the second resistance R pl2 is K2.Wherein, power supply VH can be cell voltage, perhaps other supply voltage, perhaps higher voltage in charger voltage and cell voltage; Function or the effect of the first resistance R pl1 and the second resistance R pl2 be, when the first button Key1 and the second button Key2 were not pressed, the first resistance R pl1 and the 2nd Rpl2 discharged into ground with the voltage of node K1 and K2 respectively.
In the present embodiment, the control module that resets 214 comprise first with a door AND1(be arithmetic logic unit), timing unit Counter, and the first comparator C om1 and the second comparator C om2 (i.e. two comparing units).Wherein, corresponding the first button Key1 of the first comparator C om1, corresponding the second button Key2 of the second comparator C om2.The normal phase input end of the first comparator C om1 is connected with node K1, negative-phase input input predetermined voltage threshold VT, and it is used for voltage and the predetermined voltage threshold VT at comparison node K1 place, and exports corresponding comparison signal; The normal phase input end of the second comparator C om2 is connected with node K2, negative-phase input input predetermined voltage threshold VT, and it is used for voltage and the predetermined voltage threshold VT at comparison node K2 place, and exports corresponding comparison signal.In the present embodiment, the described predetermined voltage threshold VT of design is less than the magnitude of voltage of power supply VH.When the first button Key1 was not pressed, the comparison signal KH1 of the first comparator C om1 output was low level (i.e. the first comparison signal); When the first button Key1 was pressed, the comparison signal KH1 of the first comparator C om1 output was high level (i.e. the second comparison signal).In like manner, when the second button Key2 was not pressed, the comparison signal KH2 of the second comparator C om2 output was low level (i.e. the first comparison signal); When the second button Key2 was pressed, the comparison signal KH2 of the second comparator C om2 output was high level (i.e. the second comparison signal).
Described first with the first input end of door AND1 be connected input end respectively with the output terminal of the first comparator C om1 be connected the output terminal of comparator C om2 and be connected, it is used for the comparison signal of the first comparator C om1 and the second comparator C om2 output is carried out logical operation, when the comparison signal of two comparers output be all high level (i.e. the second comparison signal), described first a signal KON who exports with an AND1 was high level (combination button signal); When the comparison signal of arbitrary output in two comparers is low level, described first with the signal KON of door AND1 output be low level (being non-combination button signal).
The reset terminal RST of described timing unit Counter is connected with the output terminal of door AND1 with described first, its clock end CK input clock signal CLK, and output terminal Q is connected with processor 120.Below specifically introduce the course of work of described timing unit Counter: when being low level (being non-combination button signal) when described first with a signal KON of AND1 output, the signal of the output terminal Q output of described timing unit Counter is high level (being non-deadlock reset signal); When being high level (being the combination button signal) when described first with a signal KON of AND1 output, described timing unit Counter begins timing, when timing reached a time threshold, the signal saltus step of its output terminal Q output was low level (reset signal that namely crashes DeadRST).That is to say, when exporting combination button signal (namely the first button Key1 and the second button Key2 are pressed) when described first with door AND1, described timing unit Counter begins timing, if timing reaches a time threshold, described timing unit Counter just exports deadlock reset signal DeadRST, so that described processor resets and recovers normal operating conditions, otherwise, the non-deadlock reset signal of described timing unit Counter output.
In another embodiment, described the first comparator C om1 and described the second comparator C om2 also can be replaced by the Schmidt trigger of built-in reference voltage, as long as the turn threshold voltage of Schmidt trigger is lower than the magnitude of voltage of power supply VH.
What the those of ordinary skill in affiliated field was easily expected is, the normal phase input end of described the first comparator C om1 and the connected node of negative-phase input can be exchanged, be described the first comparator C om1 input predetermined voltage threshold VT, its negative-phase input is connected with node K1; In like manner, also can be with described the second comparator C om2 input predetermined voltage threshold VT, its negative-phase input is connected with node K2, at this moment, first also will replace accordingly with door AND1 and timing unit Counter, to realize making described processor 220 reset and recover normal operating conditions when the first button Key1 and the second button Key2 are pressed simultaneously; Also the predetermined key in the Keysheet module 212 in electronic equipment shown in Figure 2 can be increased to 3,4 or more, as long as this combination button is convenient to user's operation.that is to say, described key-press module 212 can comprise N predetermined key, and wherein each button and a resistance string are coupled between VDD-to-VSS, the described control module 214 that resets comprises arithmetic logic unit, a timing unit and N comparing unit, in N predetermined key in the corresponding described key-press module 212 of each comparing unit one, each comparing unit compares with the button of correspondence with node voltage and predetermined voltage threshold between resistance that this button is connected, output the first comparison signal when the button of correspondence is not pressed, output the second comparison signal when the button of correspondence is pressed, described arithmetic logic unit is used for the comparison signal of N comparator circuit output is carried out logical operation, when a described N comparator circuit is all exported the second comparison signal, described arithmetic logic unit output combination button signal, when described arithmetic logic unit output combination button signal, described timing module begins timing, if timing reaches a time threshold, described timing unit is just exported deadlock reset signal DeadRST, so that described processor 220 resets and recovers normal operating conditions, otherwise, described timing unit Counter exports non-deadlock reset signal.
Please refer to shown in Figure 3ly, it is the electrical block diagram of the electronic equipment in the 3rd embodiment of the present utility model.It also has the electrification reset function when having the combination button reset function.
Electronic equipment in Fig. 3 and the something in common in Fig. 2 be, this electronic equipment all includes Keysheet module 312, the control module that resets 314, processor 320.Electronic equipment in Fig. 3 and the difference in Fig. 2 are, the former also comprise electrify restoration circuit 330 and second and the door AND2(or be referred to as the first logical operation circuit), described second is connected with the output terminal of described electrify restoration circuit 330 with the input end of door AND2, another input end is connected with the output terminal of timing unit Counter, and its output terminal is connected with the reset terminal RST of described processor 320.
In prior art, the output terminal of described electrify restoration circuit 330 can directly be connected with the reset terminal RST of described processor 320, described electrify restoration circuit 330 output power-on reset signal POR when system boot, so that described processor 320 is carried out electrification reset, when system boot is completed, it exports non-power-on reset signal, and described processor 320 begins normal operation.In the present embodiment, an input end input starting-up signal PWR of described electrify restoration circuit 330, another input end input clock signal CLK, this clock signal clk is used for timing.The start process of system is the process of each road supply voltage from zero start to the normal voltage value of system.During start, system produces starting-up signal PWR, make described electrify restoration circuit 130 output low level signals (being power-on reset signal POR), before each road supply voltage does not reach normal output voltage, described electrify restoration circuit 330 is the output low level signal always, and after each road supply voltage reached normal output voltage, described electrify restoration circuit 330 continued output low level signal a period of time, for example after 50mS, just become high level signal (being non-power-on reset signal).When described electrify restoration circuit 330 always during output low level signal (being power-on reset signal POR), described processor 320(for example, ARM core) can keep being reset state always, until after described electrify restoration circuit 330 output high level signals, described processor 320 just begins normal operation.
Please continue with reference to shown in Figure 3, when described timing unit Counter output low level signal (deadlock reset signal DeadRST) and/or described electrify restoration circuit 330 output low level signals (power-on reset signal POR), described state second all can output low level signal (new reset signal POR-New) with door AND2, described processor 320 is resetted.That is to say, described second with the door AND2 effect be, as described electrify restoration circuit 330 output power-on reset signal POR or/and described resetting during control module 314 output deadlock reset signal DeadRST, described second with i.e. the first logical operation circuit of door AND2() all export new reset signal (POR-New) to the reset terminal RST of described processor 320, so that described processor 320 resets.
Similar to Fig. 2, also the predetermined key in the Keysheet module 312 in electronic equipment shown in Figure 3 can be increased to 3,4 or more, as long as this combination button is convenient to user's operation.
Please refer to shown in Figure 4ly, it is the electrical block diagram of the electronic equipment in the 4th embodiment of the present utility model.It also has the function that resets by restarting power supply when having the combination button reset function.
The something in common of Fig. 4 and Fig. 2 is, the electronic equipment in Fig. 4 also comprises Keysheet module 412, the control module that resets 414 and processor 420.The difference of Fig. 4 and Fig. 2 is, the former also comprise electric power management circuit 440 and the 3rd with door AND3(second logical operation circuit).The described the 3rd with the door AND3 an input end input power enable signal PMU_EN, another input end is connected with the output terminal of described timing unit Counter; The Enable Pin EN of electric power management circuit 440 is connected with the output terminal of door AND3 with the 3rd, and its power end VO is connected with the power end VDD of described processor 420.
In prior art, when described processor 420 is in the deadlock state, the power enable signal PMU-EN that system produces directly can be inputted the Enable Pin EN of described electric power management circuit 440, the power supply that described electric power management circuit 440 is offered described processor 420 restarts, so that described processor 420 recovers normal operating conditions.The process of wherein restarting the supply voltage VDD of described processor 420 is that described electric power management circuit 440 is first closed the supply voltage VDD of described processor 420, then controls the supply voltage VDD of described processor 420 again from zero start to the normal voltage value.For example, when power enable signal PMU_EN signal is low level, make described electric power management circuit 440 offer each road power-off of described processor 420, make processor 420 be in off-mode; When power enable signal PMU_EN saltus step is high level, make described electric power management circuit 440 offer described processor 420 each road power initiation output normal working voltages, make processor 420 enter normal operating conditions.
Please continue with reference to shown in Figure 4, be low level in the present embodiment when described timing unit Counter output low level signal (deadlock reset signal DeadRST) and/or system produce power enable signal PMU_EN(), described state the 3rd all can output low level signal (new power enable signal PMU-EN-New) with door AND3, the power supply that makes described electric power management circuit 440 offer described processor 420 restarts.That is to say, the described the 3rd with the door AND3 effect be, when system produces power enable signal PMU_EN or/and described resetting during control module 414 output deadlock reset signal DeadRST, the described the 3rd with i.e. the second logical operation circuit of door AND3() all export new power enable signal (PMU-EN-New), the power supply that makes described electric power management circuit 440 offer described processor 420 restarts.
Similar to Fig. 2, also the predetermined key in the Keysheet module 412 in electronic equipment shown in Figure 4 can be increased to 3,4 or more, as long as this combination button is convenient to user's operation.
The smart machines such as existing bluetooth earphone, panel computer, because volume is very little, the very tight exquisiteness of its physical arrangement, when it the deadlock state occurs, domestic consumer's inconvenience resets to it by the mode of plug battery, therefore, the electronic equipment in the utility model can be embodied as the smart machines such as bluetooth earphone, panel computer, these smart machines just can be realized reset function easily like this, thereby bring better user to experience to the client.
In sum, electronic equipment in the utility model comprises reset circuit and processor, when the predetermined key of the N in described reset circuit was pressed simultaneously, described reset circuit output deadlock reset signal was given described processor, so that described processor resets and recovers normal operating conditions.That is to say, the utility model is realized deadlock to the system control that resets by combination button.In addition, system-halted reset device in the utility model also supports to pass through system boot, system is carried out electrification reset, and also support to restart by the power enable signal that system produces the power supply of the described circuit that is reset, so that the described circuit that is reset recovers normal operating conditions.Like this, not only save the cost that the deadlock reset key is set separately, and brought better user to experience to the client.
In the utility model, the word that the expression such as " connection ", " being connected ", " company ", " connecing " is electrically connected if no special instructions, represents direct or indirect electric connection.CLK in accompanying drawing is clock signal, and DATA is data-signal.
It is pointed out that being familiar with any change that the person skilled in art does embodiment of the present utility model does not all break away from the scope of claims of the present utility model.Correspondingly, the scope of claim of the present utility model also is not limited only to previous embodiment.
Claims (10)
1. an electronic equipment, is characterized in that, it comprises reset circuit and processor,
Described processor comprises normal operating conditions and deadlock state;
Described reset circuit comprises Keysheet module and the control module that resets,
Described Keysheet module comprises a plurality of buttons, and described processor responds pressing of each button and carries out predetermined corresponding operating;
When the predetermined key of the N in described Keysheet module was pressed simultaneously, the described control module output deadlock reset signal that resets was to described processor, so that described processor resets and recovers normal operating conditions,
Wherein, N is the natural number more than or equal to 2.
2. electronic equipment according to claim 1, it is characterized in that, the described control module that resets comprises timing unit, when the predetermined key of the N in described Keysheet module is pressed simultaneously, described timing unit begins timing, if timing reaches a time threshold, the described control module that resets is just exported the deadlock reset signal, otherwise the described control module that resets is exported non-deadlock reset signal.
3. electronic equipment according to claim 2, is characterized in that, each button in the predetermined key of the N in described key-press module and a resistance string are coupled between VDD-to-VSS;
The described control module that resets also comprises arithmetic logic unit and N comparing unit,
In N predetermined key in the corresponding described key-press module of each comparing unit one, each comparing unit compares with the button of correspondence with node voltage and predetermined voltage threshold between resistance that this button is connected, output the first comparison signal when the button of correspondence is not pressed, output the second comparison signal when the button of correspondence is pressed;
Described arithmetic logic unit is used for the comparison signal of N comparing unit output is carried out logical operation, when a described N comparing unit is all exported the second comparison signal, and described arithmetic logic unit output combination button signal,
When described arithmetic logic unit output combination button signal, described timing unit begins timing.
4. electronic equipment according to claim 3, is characterized in that, the normal phase input end of each comparing unit and corresponding button and be connected with node between resistance that this button is connected, the described predetermined voltage threshold of negative-phase input input.
5. electronic equipment according to claim 3, is characterized in that, described electronic equipment also comprises electrify restoration circuit and the first logical operation circuit,
Described electrify restoration circuit is exported power-on reset signal when system boot, when system boot is completed, export non-power-on reset signal;
Or/and described resetting during control module output deadlock reset signal, described the first logical operation circuit is all exported new reset signal to the reset terminal of described processor, so that described processor reset when described electrify restoration circuit output power-on reset signal.
6. electronic equipment according to claim 5, is characterized in that, the normal phase input end of each comparing unit and corresponding button and be connected with node between resistance that this button is connected, and the described predetermined voltage of negative-phase input input,
Described arithmetic logic unit be first with the door, described first with the door comprise N input end, wherein each input end is connected with the output terminal of a comparing unit;
The reset terminal of described timing unit is connected with the output terminal of door with first, its clock end input clock signal, its output terminal output deadlock reset signal;
Described the first logical operation circuit be second with the door, an input end of described the first logical operation circuit is connected with the reset signal output terminal of described electrify restoration circuit, another input end is connected with the deadlock reset signal output terminal of the described control module that resets, and its output terminal is connected with the reset terminal of described processor.
7. electronic equipment according to claim 3, is characterized in that, described electronic equipment also comprises the second logical operation circuit and electric power management circuit,
Described electric power management circuit provides power supply for described processor,
When system produces power enable signal or the described control module that resets and exports the deadlock reset signal, described the second new power enable signal of logical operation circuit output is given described electric power management circuit, so that offering the power supply of described processor, described electric power management circuit restarts, so that described processor recovers normal operating conditions.
8. processor according to claim 7, is characterized in that, the normal phase input end of each comparing unit and corresponding button and be connected with node between resistance that this button is connected, and the described predetermined voltage of negative-phase input input,
Described arithmetic logic unit be first with the door, described first with the door comprise N input end, wherein each input end is connected with the output terminal of a comparing unit;
The reset terminal of described timing unit is connected with the output terminal of door with first, its clock end input clock signal, its output terminal output deadlock reset signal;
Described the second logical operation circuit be the 3rd with the door, an input end of described the second logical operation circuit is connected with the power enable signal that system produces, another input end is connected with the deadlock reset signal output terminal of the described control module that resets, and its output terminal is connected with the Enable Pin of described electric power management circuit.
9. according to claim 1-8 arbitrary described electronic equipments, is characterized in that, N equals 2.
10. electronic equipment according to claim 9, is characterized in that, described electronic equipment is bluetooth earphone or panel computer.
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| CN 201220719557 CN202995614U (en) | 2012-12-24 | 2012-12-24 | Electronic equipment |
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| CN 201220719557 CN202995614U (en) | 2012-12-24 | 2012-12-24 | Electronic equipment |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066969A (en) * | 2012-12-24 | 2013-04-24 | 无锡中星微电子有限公司 | Electronic equipment |
| CN103561167A (en) * | 2013-10-22 | 2014-02-05 | 小米科技有限责任公司 | Device, method and terminal equipment for restarting after dead halt |
| CN104298568A (en) * | 2013-07-19 | 2015-01-21 | 中兴通讯股份有限公司 | User terminal outage control method and system |
| CN105138323A (en) * | 2015-08-06 | 2015-12-09 | 联想(北京)有限公司 | Information processing method and electronic equipment |
| CN105279041A (en) * | 2015-11-11 | 2016-01-27 | 广东欧珀移动通信有限公司 | Method and device for automatically rebooting terminal after crash of terminal |
| CN110221671A (en) * | 2019-04-25 | 2019-09-10 | 维灵（杭州）信息技术有限公司 | A kind of false-touch prevention bill key hardware reset method, chip and wearable device |
-
2012
- 2012-12-24 CN CN 201220719557 patent/CN202995614U/en not_active Withdrawn - After Issue
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066969A (en) * | 2012-12-24 | 2013-04-24 | 无锡中星微电子有限公司 | Electronic equipment |
| CN104298568A (en) * | 2013-07-19 | 2015-01-21 | 中兴通讯股份有限公司 | User terminal outage control method and system |
| CN103561167A (en) * | 2013-10-22 | 2014-02-05 | 小米科技有限责任公司 | Device, method and terminal equipment for restarting after dead halt |
| CN105138323A (en) * | 2015-08-06 | 2015-12-09 | 联想(北京)有限公司 | Information processing method and electronic equipment |
| CN105138323B (en) * | 2015-08-06 | 2019-10-29 | 联想(北京)有限公司 | A kind of information processing method and electronic equipment |
| CN105279041A (en) * | 2015-11-11 | 2016-01-27 | 广东欧珀移动通信有限公司 | Method and device for automatically rebooting terminal after crash of terminal |
| CN105279041B (en) * | 2015-11-11 | 2018-06-22 | 广东欧珀移动通信有限公司 | A kind of method and device restarted automatically after terminal crash |
| CN110221671A (en) * | 2019-04-25 | 2019-09-10 | 维灵（杭州）信息技术有限公司 | A kind of false-touch prevention bill key hardware reset method, chip and wearable device |
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