CN203117961U - Dead halt monitoring and resetting device - Google Patents
Dead halt monitoring and resetting device Download PDFInfo
- Publication number
- CN203117961U CN203117961U CN 201220706096 CN201220706096U CN203117961U CN 203117961 U CN203117961 U CN 203117961U CN 201220706096 CN201220706096 CN 201220706096 CN 201220706096 U CN201220706096 U CN 201220706096U CN 203117961 U CN203117961 U CN 203117961U
- Authority
- CN
- China
- Prior art keywords
- circuit
- deadlock
- button
- reset
- resetting means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The utility model provides a dead halt monitoring and resetting device which comprises a first circuit, a second circuit and a keyboard module, wherein the first circuit has no dead halt state, the second circuit has the dead halt state and normal working state, when keys in the keyboard module are pressed down, the first circuit starts detecting whether the second circuit is under dead halt state, and when the second circuit is under dead halt state, the second circuit is controlled by the first circuit to reset the normal working state. Compared with the prior art, the dead halt monitoring and resetting device can realize that the possible dead halt state can be found in time when a user conducts the normal function operation of keys so as to reset the system and overcome the influence of the dead halt on the use of the user in time, the frequent communication between the first circuit and the second circuit is not needed, and the energy consumption caused by the frequent communication can be reduced.
Description
[technical field]
The utility model relates to circuit design field, particularly a kind of deadlock monitoring and resetting means.
[background technology]
Various intelligence system of the prior art, bluetooth earphone for example, panel computer, smart mobile phone, intelligent television, PC, notebook computer, individual Medical Devices etc., the processors that adopt are controlled more.At present, widely used processor has low-power consumption ARM (Advanced RISC Machine, abbreviation ARM) nuclear, Intel CPU (Center Processor Unit), AMD CPU or MIPS (Million Instructions PerSecond) system etc., such as, ARM-A8.These processors may occur crashing when some abnormality.For example, when one of appearance on its supply voltage was seriously jumped down, when error in address appearred in access memory during perhaps owing to variations such as neighbourhood noise or temperature, perhaps owing to falling when causing some circuit moment loose contact, processor all may crash.And after the processor deadlock, need start shooting again and could recover by the plug battery.And smart machines such as existing bluetooth earphone, panel computer, because volume is very little, the very tight exquisiteness of its physical arrangement, the dismounting of inconvenient domestic consumer, unloading process very easily causes the physical unit loss, and therefore, domestic consumer generally can't dismantle battery.Though it is very little that the probability of deadlock takes place, if take place, consequence is very serious.Because battery is built-in, is inconvenient to dismantle, system is in the deadlock state always like this, after the electric weight of battery is depleted fully, charges again, the deadlock state could be resetted like this.Because popular low power dissipation design all at present, battery is given out light voluntarily and is taken for a long time, makes customer experience very bad like this.
Therefore be necessary to provide a kind of improved technical scheme to overcome the problems referred to above.
[utility model content]
The purpose of this utility model is to provide a kind of deadlock monitoring and resetting means, and it can be realized the deadlock monitoring of system and the control that resets by the button in this device, thereby bring better user to experience to the client.
In order to address the above problem, the utility model provides a kind of deadlock monitoring and resetting means, it comprises first circuit, second circuit and Keysheet module, described first circuit state that do not crash, described second circuit has deadlock state and normal operating conditions, when the button in the described Keysheet module is pressed, described first circuit begins to detect described second circuit and whether is in the deadlock state, when described second circuit was in the deadlock state, described first circuit was controlled described second circuit and is recovered normal operating conditions.
Further, when the button in the described Keysheet module was pressed, whether the described second circuit of described first electric circuit inspection sent correct response signal, if, judge that then described second circuit is in normal operating conditions, if not, judge that then described second circuit is in the deadlock state.
Further, be provided with communication channel and reset passages between described first circuit and the described second circuit,
Described second circuit sends to described first circuit by described communication port with response signal, and described first circuit is controlled described second circuit by described reset passages and recovered normal operating conditions.
Further, second circuit stores the corresponding check value for each button, when described second circuit is in normal operating conditions, when a button of described Keysheet module is pressed, described second circuit sends the response signal of its corresponding proof test value of expression and gives first circuit, and first circuit determines based on this proof test value whether described second circuit sends correct response signal.
Further, first circuit stores corresponding initial value for each button, when described second circuit is in normal operating conditions, when a button of described Keysheet module is pressed, described second circuit reads the initial value of the button correspondence of pressing from first circuit, and obtain proof test value after subscribing computing according to described initial value, send the response signal of this proof test value of expression subsequently and give first circuit, first circuit determines based on this proof test value whether described second circuit sends correct response signal.
Further, include a plurality of buttons in the described Keysheet module, each button and a resistance string are coupled between power supply and the ground, node between each button and the connected resistance links to each other with the push button signalling input end of first circuit and the push button signalling input end of second circuit simultaneously, when a button is pressed, a corresponding push button signalling be will produce and first circuit and second circuit given, so that described second circuit sends response signal to described first circuit, make whether described this response signal of first electric circuit inspection is correct response signal.
Further, described communication channel comprises serial data line and the serial time clock line that is arranged between described first circuit and the second circuit, and described serial time clock line links to each other with power supply by first resistance, and described serial data line links to each other with power supply by second resistance.
Further, described reset passages connects the reset signal output terminal of described first circuit and the reset terminal of second circuit, when judging that described second circuit is in the deadlock state, described first circuit enters normal operating conditions by the reset terminal of reset signal output terminal output reset signal to described second circuit to reactivate described second circuit.
Further, described first circuit is electric power management circuit, and described second circuit is processor.
Further, described reset passages connects the power output end of described first circuit and the power end of described second circuit, described first circuit provides power supply for described second circuit, when the deadlock state appearred in described second circuit, the power supply that described first circuit will offer second circuit restarted.
Further again, described first circuit is electric power management circuit, and described second circuit is processor.
Further again, described deadlock monitoring and resetting means are used for bluetooth earphone or panel computer, and when second circuit was in normal operating conditions, described second circuit responded the action of pressing of each button of described Keysheet module and operates to carry out predetermined function.
Compared with prior art, deadlock monitoring and resetting means in the utility model comprise first circuit, second circuit and Keysheet module, when a button of described Keysheet module is pressed, described first circuit begins to detect described second circuit and whether is in the deadlock state, when described second circuit was in the deadlock state, described first circuit was controlled described second circuit and is recovered normal operating conditions.Reset mode of the present utility model is simple, easy to operate, thereby brings better user to experience to the client.
[description of drawings]
In order to be illustrated more clearly in the technical scheme of the utility model embodiment, the accompanying drawing of required use is done to introduce simply in will describing embodiment below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.Wherein:
Fig. 1 is deadlock monitoring among first embodiment of the present utility model and the structural representation of resetting means;
Fig. 2 a is deadlock monitoring among second embodiment of the present utility model and the structural representation of resetting means;
Fig. 2 b is deadlock monitoring among the 3rd embodiment of the present utility model and the structural representation of resetting means;
Fig. 3 a is deadlock monitoring among the 4th embodiment of the present utility model and the structural representation of resetting means; With
Fig. 3 b is deadlock monitoring among the 5th embodiment of the present utility model and the structural representation of resetting means.
[embodiment]
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments the utility model is described in further detail.
Alleged " embodiment " or " embodiment " refers to be contained in special characteristic, structure or the characteristic at least one implementation of the utility model herein.Different local in this manual " in one embodiment " that occur not are all to refer to same embodiment, neither be independent or the embodiment mutually exclusive with other embodiment optionally.Unless stated otherwise, the word that connection herein, the expression that links to each other, joins electrically connect is all represented directly or indirectly to be electrical connected.
Deadlock monitoring in the utility model and resetting means are realized the deadlock monitoring of system and the control that resets by the button in this device, when button is pressed, first circuit that can not crash and the second circuit that may crash are communicated, monitor with the state to second circuit, when second circuit can not send correct response signal to first circuit, can judge that namely second circuit is in the deadlock state, at this moment, control described second circuit by described first circuit and recover normal operating conditions.Reset mode of the present utility model is simple, easy to operate, thereby brings better user to experience to the client.In addition, the utility model can be realized when the user carries out the normal function operation of button, in time find possible deadlock state, system is resetted, crash to the influence of client's use with timely solution, and need not first circuit and frequently communicate by letter with second circuit, reduce the energy consumption that frequent communication causes.
Please refer to shown in Figure 1ly, it is deadlock monitoring among first embodiment of the present utility model and the electrical block diagram of resetting means.Described deadlock monitoring and resetting means comprise first circuit 110, second circuit 120 and Keysheet module 130, described first circuit 110 state that do not crash, and described second circuit 120 has deadlock state and normal operating conditions.When the button Keyn of described Keysheet module 130 is pressed, described first circuit 110 begins to detect described second circuit 120 and whether is in the deadlock state, when described second circuit 120 was in the deadlock state, the described second circuit 120 of described first circuit 110 controls recovered normal operating conditions.Detailed process is: when the button Keyn of described Keysheet module 130 is pressed, described first circuit 110 detects described second circuit 120 and whether sends correct response signal, if, judge that then described second circuit 120 is in normal operating conditions, if not, judge that then described second circuit 120 is in the deadlock state.
The button Keyn that it should be noted that described Keysheet module 130 to detect in order crashing and to reset and custom-designed, and they all are the buttons with normal function, such as volume control button, receiving/hang-up button etc.That is to say that when second circuit 120 was in normal operating conditions, described second circuit 120 can respond the action of pressing of each button of described Keysheet module and operate to carry out predetermined function, such as regulating volume, receiving/hang-up phone etc.Specifically, in the use of the system that adopts described deadlock monitoring and resetting means, when if second circuit 120 is in normal operating conditions, the user can normally use each button of Keysheet module 130, such as regulating volume, receiving/hang-up phone etc., if the deadlock state appears in second circuit 120, during the button of user on the normal Keysheet module 130 that uses in this system, first circuit 110 will detect second circuit 120 and be in the deadlock device, thereby control second circuit 120 resets.
In the present embodiment, be provided with communication channel and reset passages between described first circuit 110 and the described second circuit 120, described second circuit 120 sends to described first circuit 110 by described communication port with response signal, and described first circuit 110 is controlled described second circuit 120 by described reset passages and recovered normal operating conditions.
Please refer to shown in Fig. 2 a, it is deadlock monitoring among second embodiment of the present utility model and the electrical block diagram of resetting means.
In the present embodiment, include a plurality of buttons in the described Keysheet module 130, each button and a resistance string are coupled between power supply and the ground, node between each button and the connected resistance links to each other with the push button signalling input end of first circuit 110 and the push button signalling input end of second circuit 120 simultaneously, when a button is pressed, a corresponding push button signalling be will produce and first circuit 110 and second circuit 120 given, so that described second circuit 120 sends response signal to described first circuit 110, make described first circuit 110 detect whether this response signal is correct response signal.Only show among Fig. 2 a a button Keyn in circuit with the electrical connection of other devices, n is natural number.The link of this button Keyn links to each other with power supply VH, another link is by a pull down resistor Rpln ground connection, the node of button Keyn and pull down resistor Rpln links to each other with the push button signalling input end Kn1 of first circuit and the push button signalling input end Kn2 of second circuit simultaneously, when button Keyn is pressed, a corresponding push button signalling Kn be will produce and first circuit 110 and second circuit 120 given, so that described second circuit 120 sends response signal to described first circuit 110, make described first circuit 110 detect whether this response signal is correct response signal.
Described correct response signal is unique digital signal of each button correspondence in the predefined described Keysheet module, and specific implementation has a variety of.
In one embodiment, second circuit 120 stores the corresponding check value for each button, when described second circuit 120 is in normal operating conditions, when a button of described Keysheet module 130 is pressed, described second circuit 120 sends the response signal of its corresponding proof test value of expression and determines based on this proof test value whether described second circuit 120 sends correct response signal for first circuit, 110, the first circuit 110.For example, when described second circuit 120 was in normal operating conditions, in the time of can designing button Key1 and be pressed, second circuit 120 sent 0001 binary data to first circuit 110; When button Key2 was pressed, second circuit 120 sent 0010 binary data to first circuit 110; When button Key3 was pressed, second circuit 120 sent 0011 binary data to first circuit 110; ...; When button Keyn was pressed, second circuit 120 sent the binary data of n correspondence to first circuit 110.
In another embodiment, first circuit 110 stores corresponding initial value for each button, when described second circuit 120 is in normal operating conditions, when a button of described Keysheet module 130 is pressed, described second circuit 120 reads the initial value of the button correspondence of pressing from first circuit 110, and obtain proof test value after subscribing computing according to described initial value, sending the response signal of this proof test value of expression subsequently determines based on this proof test value whether described second circuit 120 sends correct response signal for first circuit, 110, the first circuit 110.For example, when described second circuit 120 is in normal operating conditions, in the time of can designing button Key1 and be pressed, second circuit 120 reads the mode register data (initial value of the button correspondence of namely pressing) of setting from first circuit 110 earlier, after adding 0001 binary data (namely subscribing computing) then, send to first circuit 110; When button Key2 was pressed, second circuit 120 read the mode register data of setting from first circuit 110 earlier, add 0010 binary data then after, send to first circuit 110; ...; When button Keyn was pressed, second circuit 120 read the mode register data of setting from first circuit 110 earlier, add the binary data of n correspondence then after, send to first circuit 110.
In the present embodiment, the standard I 2C agreement that adopts described communication channel realizes the communication between first circuit 110 and the second circuit 120, be that described communication channel comprises the serial data line SDA(Serial Data that is arranged between described first circuit 110 and the second circuit 120) and serial time clock line SCL(Serial Clock), described serial time clock line SCL links to each other with power supply VH by the first resistance R ph1, and described serial data line SDA links to each other with power supply VH by the second resistance R ph2.The first resistance R ph1 and the second resistance R ph2 are the pull-up resistor of I2C protocol requirement, its resistance can for 100 ohm to the value between 100K ohm.In order to simplify description, the utility model omits about described communication channel and adopts the principle of work of standard I 2C agreement to describe.In other embodiments, communication channel between first circuit 110 and the second circuit 120 also can adopt any communication protocol of prior art, also can define any type of communicating requirement voluntarily, as long as can realize when the button of described Keysheet module is pressed, described second circuit sends response signal to described first circuit, and whether described this response signal of first electric circuit inspection is that correct response signal gets final product.
In the embodiment shown in Fig. 2 a, described reset passages connects the reset signal output terminal POR of first circuit 110 and the reset terminal RST of second circuit 120.When judging that second circuit 120 is in the deadlock state, first circuit 110 enters normal operating conditions by the reset terminal RST of reset signal output terminal POR output reset signal to second circuit 120 to reactivate second circuit 120.
Please refer to shown in Fig. 2 b, it is deadlock monitoring among the 3rd embodiment of the present utility model and the circuit diagram of resetting means.Its communication mode is identical with Fig. 2 a.The difference of itself and Fig. 2 a is that described reset passages connects the power output end VO of first circuit 110 and the power end VDD of second circuit 120.That is to say that described first circuit 110 provides power supply for second circuit 120, when the deadlock state appearred in described second circuit 120, the power supply that first circuit 110 will offer second circuit 120 restarted, so that second circuit 120 recovers normal operating conditions.The process of wherein restarting the supply voltage VDD of second circuit 120 is, first circuit 110 is closed the supply voltage VDD of second circuit 120 earlier, the supply voltage VDD that controls second circuit 120 then again from zero start to the normal voltage value.If there are a plurality of power supplys in second circuit 120, when resetting by the power supply of restarting second circuit 120, need earlier all power supplys of second circuit 120 to be closed simultaneously, re-power again and carry out reset operation.
What easily full of beard reached is, first circuit 110 and second circuit 120 can be two chips, communicate and reset operation by the signal that connects each other, also can design on same chip, connect to realize communication and reset operation (shown in Fig. 2 a and Fig. 2 b) by some signal wires.
Smart machines such as existing bluetooth earphone, panel computer, because volume is very little, the very tight exquisiteness of its physical arrangement, when it the deadlock state occurs, domestic consumer's inconvenience resets to it by the mode of plug battery, therefore, above-mentioned deadlock monitoring and resetting means can be applied in the smart machines such as bluetooth earphone, panel computer, automatically reset with realization, it is better to make product experience.
Please refer to shown in Fig. 3 a, it is deadlock monitoring among the 4th embodiment of the present utility model and the circuit diagram of resetting means, and this crash monitoring and resetting means are for bluetooth earphone or panel computer.The difference of itself and Fig. 2 a is that first circuit is the electric power management circuit 310(Power Management Unit in the system, is called for short PMU), second circuit is the processor 320 in the system, for example, ARM-A8.Because electric power management circuit 310 does not exist as complex state machine such as ARM, so it the deadlock state can not occur.And processor 320 may occur crashing when some abnormality.For example, when one of appearance on its supply voltage is seriously jumped down, perhaps under some situation because when error in address appearred in access memory during variation such as neighbourhood noise or temperature, perhaps owing to falling when causing some circuit moment loose contact, processor 320 all may crash.
For the ease of understanding, below specifically introduce the deadlock monitoring shown in Fig. 3 a and the course of work of resetting means.
Communication channel between electric power management circuit 310 and the processor 310 adopts standard I
2The C agreement.Reset passages between electric power management circuit 310 and the processor 320 connects the reset signal output terminal POR of electric power management circuit 310 and the reset terminal RSTN of processor 320.When button Keyn was not pressed, pull down resistor Rpln discharged into ground with the voltage of the connected node between button Keyn and the pull down resistor Rpln; When button Keyn is pressed, the voltage of the connected node between button Keyn and the pull down resistor Rpln is high level (voltage VH) by low level (ground level) saltus step, namely when button Keyn is pressed, described Keysheet module 330 output key signal Kn(high level signals), and with this high level signal be input to electric power management circuit 310 and processor 320.At this moment, if described processor 320 is in normal operating conditions, then can sends correct response signal and give described electric power management circuit 310, if described processor 320 is in the deadlock state, then can not sends correct response signal and give described electric power management circuit 310; If what electric power management circuit 310 detected described processors 320 sent is correct response signal, then do not produce reset signal POR; If what electric power management circuit 310 detected described processors 320 sent is not correct response signal, then produce reset signal POR, the processor 320 that is in the deadlock state is resetted.
Please refer to shown in Fig. 3 b, it is deadlock monitoring among the 5th embodiment of the present utility model and the circuit diagram of resetting means.This deadlock monitoring and resetting means also can be used for bluetooth earphone or panel computer.The difference of itself and Fig. 3 a is that the reset passages of electric power management circuit 310 and processor 320 is connected the power output end VO of electric power management circuit 310 and the power end VDD of processor 320.That is to say, described electric power management circuit 310 provides power supply for processor 320, when the deadlock state appearred in described processor 320, the power supply that described electric power management circuit 310 will offer processor 320 restarted, so that processor 320 recovers normal operating conditions.
In sum, deadlock monitoring in the utility model and resetting means are realized the deadlock monitoring of system and the control that resets by the button in this device, when a button is pressed, first circuit that can not crash and the second circuit that may crash are communicated, monitor with the state to second circuit, when second circuit can not send correct response signal to first circuit, can judge that namely second circuit is in the deadlock state, at this moment, control described second circuit by described first circuit and recover normal operating conditions.The utility model can be realized when the user carries out the normal function operation of button, in time find possible deadlock state, system is resetted, crash to the influence of client's use with timely solution, and need not first circuit and frequently communicate by letter with second circuit, reduce the energy consumption that frequent communication causes.
Those of ordinary skill in the affiliated field can be understood that, above only be that the deadlock monitoring in the utility model and resetting means are applied to the bluetooth earphone system, also the deadlock monitoring in the utility model and resetting means can be applied in other intelligent processor in fact, so that its reset mode is simple, easy to operate, thereby bring better user to experience to the client.
In the utility model, the word that expression such as " connection ", " linking to each other ", " company ", " connecing " electrically connects if no special instructions, is then represented direct or indirect electric connection.CLK in the accompanying drawing is clock signal, and DATA is data-signal.
It is pointed out that and be familiar with the scope that any change that the person skilled in art does embodiment of the present utility model does not all break away from claims of the present utility model.Correspondingly, the scope of claim of the present utility model also is not limited only to previous embodiment.
Claims (8)
1. crash monitoring and resetting means is characterized in that it comprises first circuit, second circuit and Keysheet module, described first circuit state that do not crash, and described second circuit has deadlock state and normal operating conditions,
When the button in the described Keysheet module was pressed, described first circuit began to detect described second circuit and whether is in the deadlock state, and when described second circuit was in the deadlock state, described first circuit was controlled described second circuit and recovered normal operating conditions.
2. deadlock monitoring according to claim 1 and resetting means is characterized in that,
Be provided with communication channel and reset passages between described first circuit and the described second circuit,
Described second circuit sends to described first circuit by described communication port with response signal, and described first circuit is controlled described second circuit by described reset passages and recovered normal operating conditions.
3. deadlock monitoring according to claim 2 and resetting means, it is characterized in that, include a plurality of buttons in the described Keysheet module, each button and a resistance string are coupled between power supply and the ground, node between each button and the connected resistance links to each other with the push button signalling input end of first circuit and the push button signalling input end of second circuit simultaneously, when a button is pressed, a corresponding push button signalling be will produce and first circuit and second circuit given, so that described second circuit sends response signal to described first circuit, make whether described this response signal of first electric circuit inspection is correct response signal.
4. deadlock monitoring according to claim 3 and resetting means, it is characterized in that, described communication channel comprises serial data line and the serial time clock line that is arranged between described first circuit and the second circuit, described serial time clock line links to each other with power supply by first resistance, and described serial data line links to each other with power supply by second resistance.
5. according to the arbitrary described deadlock monitoring of claim 2-4 and resetting means, it is characterized in that, described reset passages connects the reset signal output terminal of described first circuit and the reset terminal of second circuit, when judging that described second circuit is in the deadlock state, described first circuit enters normal operating conditions by the reset terminal of reset signal output terminal output reset signal to described second circuit to reactivate described second circuit.
6. deadlock monitoring according to claim 5 and resetting means is characterized in that, described first circuit is electric power management circuit, and described second circuit is processor.
7. according to the arbitrary described deadlock monitoring of claim 2-4 and resetting means, it is characterized in that, described reset passages connects the power output end of described first circuit and the power end of described second circuit, described first circuit provides power supply for described second circuit, when the deadlock state appearred in described second circuit, the power supply that described first circuit will offer second circuit restarted.
8. deadlock monitoring according to claim 7 and resetting means is characterized in that, described first circuit is electric power management circuit, and described second circuit is processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220706096 CN203117961U (en) | 2012-12-19 | 2012-12-19 | Dead halt monitoring and resetting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220706096 CN203117961U (en) | 2012-12-19 | 2012-12-19 | Dead halt monitoring and resetting device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203117961U true CN203117961U (en) | 2013-08-07 |
Family
ID=48898287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220706096 Expired - Lifetime CN203117961U (en) | 2012-12-19 | 2012-12-19 | Dead halt monitoring and resetting device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203117961U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103049347A (en) * | 2012-12-19 | 2013-04-17 | 无锡中星微电子有限公司 | Computer crash monitoring and resetting device |
| CN105204954A (en) * | 2015-09-17 | 2015-12-30 | 广东欧珀移动通信有限公司 | Method and terminal for processing dead halt state |
| CN105279041A (en) * | 2015-11-11 | 2016-01-27 | 广东欧珀移动通信有限公司 | Method and device for automatically rebooting terminal after crash of terminal |
-
2012
- 2012-12-19 CN CN 201220706096 patent/CN203117961U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103049347A (en) * | 2012-12-19 | 2013-04-17 | 无锡中星微电子有限公司 | Computer crash monitoring and resetting device |
| CN103049347B (en) * | 2012-12-19 | 2016-05-11 | 无锡中感微电子股份有限公司 | Monitoring and resetting means crash |
| CN105204954A (en) * | 2015-09-17 | 2015-12-30 | 广东欧珀移动通信有限公司 | Method and terminal for processing dead halt state |
| CN105204954B (en) * | 2015-09-17 | 2019-02-22 | Oppo广东移动通信有限公司 | A kind of method and terminal handling crash state |
| CN105279041A (en) * | 2015-11-11 | 2016-01-27 | 广东欧珀移动通信有限公司 | Method and device for automatically rebooting terminal after crash of terminal |
| CN105279041B (en) * | 2015-11-11 | 2018-06-22 | 广东欧珀移动通信有限公司 | A kind of method and device restarted automatically after terminal crash |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10846160B2 (en) | System and method for remote system recovery | |
| CN103066969B (en) | A kind of electronic equipment with crash reset function | |
| CN104516296B (en) | A kind of awakening method and peripheral module of the micro controller system based on peripheral module | |
| US10860522B2 (en) | Method and apparatus for controlling USB-C connectors on system with multiple host controllers | |
| US20130254571A1 (en) | Power management method and apparatus for network access module | |
| US10887075B2 (en) | Method and system for adaptive link training mechanism to calibrate an embedded universal serial bus redriver clock | |
| CN203366017U (en) | Building talk-back intelligent terminal and crash restart system for same | |
| CN108089940A (en) | Handle system, the method and apparatus of time-out | |
| CN101581964B (en) | Computer system and peripheral equipment drive method | |
| CN104781754A (en) | Reduction of idle power in a communication port | |
| CN202995614U (en) | Electronic equipment | |
| JP2016500174A (en) | Virtual GPIO | |
| US11126442B2 (en) | False-touch-wakeup prevention apparatus and method, intelligent terminal and computer storage medium | |
| US20140334364A1 (en) | Remote wake-up system and method | |
| CN105225316A (en) | A kind of dormancy of electron key low-power consumption power supply plan and awakening method | |
| CN104597790A (en) | Serial port controller and awakening method for micro-controller system based on the same | |
| CN203117961U (en) | Dead halt monitoring and resetting device | |
| CN104182243A (en) | Sleep state control system, computer system and sleep state detection method thereof | |
| CN104281465A (en) | Computer and awakening method thereof | |
| CN110245048B (en) | Intelligent management system and management method for chassis | |
| CN202995613U (en) | Crash resetting device | |
| CN101350995B (en) | Awakening method between mobile terminal modules and multi-mode terminal using the same | |
| CN103049347B (en) | Monitoring and resetting means crash | |
| CN102866873A (en) | Method for detecting state of seat with computer | |
| CN103049063A (en) | Computer crash resetting device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 214135 10th Floor, Area A, 530 Building, Qingyuan Road, Taihu International Science Park, Wuxi New District, Jiangsu Province Patentee after: Zgmicro Corporation Address before: 214135 10th Floor, Area A, 530 Building, Qingyuan Road, Taihu International Science Park, Wuxi New District, Jiangsu Province Patentee before: WUXI VIMICRO Corp. |
|
| CP01 | Change in the name or title of a patent holder | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130807 |
|
| CX01 | Expiry of patent term |