CN104597790A - Serial port controller and awakening method for micro-controller system based on the same - Google Patents
Serial port controller and awakening method for micro-controller system based on the same Download PDFInfo
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- CN104597790A CN104597790A CN201410830132.7A CN201410830132A CN104597790A CN 104597790 A CN104597790 A CN 104597790A CN 201410830132 A CN201410830132 A CN 201410830132A CN 104597790 A CN104597790 A CN 104597790A
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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Abstract
The invention discloses a serial port controller and an awakening method for a micro-controller system based on the same. The awakening method includes that judging whether a frame starting mark is detected under a low-power consumption mode, if the frame starting mark is detected, opening a clock switching circuit to generate a serial port working clock; receiving a current data frame; judging whether the current data frame is matched with an awakening frame, if so, generating awakening interruption, and awakening the micro-controller system. The serial port controller and the awakening method for the micro-controller system based on the same do not open the clock switching circuit to generate the serial port working clock until the frame starting mark is detected, and the system power consumption under the low-power consumption mode is lowered.
Description
Technical field
The present invention relates to electronic circuit technology field, particularly relate to the awakening method of a kind of serial ports controller and the micro controller system based on it.
Background technology
In microcontroller (MCU, Micro Control Unit) chip system, in order to reduce stand-by power consumption, chip all possesses one or more low-power consumption modes usually.Chip is after entering low-power consumption mode, most clocks of chip internal all can be closed, and central processing unit (CPU, Central Processing Unit) cannot continue executive software instruction, need to wake chip up on suitable opportunity, make chip get back to normal duty.
Existing awakening technology mainly contains CPU and interrupts waking up waking up with peripheral hardware.
CPU interrupts waking up and mainly uses arousal function integrated in CPU module.Under low-power consumption mode, when CPU on the pin waken up, receive a pulse or high level time, CPU will start to perform wake up procedure, by system wake-up.The shortcoming that CPU interrupts waking up is that wake-up mode is more single.
Peripheral hardware wakes peripheral module integrated in mainly use system up and wakes up.Existing peripheral hardware wake-up mode all needs to keep peripheral clock to open under low-power consumption mode substantially, causes the system power dissipation under low-power consumption mode larger.
Summary of the invention
The object of the invention is to the awakening method proposing a kind of serial ports controller and the micro controller system based on it, this awakening method can solve the problem that in existing awakening technology, system power dissipation is larger.
For reaching this object, the present invention by the following technical solutions:
First aspect, the invention discloses a kind of awakening method of the micro controller system based on serial ports controller, comprising:
Under low-power consumption mode, judge whether frame beginning label to be detected, if described frame beginning label detected, then open clock switch circuit, to produce serial ports work clock;
Receive current data frame;
Judge described current data frame and wake frame up and whether mate, if described current data frame is mated with the described frame that wakes up, then produce wake-up interrupts, wake micro controller system up.
Further, also comprise:
If described current data frame is not mated with the described frame that wakes up, then close clock switch circuit.
Further, described under low-power consumption mode, before judging whether frame beginning label to be detected, described method also comprises:
Under system running pattern, judge whether to receive the instruction entering described low-power consumption mode; If so, then close clock generation circuit, if not, then continue system running pattern.
Further, described under system running pattern, before judging whether to receive the instruction entering described low-power consumption mode, described method also comprises:
Under system running pattern, described in being configured by system bus, wake the content of frame up.
Second aspect, the invention discloses a kind of serial ports controller, and described serial ports controller can realize above-mentioned arbitrary described awakening method, comprising:
Configuration register, frame start testing circuit, data frame receipt circuit, received frame content analysis circuit and clock switch circuit,
Described frame starts testing circuit and is connected with described clock switch circuit, and described received frame content analysis circuit is connected with described configuration register and described data frame receipt circuit respectively;
Described configuration register is used for storage and wakes frame up;
Described frame starts testing circuit under low-power consumption mode, judges whether frame beginning label to be detected, if described frame beginning label detected, then opens clock switch circuit, to produce serial ports work clock;
Described data frame receipt circuit is used for accepting current data frame;
Described received frame content analysis circuit is for judging whether described current data frame mates with the described frame that wakes up, if described current data frame is mated with the described frame that wakes up, then produces wake-up interrupts, wakes micro controller system up.
Further, described received frame content analysis circuit is connected with described clock switch circuit;
If described received frame content analysis circuit does not also mate with the described frame that wakes up for described current data frame, then close described clock switch circuit.
Further, described configuration register is also connected with the system bus in micro controller system, under system running pattern, is configured the described frame that wakes up by described system bus.
Further, described frame starts testing circuit is that CK type is along testing circuit.
Further, described clock switch circuit comprise the first trigger, the second trigger, phase inverter and with door, the pulse signal that described first trigger is used for described frame to start testing circuit generation carries out broadening with synchronous, the clock switch that described second trigger opens or closes for generation of the described clock generation circuit of control, wherein, described first trigger comprises the first set end, the first clock end, the first trigger end and the first output terminal, described second trigger comprises the second set end, second clock end, the second trigger end and the second output terminal
Described first set end starts testing circuit with described frame and is connected, and described first clock end is connected with the output terminal of described clock generation circuit, and described first trigger end is for receiving an electronegative potential, and described first output terminal is connected with described second set end;
Described second clock end is connected with the output terminal of described clock generation circuit, and described second trigger end is connected with the output terminal of door with described, and described second output terminal is connected with the input end of described clock generation circuit;
The input end of described phase inverter is connected with the output terminal of described received frame content analysis circuit, and the output terminal of described phase inverter is connected with the first input end of door with described, is describedly connected with described second output terminal with the second input end of door.
Further, when described clock generation circuit controls the closedown of described serial ports work clock, and when described frame start testing circuit frame beginning label detected time, control described first trigger and described second trigger set, the clock switch that described second output terminal exports is opened, thus controls described clock generation circuit generation serial ports work clock; When described clock generation circuit produces serial ports work clock, if described received frame content analysis circuit judges that described current data frame is not mated with the described frame that wakes up, then described received frame content analysis circuit exports noble potential, the clock switch that described second trigger is exported is closed, thus controls described clock generation circuit and close described serial ports work clock.
Further, also comprise:
Dataframe circuit, described dataframe circuit is connected with described configuration register, for sending the Frame stored in configuration register;
Described data frame receipt circuit is connected with described configuration register, for being sent in described configuration register by the Frame received.
Serial ports controller of the present invention and only just open clock switch circuit when frame beginning label being detected based on the awakening method of its micro controller system, to produce serial ports work clock, reduces the system power dissipation under low-power consumption mode.
Accompanying drawing explanation
In order to the technical scheme of exemplary embodiment of the present is clearly described, one is done to the accompanying drawing used required for describing in embodiment below and simply introduce.Obviously, the accompanying drawing introduced is the accompanying drawing of a part of embodiment that the present invention will describe, instead of whole accompanying drawings, for those of ordinary skill in the art, under the prerequisite not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the process flow diagram of the awakening method of the micro controller system based on serial ports controller that the embodiment of the present invention one provides.
Fig. 2 is the structural drawing of the serial ports controller that the embodiment of the present invention two provides.
Fig. 3 is the structural drawing of the clock switch circuit of the serial ports controller that the embodiment of the present invention two provides.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below with reference to the accompanying drawing in the embodiment of the present invention, by embodiment, technical scheme of the present invention is intactly described.Obviously; described embodiment is a part of embodiment of the present invention, instead of whole embodiments, based on embodiments of the invention; the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all falls within protection scope of the present invention.
Embodiment one:
Fig. 1 is the process flow diagram of the awakening method of the micro controller system based on serial ports controller that the embodiment of the present invention one provides.As shown in Figure 1, this awakening method comprises:
Step 101, under low-power consumption mode, judge whether frame beginning label to be detected.If monitor frame beginning label, then perform following steps:
In this step, detect in real time to frame beginning label, frame beginning label can be negative edge signal.In the process detected frame beginning label, do not need to use serial ports work clock.
Step 102, open clock switch circuit, to produce serial ports work clock.
In this step, produce serial ports work clock, so that current data frame can be received.
Step 103, reception current data frame.
In this step, the current data frame that the frame beginning label that reception detects is corresponding.
Step 104, judge current data frame and wake frame up and whether mate.If current data frame with wake frame up and mate, then perform step 105, produce wake-up interrupts, wake micro controller system up.
Preferably, further comprising the steps of:
If current data frame with wake frame up and do not mate, then perform step 106, close clock switch circuit.
In this step, close clock switch circuit, and then serial ports work clock is closed.This makes while achieving arousal function, reduces the stand-by power consumption of micro controller system as much as possible.
Preferably, further comprising the steps of:
If frame beginning label do not detected, then perform step 151, system cloud gray model low-power consumption mode.
In this step, under low-power consumption mode, if frame beginning label do not detected, then system continues to run low-power consumption mode.
Preferably, further comprising the steps of before step 151, system cloud gray model low-power consumption mode:
Step 121, under system running pattern, judge whether to receive the instruction entering low-power consumption mode.If so, then perform step 131, close clock generation circuit.If not, then perform step 141, continue system running pattern.
In this step, after entering low-power consumption mode, do not need to use serial ports work clock to the testing process of frame beginning label.So close clock generation circuit before system enters low-power consumption mode, and then close serial ports work clock, reduce system power dissipation as much as possible.
Preferably, in step 121, under system running pattern, further comprising the steps of before judging whether to receive the instruction entering low-power consumption mode:
Step 111, under system running pattern, described in being configured by system bus, wake the content of frame up.
In this step, user can be configured waking frame up by system bus, can select certain several bit be the received frame of specific value as coupling frame, or arbitrary received frame all regarded mate frame, even can select start of frame delimiter as being mate frame.By to the configuration waking frame up, add the dirigibility of arousal function, allow user freely to customize the content waken up, and then wake micro controller system up selectively.
The awakening method of the micro controller system based on serial ports controller that the embodiment of the present invention one provides only just opens clock switch circuit when frame beginning label being detected, to produce serial ports work clock, reduces the system power dissipation under low-power consumption modulus.
Embodiment two:
Fig. 2 is the structural drawing of the serial ports controller that the embodiment of the present invention two provides.The serial ports controller that the embodiment of the present invention two provides can realize the awakening method described in the embodiment of the present invention one.As shown in Figure 2, this serial ports controller comprises: configuration register 201, frame start testing circuit 202, data frame receipt circuit 203, received frame content analysis circuit 204 and clock switch circuit 205, frame starts testing circuit 202 and is connected with clock switch circuit 205, and received frame content analysis circuit 204 is connected with configuration register 201 and data frame receipt circuit 203 respectively.
Configuration register 201 wakes frame up for storing.
Preferably, configuration register 201 can also be connected with the system bus 206 in micro controller system by bus interface, under system running pattern, is configured waking frame up by system bus 206.
In the present embodiment, user can be configured waking frame up by system bus 206, can select certain several bit be the received frame of specific value as coupling frame, or arbitrary received frame all regarded mate frame, even can select start of frame delimiter as being mate frame.By to the configuration waking frame up, add the dirigibility of arousal function, allow user freely to customize the content waken up, and then wake micro controller system up selectively.
Wherein, configuration register comprises multiple register, is read and write by system bus 206, controls the operational mode of serial ports controller.Transmission data can be passed to serial ports controller by configuration register 201 by system, and read the data that serial ports controller receives.
Frame starts testing circuit 202 under low-power consumption mode, judges whether frame beginning label to be detected, if described frame beginning label detected, then opens clock switch circuit 205, to produce serial ports work clock.
In the present embodiment, frame starts testing circuit 202 for detecting the negative edge signal on serial interface 207 in real time, as frame beginning label.In the process detecting negative edge signal, frame starts testing circuit 202 not to be needed to use serial ports work clock.Before system enters low-power consumption mode, in order to reduce system power dissipation, can first serial ports work clock be closed.Under low-power consumption mode, if frame starts testing circuit 202 detect start of frame delimiter, clock switch circuit 205 will be opened, and then the clock generation circuit 208 in control micro controller system produces serial ports work clock, make data frame receipt circuit 203 can receive the content of current data frame normally.
Preferably, frame starts testing circuit 202 for CK type is along testing circuit.
Frame starts testing circuit and adjusts 202 by CK type along testing circuit, and when can ensure that serial ports work clock is closed, frame starts testing circuit 202 also can detect frame beginning label normally.CK type along testing circuit after start of frame delimiter being detected, can produce one with the pulse signal of serial ports work clock asynchronous relationship each other.
Data frame receipt circuit 203 is for receiving current data frame.
In the present embodiment, data frame receipt circuit 203 can receive the Frame that serial interface 207 transmits.
Received frame content analysis circuit 204 for judging current data frame and waking frame up and whether mate, if current data frame with wake frame up and mate, then produce wake-up interrupts, wake micro controller system up.
In the present embodiment, whether received frame content analysis circuit 204, for analyzing the current data frame received, judges it and wakes frame up and mate, if coupling, then produce wake-up interrupts, the interrupt response 209 in input micro controller system, and then wake micro controller system up.
Preferably, received frame content analysis circuit 204 is connected with clock switch circuit 205.
Content frame analysis circuit 204 be connected with clock switch circuit 205 make received frame content analysis circuit 204 also for current data frame with wake up frame do not mate time, close clock switch circuit 205.
In the present embodiment, close clock switch circuit 205, and then control clock generation circuit 208 closes serial ports work clock, makes while achieving arousal function, reduces the stand-by power consumption of micro controller system as much as possible.
Fig. 3 is the structural drawing of the clock switch circuit of the serial ports controller that the embodiment of the present invention two provides.Preferably, as shown in Figure 3, clock switch circuit 205 comprises: the first trigger 215, second trigger 225, phase inverter 235 and with door 245, first trigger 215 comprises the first set end SET1, the first clock end CK1, the first trigger end D1 and the first output terminal Q1, and the second trigger 225 comprises the second set end SET2, second clock end CK2, the second trigger end D2 and the second output terminal Q2.
First set end SET1 starts testing circuit 202 with frame and is connected, and the first clock end CK1 is connected with the output terminal of clock generation circuit 208, and the first trigger end D1 is for receiving an electronegative potential, and the first output terminal Q1 is connected with the second set end SET2; Second clock end CK2 is connected with the output terminal of clock generation circuit 208, the second trigger end D2 and being connected with the output terminal of door 245, and the second output terminal Q2 is connected with the input end of clock generation circuit 208; The input end of phase inverter 235 is connected with the output terminal of received frame content analysis circuit 204, the output terminal of phase inverter 235 and being connected with the first input end of door 245, is connected with the second output terminal Q2 with the second input end of door 245.
First trigger 215 carries out broadening and synchronous for pulse signal frame being started testing circuit 202 and produce, and the second trigger 225 is for generation of the clock switch controlling clock generation circuit 208 and open or close.
When clock generation circuit 208 controls the closedown of serial ports work clock, and when frame start testing circuit 202 frame beginning label detected time, control the first trigger 215 and the second trigger 225 set, the clock switch that second output terminal Q2 exports is opened, thus control clock generation circuit 208 produces serial ports work clock; When clock generation circuit 208 produces serial ports work clock, if received frame content analysis circuit 204 judges current data frame and wakes frame up and do not mate, then received frame content analysis circuit 204 exports noble potential, the clock switch that second trigger 225 is exported is closed, thus control clock generation circuit 208 closes serial ports work clock.
Preferably, also comprise:
Dataframe circuit 210, dataframe circuit 210 is connected with configuration register 201, for sending the Frame stored in configuration register.
In the present embodiment, the transmission data that system bus 206 can send by dataframe circuit 210 are sent to serial interface 207.
Data frame receipt circuit 203 is connected with configuration register 201, for being sent in configuration register 201 by the Frame received from serial interface 207.
In the present embodiment, the Frame received can be back to configuration register 201 by data frame receipt circuit 203.
The serial ports controller that the embodiment of the present invention two provides only just opens clock switch circuit when frame beginning label being detected, to produce serial ports work clock, reduce the power consumption of micro controller system under low-power consumption mode, and start testing circuit, clock switch circuit and received frame content analysis circuit by existing serial ports controller is increased frame, achieve arousal function, waking up for micro controller system, decreases the chip area realizing arousal function and consume, and then decreases cost.
The know-why that above are only preferred embodiment of the present invention and use.The invention is not restricted to specific embodiment described here, the various significant changes can carried out for a person skilled in the art, readjust and substitute all can not depart from protection scope of the present invention.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by the scope of claim.
Claims (11)
1. based on an awakening method for the micro controller system of serial ports controller, it is characterized in that, comprising:
Under low-power consumption mode, judge whether frame beginning label to be detected, if described frame beginning label detected, then open clock switch circuit, to produce serial ports work clock;
Receive current data frame;
Judge described current data frame and wake frame up and whether mate, if described current data frame is mated with the described frame that wakes up, then produce wake-up interrupts, wake micro controller system up.
2. awakening method according to claim 1, is characterized in that, also comprises:
If described current data frame is not mated with the described frame that wakes up, then close clock switch circuit.
3. awakening method according to claim 1 and 2, is characterized in that, described under low-power consumption mode, and before judging whether frame beginning label to be detected, described method also comprises:
Under system running pattern, judge whether to receive the instruction entering described low-power consumption mode; If so, then close clock generation circuit, if not, then continue system running pattern.
4. awakening method according to claim 3, is characterized in that, described under system running pattern, and before judging whether to receive the instruction entering described low-power consumption mode, described method also comprises:
Under system running pattern, described in being configured by system bus, wake the content of frame up.
5. a serial ports controller, described serial ports controller can realize the arbitrary described awakening method of claim 1-4, it is characterized in that, comprising:
Configuration register, frame start testing circuit, data frame receipt circuit, received frame content analysis circuit and clock switch circuit,
Described frame starts testing circuit and is connected with described clock switch circuit, and described received frame content analysis circuit is connected with described configuration register and described data frame receipt circuit respectively;
Described configuration register is used for storage and wakes frame up;
Described frame starts testing circuit under low-power consumption mode, judges whether frame beginning label to be detected, if described frame beginning label detected, then opens clock switch circuit, to produce serial ports work clock;
Described data frame receipt circuit is used for accepting current data frame;
Described received frame content analysis circuit is for judging whether described current data frame mates with the described frame that wakes up, if described current data frame is mated with the described frame that wakes up, then produces wake-up interrupts, wakes micro controller system up.
6. serial ports controller according to claim 5, is characterized in that, described received frame content analysis circuit is connected with described clock switch circuit;
If described received frame content analysis circuit does not also mate with the described frame that wakes up for described current data frame, then close described clock switch circuit.
7. serial ports controller according to claim 6, is characterized in that, described configuration register is also connected with the system bus in micro controller system, under system running pattern, is configured the described frame that wakes up by described system bus.
8. serial ports controller according to claim 7, is characterized in that, it is that CK type is along testing circuit that described frame starts testing circuit.
9. serial ports controller according to claim 7, it is characterized in that, described clock switch circuit comprises the first trigger, second trigger, phase inverter and with door, the pulse signal that described first trigger is used for described frame to start testing circuit generation carries out broadening with synchronous, the clock switch that described second trigger opens or closes for generation of the described clock generation circuit of control, wherein, described first trigger comprises the first set end, first clock end, first trigger end and the first output terminal, described second trigger comprises the second set end, second clock end, second trigger end and the second output terminal,
Described first set end starts testing circuit with described frame and is connected, and described first clock end is connected with the output terminal of described clock generation circuit, and described first trigger end is for receiving an electronegative potential, and described first output terminal is connected with described second set end;
Described second clock end is connected with the output terminal of described clock generation circuit, and described second trigger end is connected with the output terminal of door with described, and described second output terminal is connected with the input end of described clock generation circuit;
The input end of described phase inverter is connected with the output terminal of described received frame content analysis circuit, and the output terminal of described phase inverter is connected with the first input end of door with described, is describedly connected with described second output terminal with the second input end of door.
10. serial ports controller according to claim 9, it is characterized in that, when described clock generation circuit controls the closedown of described serial ports work clock, and when described frame start testing circuit frame beginning label detected time, control described first trigger and described second trigger set, the clock switch that described second output terminal exports is opened, thus controls described clock generation circuit generation serial ports work clock; When described clock generation circuit produces serial ports work clock, if described received frame content analysis circuit judges that described current data frame is not mated with the described frame that wakes up, then described received frame content analysis circuit exports noble potential, the clock switch that described second trigger is exported is closed, thus controls described clock generation circuit and close described serial ports work clock.
11., according to the arbitrary described serial ports controller of claim 5-9, is characterized in that, also comprise:
Dataframe circuit, described dataframe circuit is connected with described configuration register, for sending the Frame stored in configuration register;
Described data frame receipt circuit is connected with described configuration register, for being sent in described configuration register by the Frame received.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105071891A (en) * | 2015-08-28 | 2015-11-18 | Tcl移动通信科技（宁波）有限公司 | Bluetooth clock control system and Bluetooth clock control method |
| CN108663070A (en) * | 2017-03-27 | 2018-10-16 | 英飞凌科技股份有限公司 | Digital sensor system |
| CN109859454A (en) * | 2017-11-30 | 2019-06-07 | 珠海格力电器股份有限公司 | Infrared code transmitting line, chip, remote control equipment and air-conditioning based on infrared protocol |
| CN109976501A (en) * | 2017-12-28 | 2019-07-05 | 中移物联网有限公司 | A kind of Low-power-consumptiocontrol control method, device, system and storage medium |
| CN111061358A (en) * | 2018-10-15 | 2020-04-24 | 珠海格力电器股份有限公司 | Clock-free chip wake-up circuit, wake-up method and chip |
| CN111158758A (en) * | 2018-11-07 | 2020-05-15 | 珠海格力电器股份有限公司 | Method and device for waking up central processing unit |
| CN112214246A (en) * | 2019-07-11 | 2021-01-12 | 深圳市航顺芯片技术研发有限公司 | Low-power-consumption multiprocessor serial port awakening method and system |
| CN113177016A (en) * | 2021-05-25 | 2021-07-27 | 惠州Tcl移动通信有限公司 | Serial port communication method, device, terminal equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060205382A1 (en) * | 2005-03-10 | 2006-09-14 | Wang Michael M | Apparatus and method for determining sleep clock timing |
| CN101150809A (en) * | 2007-11-03 | 2008-03-26 | 青岛海信移动通信技术股份有限公司 | Method for arousing and stream control of mobile terminal processor serial port |
| WO2009078575A1 (en) * | 2007-12-17 | 2009-06-25 | Electronics And Telecommunications Research Institute | Wake-up apparatus and wake-up method for low power sensor node |
| CN103631360A (en) * | 2013-11-15 | 2014-03-12 | 北京兆易创新科技股份有限公司 | Chip allowing sleep mode and method |
-
2014
- 2014-12-26 CN CN201410830132.7A patent/CN104597790B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060205382A1 (en) * | 2005-03-10 | 2006-09-14 | Wang Michael M | Apparatus and method for determining sleep clock timing |
| CN101150809A (en) * | 2007-11-03 | 2008-03-26 | 青岛海信移动通信技术股份有限公司 | Method for arousing and stream control of mobile terminal processor serial port |
| WO2009078575A1 (en) * | 2007-12-17 | 2009-06-25 | Electronics And Telecommunications Research Institute | Wake-up apparatus and wake-up method for low power sensor node |
| CN103631360A (en) * | 2013-11-15 | 2014-03-12 | 北京兆易创新科技股份有限公司 | Chip allowing sleep mode and method |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105071891A (en) * | 2015-08-28 | 2015-11-18 | Tcl移动通信科技（宁波）有限公司 | Bluetooth clock control system and Bluetooth clock control method |
| CN108663070A (en) * | 2017-03-27 | 2018-10-16 | 英飞凌科技股份有限公司 | Digital sensor system |
| CN109859454A (en) * | 2017-11-30 | 2019-06-07 | 珠海格力电器股份有限公司 | Infrared code transmitting line, chip, remote control equipment and air-conditioning based on infrared protocol |
| US11004331B2 (en) | 2017-11-30 | 2021-05-11 | Gree Electric Appliances (Wuhan) Co., Ltd | Infrared protocol-based infrared code transmission circuit, chip, remote control device and air conditioner |
| CN109976501A (en) * | 2017-12-28 | 2019-07-05 | 中移物联网有限公司 | A kind of Low-power-consumptiocontrol control method, device, system and storage medium |
| CN111061358A (en) * | 2018-10-15 | 2020-04-24 | 珠海格力电器股份有限公司 | Clock-free chip wake-up circuit, wake-up method and chip |
| CN111061358B (en) * | 2018-10-15 | 2021-05-25 | 珠海格力电器股份有限公司 | Clock-free chip wake-up circuit, wake-up method and chip |
| CN111158758A (en) * | 2018-11-07 | 2020-05-15 | 珠海格力电器股份有限公司 | Method and device for waking up central processing unit |
| CN111158758B (en) * | 2018-11-07 | 2024-03-15 | 珠海格力电器股份有限公司 | Method and device for waking up central processing unit |
| CN112214246A (en) * | 2019-07-11 | 2021-01-12 | 深圳市航顺芯片技术研发有限公司 | Low-power-consumption multiprocessor serial port awakening method and system |
| CN113177016A (en) * | 2021-05-25 | 2021-07-27 | 惠州Tcl移动通信有限公司 | Serial port communication method, device, terminal equipment and storage medium |
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