CN111061358B - Clock-free chip wake-up circuit, wake-up method and chip - Google Patents
Clock-free chip wake-up circuit, wake-up method and chip Download PDFInfo
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Abstract
The invention discloses a clock-free chip wake-up circuit, a wake-up method and a chip, wherein the clock-free chip wake-up circuit comprises an acquisition circuit and a detection circuit, wherein the acquisition circuit is used for acquiring an input signal to be detected; the detection circuit is used for detecting a signal to be detected and generating a wake-up signal according to the signal to be detected, and comprises a state detection module, a state latch module and a state recovery module, wherein the state detection module is connected with the acquisition circuit and is used for detecting whether the signal to be detected is input or not, if the signal to be detected is input, the state detection module outputs the signal to be detected, the state latch module is connected with the state detection module and is used for generating the wake-up signal according to the signal to be detected, and after the wake-up signal is generated, the state recovery module resets the state latch module and the state detection module and recovers to the. The method comprises the steps of detecting a signal to be detected by collecting an input signal to be detected, generating a wake-up signal according to the signal to be detected, realizing clock-free IO wake-up, reducing power consumption to the lowest as possible, and improving circuit reliability.
Description
Technical Field
The invention relates to the field of electronic circuits, in particular to a clock-free chip wake-up circuit, a wake-up method and a chip.
Background
The Microcontroller Chip (MCU) has independent processor, I/O device and memory, can reduce size, reduce equipment cost, and is widely applied in various fields, such as household appliances, medical instruments, industrial control, remote equipment, office equipment, toys and embedded systems.
The power consumption is a very important parameter for measuring a Microcontroller Chip (MCU), different chips with the same function are realized, the temperature of the chip is increased due to higher power consumption density, the reliability of a circuit is influenced, the service life of a device is reduced, and meanwhile, higher power consumption means more battery consumption and higher use cost.
However, the Microcontroller Chip (MCU) has to achieve the function of real-time response due to the application requirements, so that the CPU in the power-off or sleep state needs to be activated in real time to work, therefore, the low-power wake-up design of the chip is very important, IO wake-up needs to detect the change of an external level, extra power consumption can be increased by using clock detection, and the chip has large power consumption and high cost.
Disclosure of Invention
The invention aims to overcome the technical problem that additional power consumption is increased by using clock detection in the prior art, and provides a clock-free chip wake-up circuit, a wake-up method and a chip.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows: a clock-free chip wake-up circuit comprises an acquisition circuit and a detection circuit
The acquisition circuit is used for acquiring an input signal to be detected;
the detection circuit is used for detecting a signal to be detected and generating a wake-up signal according to the signal to be detected, and comprises a state detection module, a state latch module and a state recovery module,
the state detection module is connected with the acquisition circuit and is used for detecting whether a signal to be detected is input or not, if the signal to be detected is input, the output end of the state detection module outputs the signal to be detected,
the state latch module is connected with the state detection module, generates a wake-up signal according to the signal to be detected and latches the conversion state;
the state recovery module is respectively connected with the state latch module and the state detection module, and after the wake-up signal is generated, the state latch module and the state detection module are reset to recover to a detection state.
Furthermore, the acquisition circuit comprises an exclusive-or gate and a first and gate, wherein a first input end of the exclusive-or gate is connected with the signal to be detected, a second input end of the exclusive-or gate is connected with the edge selection signal, an output end of the exclusive-or gate is connected with a first input end of the first and gate, and a second input end of the first and gate is connected with the detection enabling signal.
Furthermore, the state detection module comprises a first trigger and a first phase inverter, a first input end of the first trigger is connected with an output end of the first and gate, a second input end of the first trigger is respectively connected with the state recovery module and the state latch module, an output end of the first trigger is connected with an input end of the first phase inverter, and an output end of the first phase inverter is connected with the state latch module.
Furthermore, the state latch module comprises a register and a second and gate, a first input end of the register is connected with an output end of the first phase inverter, a second input end of the register is connected with the reset signal, a third input end of the register is connected with an output end of the second and gate, a fourth input end of the register is connected with the clock signal, a first output end of the register outputs the wake-up signal, a second output end of the register is connected with the state recovery module, a first input end of the second and gate is connected with a first output end of the register, and a second input end of the register is connected with the.
Furthermore, a third input end of the register forms self-feedback with the first output end through a second AND gate.
Further, the state recovery module includes a second flip-flop, a third and gate, a second inverter, and a nand gate, where a first input end of the second flip-flop is connected to an output end of the third and gate and a second input end of the first flip-flop respectively, a second output end of the second flip-flop is connected to an output end of the first and gate and a second input end of the nand gate respectively, an output end of the second flip-flop is connected to an input end of the second inverter, a first input end of the third and gate is connected to the reset signal, a second input end of the third and gate is connected to a second output end of the register, an output end of the second flip-flop is connected to a second input end of the nand gate, a second output end of the nand gate is connected to an output end of the first and gate, and an output end of the nand gate is connected to a.
Further, the trigger is an RS trigger.
A chip with a wake-up function is provided, and the chip is integrated with the clock-free chip wake-up circuit.
A clock-free chip wake-up circuit wake-up method is used for waking up a CPU in a chip, and comprises the following steps:
collecting an input signal to be detected;
detecting whether a signal to be detected is input, if the signal to be detected is input, outputting a signal to be detected by an output end of the state detection module,
the state latch module generates a wake-up signal according to the signal to be detected and latches the conversion state;
and after the wake-up signal is generated, resetting, recovering to a detection state, and detecting again.
Further, when a signal to be detected is input, the first trigger is triggered, the state of the first trigger is changed, the first trigger is input to the register, the state of the register is changed, a wake-up signal is sent out, the CPU in the chip is awakened, meanwhile, the register latches data information, the wake-up signal is cleared, the state of the register is changed, the state of the second trigger is changed, and therefore the state of the first trigger is changed, and the detection state is restored.
Further, when a signal to be detected is input, the output of the exclusive-or gate is at a high level, the output of the first and gate is at a high level, at this time, the output of the Q-not end of the output end of the second flip-flop is at a low level, after passing through the second inverter, the output of the second inverter is at a high level, and is input into the nand gate together with the output of the exclusive-or gate, the output of the nand gate is at a low level, when the R end of the first input end of the first flip-flop receives the low level, the reset is effective, the output of the Q end becomes at a low level, the output of the Q-not end of the output end becomes at a high level, the output of the Q-not end of the output end passes through the first inverter, the first inverter outputs a low level, and is input into the SB end of the register, at this time, the output of the Q end of the first output end of the register becomes at a high level, the output, the output of the third AND gate is low level and is input to the R end of the first input end of the second trigger, the second trigger is effective, the Q non-end output of the output end of the second trigger is high level, the Q non-end output of the second inverter is low level through the second inverter, the Q non-end output of the NAND gate is high level, the R end of the first input end of the first trigger is ineffective, the second input end of the first trigger is connected with the output end of the third AND gate at the moment, the output of the third AND gate is low level, the Q non-end output of the output end of the first trigger 2 is low level, after the first inverter, the inverter outputs high level and is input to the SB end of the first input end of the register, the state is ineffective at the moment, the state of the detection circuit is recovered and recovered to the detection.
As can be seen from the above description of the present invention, compared with the prior art, the clock-less chip wake-up circuit, the wake-up method and the chip provided by the present invention employ the clock-less edge detection circuit, detect the signal to be detected by collecting the input signal to be detected, and generate the wake-up signal according to the signal to be detected, thereby realizing clock-less IO wake-up, minimizing power consumption as much as possible, and improving circuit reliability.
Drawings
FIG. 1 is a circuit diagram of a clock-less chip wake-up circuit according to the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments.
As shown in fig. 1, a clock-free chip wake-up circuit includes an acquisition circuit 10 and a detection circuit 11, where the acquisition circuit 10 acquires an input signal to be detected; the acquisition circuit 10 comprises an exclusive-or gate and a first and gate, a first input end of the exclusive-or gate is connected with a signal to be detected, a second input end of the exclusive-or gate is connected with an edge selection signal, an output end of the exclusive-or gate is connected with a first input end of the first and gate, a second input end of the first and gate is connected with a detection enabling signal, the detection circuit 11 detects the signal to be detected and generates a wake-up signal according to the signal to be detected, the detection circuit 11 comprises a state detection module 1, a state latch module 2 and a state recovery module 3,
the state detection module 1 is connected with the acquisition circuit 10 to detect whether a signal to be detected is input, if a signal to be detected is input, the output end of the state detection module 1 outputs the signal to be detected,
the state latch module 2 is connected with the state detection module 1, generates a wake-up signal according to the signal to be detected, and latches the wake-up signal;
the state recovery module 3 is respectively connected with the state latch module 2 and the state detection module 1, and after the wake-up signal is generated, the state latch module 2 and the state detection module 1 are reset, and the detection circuit recovers to the detection state.
The state detection module 1 comprises a first trigger and a first phase inverter, wherein a first input end of the first trigger is connected with an output end of the first AND gate, a second input end of the first trigger is respectively connected with the state recovery module 3 and the state latch module 2, an output end of the first trigger is connected with an input end of the first phase inverter, and an output end of the first phase inverter is connected with the state latch module 2.
The state latch module 2 comprises a register and a second AND gate, wherein the first input end of the register is connected with the output end of the first inverter, the second input end of the register is connected with a reset signal, the third input end of the register is connected with the output end of the second AND gate, the fourth input end of the register is connected with a clock signal, the first output end of the register outputs a wake-up signal, the second output end of the register is connected with the state recovery module, the first input end of the second AND gate is connected with the first output end of the register, the second input end of the second AND gate is connected with a wake-up clearing signal, the third input end of the register forms self-feedback with the first output end through the second AND gate,
the state recovery module 3 comprises a second trigger, a third and gate, a second inverter and a nand gate, wherein a first input end of the second trigger is connected with an output end of the third and gate and a second input end of the first trigger respectively, a second output end of the second trigger is connected with an output end of the first and gate and a second input end of the nand gate respectively, an output end of the second trigger is connected with an input end of the second inverter, a first input end of the third and gate is connected with a reset signal, a second input end of the third and gate is connected with a second output end of the register, an output end of the second trigger is connected with a second input end of the first trigger, an output end of the second inverter is connected with a first input end of the nand gate, a second output end of the nand gate is connected with an output end of the first and gate, and an output end.
The first trigger and the second trigger are both RS triggers, and the detection of the jump edge by the RS triggers is more sensitive and can also detect shorter pulse changes.
This no clock chip awakens circuit adopts two RS triggers, register and logic circuit to constitute no clock border detection circuitry, wait to detect the input signal through the collection, wait to examine through first RS trigger detection and wait to examine the signal, the register is according to waiting to examine the signal and generating awakening signal, realize no clock IO awakens up, after generating awakening signal, second RS trigger resets first RS trigger and register, detection circuitry resumes to the detection state, effectually falls to the lowest as far as with the consumption, improves the circuit reliability.
A chip with a wake-up function is provided, and the chip is integrated with the clock-free chip wake-up circuit.
A clock-free chip wake-up circuit wake-up method is used for waking up a CPU in a chip, and comprises the following steps:
collecting an input signal to be detected;
detecting whether a signal to be detected is input, if the signal to be detected is input, outputting a signal to be detected by an output end of the state detection module,
the state latch module generates a wake-up signal according to the signal to be detected and latches the conversion state;
and after the wake-up signal is generated, resetting, recovering to a detection state, and detecting again.
Specifically, when a signal to be detected is input, the first trigger is triggered, the state of the first trigger is changed, the first trigger is input to the register, the state of the register is changed, a wake-up signal is sent out, the CPU in the chip is awakened, meanwhile, the register latches data information, the wake-up signal is cleared, the state of the register is changed, the state of the second trigger is changed, and therefore the state of the first trigger is changed and the detection state is restored.
For convenience, 0 is defined as low, 1 is defined as high, the first input terminal of the flip-flop is R terminal, i.e., reset terminal, the second input terminal is S terminal, i.e., set terminal, the output terminal is Q not terminal, the first input terminal of the register is SB terminal, i.e., set terminal, the second input terminal is RB terminal, i.e., reset terminal, the third input terminal is D terminal, the fourth input terminal is CLK terminal, the clock signal is accessed, the first output terminal is Q terminal, and the second output terminal is QB terminal, i.e., Q not terminal.
The edge selection signal is configurable and programmable by software, and can select to detect a rising edge or a falling edge, when the rising edge is selected, the circuit can detect the change of the rising edge of the input signal, and when the value is 0, the rising edge is detected; when the value is 1, the detection of the falling edge, and the detection of the rising edge is adopted in the present embodiment.
The detection enabling signal is configurable by software, and when the value is 1, the detection function is turned on, and when the value is 0, the detection function is turned off.
When in a default state, the reset signal is connected to the reset end (R end) of the second trigger, and simultaneously the reset signal is connected to the set end (S end) of the first trigger, and after reset and evacuation, the output level of the second trigger is as follows: the Q end outputs 1 and the Q non-end outputs 0; the output level of the first flip-flop is: the Q terminal outputs 1, and the Q non-terminal outputs 0.
When the edge selection signal and the enable signal are configured by software, when the external level is not changed, the output of the exclusive-or gate is 0, the output of the first and gate is 0, the output of the nand gate is 1, the invalid signal is input into the first trigger, the output level of the first trigger is in a default state, the Q end is 1, the Q end is 0, the Q end of the first trigger passes through the first inverter, the value of the first inverter is 1, the first inverter is input into the set end (S end) of the register and belongs to the invalid signal, therefore, the output level of the register is in the default state, the Q end is 0, namely the wake-up output signal is 0, and the wake-up is not performed;
when the level of an external signal to be detected changes, the output of the exclusive-or gate is 1, the output of the first and gate is 1, at this time, the output of the Q non-end of the second trigger is 0, after passing through the second inverter, the value of the second inverter is 1, the second inverter and the output of the exclusive-or gate are jointly input into the NAND gate, at this time, the output of the NAND gate is 0, when the R end of the first trigger receives the value 0, the reset is effective, the output of the Q end is 0, the output of the Q non-end is 1, the first inverter passes through the first inverter, the value of the first inverter is 0, the output of the Q end of the register is input into the set end (S end) of the register, at this time, the register is effective, the output of the Q end of the register is 1, at this time, the awakening output signal is;
when the signal level change is detected, the output of the Q end of the register is 1, the output of the Q non-end is 0, the output of the third AND gate is 0, the signal is input to the reset end (R end) of the second trigger, the second trigger is effective, the output of the Q non-end of the second trigger is 1, the output of the second inverter is 0 after passing through the second inverter, the output of the NAND gate is 1, the reset end (R end) of the first trigger is invalid, the set end of the first trigger is connected with the output of the third AND gate (value is 0) and is effective, so that the Q non-end of the first trigger is 0, the signal is input to the set end (S end) of the register after passing through the first inverter, the invalid state of the detection circuit is recovered, the Q end of the register is connected to the D end of the register through the second AND gate, the self-feedback mode is adopted, when the chip is awakened, the chip recovers the clock, and the CPU can read the value of, meanwhile, the configurable programming wake-up signal clearing signal is 0, so that the output of the second AND gate is 0, after the register passes through and the next clock, the Q end of the register is changed from 1 to 0, and the detection state is restored again.
As can be seen from the above description of the present invention, compared with the prior art, the clock-less chip wake-up circuit, the wake-up method and the chip provided by the present invention employ the clock-less edge detection circuit, detect the signal to be detected by collecting the input signal to be detected, and generate the wake-up signal according to the signal to be detected, thereby realizing clock-less IO wake-up, minimizing power consumption as much as possible, and improving circuit reliability.
The above description is only a few specific embodiments of the present invention, but the design concept of the present invention is not limited thereto, and any insubstantial modifications made by the design concept should fall within the scope of the present invention.
Claims (10)
1. A clock-free chip wake-up circuit is characterized in that: comprises an acquisition circuit and a detection circuit
The acquisition circuit is used for acquiring an input signal to be detected;
the detection circuit is used for detecting a signal to be detected and generating a wake-up signal according to the signal to be detected, and comprises a state detection module, a state latch module and a state recovery module;
the state detection module is connected with the acquisition circuit and is used for detecting whether a signal to be detected is input or not, if the signal to be detected is input, the output end of the state detection module outputs the signal to be detected, the state detection module comprises a first trigger and a first phase inverter, the first input end of the first trigger is connected with the output end of the first AND gate, the second input end of the first trigger is respectively connected with the state recovery module and the state latch module, the output end of the first trigger is connected with the input end of the first phase inverter, and the output end of the first phase inverter is connected with the state latch module;
the state latch module is connected with the state detection module, generates a wake-up signal according to the signal to be detected and latches the conversion state;
the state recovery module is respectively connected with the state latch module and the state detection module, and after the wake-up signal is generated, the state latch module and the state detection module are reset to recover to a detection state.
2. The clockless chip wake-up circuit according to claim 1, characterized in that: the acquisition circuit comprises an exclusive-OR gate and a first AND gate, wherein a first input end of the exclusive-OR gate is connected with a signal to be detected, a second input end of the exclusive-OR gate is connected with an edge selection signal, an output end of the exclusive-OR gate is connected with a first input end of the first AND gate, and a second input end of the first AND gate is connected with a detection enabling signal.
3. The clockless chip wake-up circuit according to claim 1, characterized in that: the state latch module comprises a register and a second AND gate, wherein a first input end of the register is connected with an output end of the first phase inverter, a second input end of the register is connected with a reset signal, a third input end of the register is connected with an output end of the second AND gate, a fourth input end of the register is connected with a clock signal, a first output end of the register outputs a wake-up signal, a second output end of the register is connected with the state recovery module, a first input end of the second AND gate is connected with a first output end of the register, and a second input end of the second AND.
4. The clockless chip wake-up circuit according to claim 3, characterized in that: and the third input end of the register forms self feedback with the first output end through the second AND gate.
5. The clockless chip wake-up circuit according to claim 3, characterized in that: the state recovery module comprises a second trigger, a third AND gate, a second phase inverter and a NAND gate, wherein a first input end of the second trigger is respectively connected with an output end of the third AND gate and a second input end of the first trigger, a second output end of the second trigger is respectively connected with an output end of the first AND gate and a second input end of the NAND gate, an output end of the second trigger is connected with an input end of the second phase inverter, a first input end of the third AND gate is connected with a reset signal, a second input end of the third AND gate is connected with a second output end of the register, an output end of the second trigger is connected with a second input end of the first trigger, an output end of the second phase inverter is connected with a first input end of the NAND gate, a second output end of the NAND gate is further connected with an output end of the first AND gate.
6. The clockless chip wake-up circuit according to claim 1 or 5, characterized in that: the trigger is an RS trigger.
7. A chip with a wake-up function is characterized in that: the chip is integrated with the clockless chip wake-up circuit of any one of claims 1 to 6.
8. A clock-free chip wake-up circuit wake-up method is used for waking up a CPU in a chip, and is characterized by comprising the following steps:
collecting an input signal to be detected;
detecting whether a signal to be detected is input, and if the signal to be detected is input, outputting a signal to be detected by an output end of the state detection module;
the state latch module generates a wake-up signal according to the signal to be detected and latches the conversion state;
and after the wake-up signal is generated, resetting, recovering to a detection state, and detecting again.
9. The clock-less chip wake-up circuit wake-up method of claim 8, wherein: when a signal to be detected is input, the first trigger is triggered, the state of the first trigger is changed, the first trigger is input into the register, the state of the register is changed, a wake-up signal is sent out, a CPU in the chip is awakened, meanwhile, the register latches data information, the wake-up signal is cleared, the state of the register is changed, the state of the second trigger is changed, and therefore the state of the first trigger is changed, and the detection state is restored.
10. The clock-less chip wake-up circuit wake-up method of claim 9, wherein: when a signal to be detected is input, the output of the exclusive-or gate is high level, the output of the first and gate is high level, at this time, the output of the Q non-end of the output end of the second trigger is low level, after passing through the second inverter, the output of the second inverter is high level, and is input into the nand gate together with the output of the exclusive-or gate, the output of the nand gate is low level, when the first input end R end of the first trigger receives low level, the reset is effective, the output of the Q end is low level, the output of the Q non-end of the output end is high level, the output of the first inverter passes through the first inverter, the low level is output into the SB end of the first input end of the register, at this time, the output of the Q end of the first output end of the register is high level, a wake-up signal is sent, the CPU in the chip is, the output of the third AND gate is low level and is input to the R end of the first input end of the second trigger, the second trigger is effective, the Q non-end output of the output end of the second trigger is high level, the Q non-end output of the second inverter is low level through the second inverter, the Q non-end output of the NAND gate is high level, the R end of the first input end of the first trigger is ineffective, the second input end of the first trigger is connected with the output end of the third AND gate at the moment, the output of the third AND gate is low level, the Q non-end output of the output end of the first trigger 2 is low level, after the first inverter, the inverter outputs high level and is input to the SB end of the first input end of the register, the state is ineffective at the moment, the state of the detection circuit is recovered and recovered to the detection.
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| CN114996196B (en) * | 2022-08-04 | 2022-10-21 | 北京数字光芯集成电路设计有限公司 | I2C communication drive circuit, micro display chip and electronic equipment |
| WO2024078147A1 (en) * | 2022-10-13 | 2024-04-18 | 华润微集成电路(无锡)有限公司 | Power consumption control circuit, chip, and electronic device |
| CN115686635B (en) * | 2023-01-03 | 2023-04-18 | 杭州米芯微电子有限公司 | MCU structure without clock circuit and corresponding electronic equipment |
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