CN111934666A - Key circuit with system awakening function and specific function - Google Patents
Key circuit with system awakening function and specific function Download PDFInfo
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- CN111934666A CN111934666A CN202010558929.1A CN202010558929A CN111934666A CN 111934666 A CN111934666 A CN 111934666A CN 202010558929 A CN202010558929 A CN 202010558929A CN 111934666 A CN111934666 A CN 111934666A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4418—Suspend and resume; Hibernate and awake
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Abstract
The invention relates to the technical field of keys, in particular to a key circuit with a system awakening function and a specific function, which comprises a key module, a phase inverter circuit module, a key state latch module, a system power supply control module and an MCU circuit module, wherein the key module, the phase inverter circuit module, the key state latch module and the system power supply control module are sequentially connected with one another, and the problems that the number of keys is large and material management is inconvenient due to the fact that the traditional awakening key and the specific function key are independent from one another, and the awakening key is large in size and high in cost due to the fact that the awakening key is required to be provided with. The invention can realize the system awakening function and the specific function through a single common key, thereby reducing the power consumption and the number of keys and facilitating the use of users; the invention does not need to additionally increase a wake-up key, reduces the material cost, is convenient for material management, and has the advantages of simple and practical circuit, strong anti-interference capability and high reliability.
Description
Technical Field
The present invention relates to the field of key technology, and in particular, to a key circuit having both a system wake-up function and a specific function.
Background
The current engineering vehicle combination instruments are all provided with keys, and corresponding functions are realized through the keys, such as a wake-up key for waking up a system and function keys for other specific functions (for example, an up key, a down key and the like for menu selection).
However, the conventional key for waking up the system function and the conventional key for other specific functions are mostly independent from each other, and the two keys are different in type, so that the number and the type of the keys to be designed are large, the space resource is occupied, the use experience of a user is influenced, and meanwhile, the material cost and the management difficulty are increased;
moreover, the key for waking up the system generally adopts a mechanical key with a latching function, and such mechanical keys are generally large in size and high in cost.
Disclosure of Invention
The invention provides a key circuit with a system awakening function and a specific function, and solves the technical problems that the number of keys is large and material management is inconvenient due to the fact that a traditional awakening key and a specific function key are independent, and the awakening key is large in size and high in cost due to the fact that the awakening key is required to be provided with a latching function.
In order to solve the technical problems, the invention provides a key circuit with a system awakening function and a specific function, which comprises a key module (1), a phase inverter circuit module (2), a key state latch module (3) and a system power supply control module (4) which are sequentially connected, and further comprises an MCU circuit module (5) which is connected with the key module (1) and the key state latch module (3);
the MCU circuit module (5) is used for outputting a dormancy logic control signal to the key state latch module (3) when the system is converted from a working state to a dormancy state;
the key state latch module (3) is used for controlling the output voltage of the system power supply control module (4) to be zero according to the dormancy logic control signal so as to enable the MCU circuit module (5) not to work;
the key module (1) is used for collecting the working state of the key when the system is in a dormant state, outputting a key state signal to the phase inverter circuit module (2) when the key is pressed down, and outputting a key working signal to the MCU circuit module (5);
the phase inverter circuit module (2) is used for carrying out phase inversion on the received key state signal and outputting a wake-up signal to the key state latch module (3);
the key state latch module (3) is also used for latching according to the wake-up signal and outputting a system power supply enable signal to the system power supply control module (4);
the system power supply control module (4) is used for outputting a system power supply according to the system power supply enabling signal so as to enable the MCU circuit module (5) to work;
the MCU circuit module (5) is also used for executing a specific function according to the key working signal in a working state;
according to the technical scheme, the key circuit with the system awakening function and the specific function is provided, so that the effect that a common key has the system awakening function and the specific function is achieved, the use by a user is facilitated, and the occupied space is reduced; meanwhile, the key state latch module (3) achieves a latch function, the problems that the existing awakening key needs to have the latch function, so that the size is large and the cost is high are solved, the size is reduced, and the key state latch module is simple in circuit and low in cost.
In a further embodiment, the key module (1) comprises at least a first key unit (11) and a second key unit (12) both connected to the MCU circuit module (5) and the inverter circuit module (2), the first key unit (11) and the second key unit (12) being provided with a first key (SB1) and a second key (SB2), respectively;
the first key unit (11) is used for acquiring the working state of the first key (SB1), outputting a first key state signal to the inverter circuit module (2) when the first key (SB1) is pressed, and outputting a first key working signal to the MCU circuit module (5);
the second key unit (12) is configured to collect a working state of the second key (SB2), output a second key state signal to the inverter circuit module (2) when the second key (SB2) is pressed, and output a second key working signal to the MCU circuit module (5);
wherein the first key (SB1) and the second key (SB2) are mechanical keys.
In the technical scheme, in the sleep state, when the first key (SB1) or the second key (SB2) is pressed, the first key unit (11) or the second key unit (12) achieves the purposes of enabling the MCU circuit module (5) to work and waking up the system by sending key state signals; when the MCU circuit module (5) is in a normal working state, the MCU circuit module (5) determines whether the first key (SB1) or the second key (SB2) is pressed according to the detected key working signal, and then executes a specific function after determining that the key is pressed; in addition, according to the technical scheme, the awakening key is not required to be additionally arranged, so that the power consumption is saved, the material cost is reduced, the number of used keys is reduced, and the occupied space of the keys is small.
In a further embodiment, the first key unit (11) is provided with a first diode (D1), a second diode (D2), a first resistor (R1), a second resistor (R2) and a first capacitor (C1) in addition to the first key (SB 1);
a first Pin (Pin1) and a second Pin (Pin2) at one end of the internal switch of the first key (SB1) are both grounded, a third Pin (Pin3) and a fourth Pin (Pin4) at the other end are communicated internally, and the outside of the third Pin (Pin3) of the first key (SB1) is also connected with the cathode of the first diode (D1), the cathode of the second diode (D2) and the fourth Pin (Pin4) of the first key (SB 1); an anode of the first diode (D1) is used for outputting the first key state signal to the inverter circuit module (2) when the first key (SB1) is pressed; the positive pole of second diode (D2) is connected the one end of first resistance (R1) with the one end of second resistance (R2), non-permanent power supply (VCC2) is connected to the other end of first resistance (R1), the other end of second resistance (R2) is used for when first button (SB1) is pressed the output first button working signal extremely the first button detection terminal (GPIO1) of MCU circuit module (5), and through first electric capacity (C1) ground connection.
In the technical scheme, the first key unit (11) mainly collects the first key state signal through the first diode (D1), and also collects the first key working signal through the second diode (D2), the second resistor (R2) and the first capacitor (C1); in a dormant state, after the key is pressed down, the first key unit (11) outputs the first key state signal to the inverter circuit module (2) and outputs the first key working signal to the MCU circuit module (5), so that the MCU circuit module (5) starts to work, and the system is awakened and the specific function is executed.
The second key unit (12) is provided with a third diode (D3), a fourth diode (D4), a third resistor (R3), a fourth resistor (R4) and a second capacitor (C2) besides the second key (SB 2);
a first Pin (Pin1) and a second Pin (Pin2) at one end of the internal switch of the second key (SB2) are both grounded, a third Pin (Pin3) and a fourth Pin (Pin4) at the other end are communicated internally, and the outside of the third Pin (Pin3) of the second key (SB2) is also connected with the cathode of the third diode (D3), the cathode of the fourth diode (D4) and the fourth Pin (Pin4) of the second key (SB 2); an anode of the third diode (D3) is used to output the second key state signal to the inverter circuit module (2) when the second key (SB2) is pressed; an anode of the fourth diode (D4) is connected to one end of the third resistor (R3) and one end of the fourth resistor (R4), the other end of the third resistor (R3) is connected to the non-constant power supply (VCC2), and the other end of the fourth resistor (R4) is used for outputting the second key operation signal to the second key detection terminal (GPIO2) of the MCU circuit module (5) when the second key (SB2) is pressed, and is grounded through the second capacitor (C2).
In the present technical solution, the second key unit (12) mainly collects the second key state signal through the third diode (D3), and also collects the second key operation signal through the fourth diode (D4), the fourth resistor (R4) and the second capacitor (C2); in a dormant state, when the key is pressed down, the second key unit (12) outputs the second key state signal to the inverter circuit module (2) and outputs the second key working signal to the MCU circuit module (5), so that the MCU circuit module (5) starts to work, and the system is awakened and the specific function is executed.
In a further embodiment, the inverter circuit module (2) includes a first MOS transistor (N1), fifth to eighth resistors (R5 to R8), and a third capacitor (C3);
the source (S) of the first MOS transistor (N1) is grounded, the drain (D) is connected with the key state latch module (3) and is connected with a constant power supply (VCC1) through the sixth resistor (R6), and the gate (G) is connected with one end of the seventh resistor (R7), one end of the eighth resistor (R8) and one end of the third capacitor (C3); the other end of the eighth resistor (R8) and the other end of the third capacitor (C3) are grounded; the other end of the seventh resistor (R7) is connected with the key module (1) and is connected with the constant power supply (VCC1) through the fifth resistor (R5);
the first MOS tube (N1) is an N-channel enhancement type MOS tube;
in the technical scheme, the phase inverter circuit module (2) is mainly used for carrying out phase reversal on the received first key state signal and the received second key state signal through the first MOS tube (N1), outputting the awakening signal to the key state latch module (3), and is simple and practical in circuit and high in stability.
In a further embodiment, the key state latch module (3) includes a D flip-flop chip (U1), ninth to seventeenth resistors (R9 to R17), fourth to eighth capacitors (C4 to C8), and a first transistor (Q1);
a power supply input end (VCC) of the D trigger chip (U1) is connected with the constant power supply (VCC1) and one end of the sixth capacitor (C6), and the other end of the sixth capacitor (C6) is grounded;
an asynchronous reset input of the D flip-flop chip (U1)
The collector (C) of the first triode (Q1), one end of the fifth capacitor (C5) and one end of the ninth resistor (R9) are connected, the other end of the fifth capacitor (C5) is grounded, and the other end of the ninth resistor (R9) is connected with the constant power supply (VCC 1); an emitter (E) of the first triode (Q1) is grounded, a base (B) is connected with one end of the fourth capacitor (C4), one end of the tenth resistor (R10), one end of the eleventh resistor (R11), the other end of the fourth capacitor (C4) and the baseThe other end of the eleventh resistor (C11) is grounded, and the other end of the tenth resistor (R10) is connected with a sleep logic control terminal (GPIO4) of the MCU circuit module (5);
the data input end (D) of the D flip-flop chip (U1) is connected with the constant power supply (VCC1) through the twelfth resistor (R12);
a clock input end (CP) of the D trigger chip (U1) is connected with a drain electrode (D) of the first MOS tube (N1) through the thirteenth resistor (R13), and the clock input end (CP) is also connected with a first RC parallel filter circuit formed by the fifteenth resistor (R15) and the seventh capacitor (C7) and then grounded;
an asynchronous digital input terminal of the D flip-flop chip (U1)
-connecting said constant supply source (VCC1) through said fourteenth resistor (R14);
the same-direction output end (Q) of the D trigger chip (U1) is connected with a power supply enabling end of a system power supply control module (4) and is also connected with one end of the sixteenth resistor (R16); the other end of the sixteenth resistor (R16) is connected with a key awakening control end (GPIO3) of the MCU circuit module (5), and is also connected with a second RC parallel filter circuit consisting of the seventeenth resistor (R17) and the eighth capacitor (C8) and then is grounded;
an inverted output terminal of the D flip-flop chip (U1)
Vacant;
the grounding end (GND) of the D trigger chip (U1) is grounded.
In the technical scheme, in a dormant state, after a key is pressed down, the key state latch module (3) receives the wake-up signal and outputs a system power enable signal to the system power control module (4) through the thirteenth resistor (R13), a clock input end (CP) of the D-flip-flop chip (U1) and a syntropy output end (Q), so that a latch function is realized and the system power control module (4) is controlled to enable, the circuit is simple, practical and high in stability, a complex and large-size latch wake-up key in the prior art is not needed, the key space is saved, and the product appearance is beautified; under the normal working state, the key state latch module (3) mainly controls the system power supply enabling signal through the first triode (Q1) and the D trigger chip (U1) according to the dormancy logic control signal, so that the voltage of the system power supply is zero, and the MCU circuit module (5) does not work.
In a further embodiment, the system power control module (4) includes eighteenth resistor (R18) to twenty-first resistor (R21), ninth capacitor (C9) to eleventh capacitor (C11), first magnetic bead (L1), second MOS transistor (P1), and second transistor (Q2);
a source electrode (S) of the second MOS transistor (P1) is connected with the constant power supply (VCC1), a drain electrode (D) is connected with one end of the first magnetic bead (L1), and a grid electrode (G) is connected with a collector electrode (C) of the second triode (Q2) through the nineteenth resistor (R19); an emitter (E) of the second triode (Q2) is grounded, a base (B) is connected with one end of a twentieth resistor (R20), one end of a twenty-first resistor (R21) and one end of an eleventh capacitor (C11), the other end of the twentieth resistor (R20) is connected with a same-direction output end (Q) of the D flip-flop chip (U1), and the other end of the twenty-first resistor (R21) and the other end of the eleventh capacitor (C11) are grounded;
the other end of the first magnetic bead (L1) is connected with a system power supply and is grounded through the tenth capacitor (C10), and two ends of a third RC parallel filter circuit consisting of the eighteenth resistor (R18) and the ninth capacitor (C9) are respectively connected with the source (S) and the gate (G) of the second MOS tube (P1);
the second MOS tube (P1) is a P-channel enhancement type MOS tube;
the second triode (Q2) is an NPN type triode.
In the technical scheme, the system power supply control module (4) receives the system power supply enabling signal, and the system power supply voltage is controlled through the second MOS tube (P1), the second triode (Q2) and the first magnetic bead (L1), so that the MCU circuit module (5) is controlled to work, and the power consumption is reduced.
In a further embodiment, the MCU circuit module (5) comprises an MCU chip (U2);
the MCU chip (U2) at least comprises the first key detection terminal (GPIO1), the second key detection terminal (GPIO2), the key wake-up control terminal (GPIO3) and the sleep logic control terminal (GPIO 4).
In the technical scheme, when the MCU circuit module (5) normally operates and the first key (SB1) or the second key (SB2) is pressed, the MCU circuit module (5) determines that the system is woken up by the first key (SB1) or the second key (SB2) through the key wake-up control terminal (GPIO3), detects the first or second key operating signal through the first key detection terminal (GPIO1) or the second key detection terminal (GPIO2), and determines whether the first key (SB1) or the second key (SB2) is pressed, thereby implementing the specific function of the key; after the system receives a sleep instruction, the MCU circuit module (5) outputs a sleep logic control signal through the sleep logic control terminal (GPIO4) so as to control the key state latch module (3) to enable the system to enter a sleep state; the whole circuit of this technical scheme is simple and practical, and the interference killing feature is strong, and the reliability is high.
Drawings
Fig. 1 is a block diagram of a key circuit having both a system wake-up function and a specific function according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a key module according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of an inverter circuit module according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a key state latch module according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a system power control module according to an embodiment of the present invention;
fig. 6 is a circuit schematic diagram of an MCU circuit module according to an embodiment of the present invention.
And (3) graphic labeling:
a key module 1 (a first key unit 11, a second key unit 12);
an inverter circuit module 2; a key state latch module 3;
a system power supply control module 4; an MCU circuit module 5;
a first button SB 1; a second button SB 2; a first diode D1 to a fourth diode D4;
the first resistor R1-the twenty-first resistor R21; the first capacitor C1-the eleventh capacitor C11;
a first transistor Q1; a second transistor Q2; a first MOS transistor N1; a second MOS transistor P1;
d flip-flop chip U1; an MCU chip U2; first magnetic beads L1;
a constant supply voltage VCC 1; a non-constant supply voltage VCC 2.
Detailed Description
The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, which are given solely for the purpose of illustration and are not to be construed as limitations of the invention, including the drawings which are incorporated herein by reference and for illustration only and are not to be construed as limitations of the invention, since many variations thereof are possible without departing from the spirit and scope of the invention.
Aiming at the problems that the traditional awakening key and the special function key are independent respectively, so that the number of keys is large, the material management is inconvenient, and the awakening key needs to be provided with a latching function, so that the volume is large and the cost is high, the embodiment of the invention provides a key circuit with a system awakening function and a special function, and the embodiment of the invention can be applied to all electronic products with key functions, such as: electronic products such as automobile combination instruments, automobile navigators, key-type mobile phones, televisions and the like; for convenience of description, the embodiment of the present invention is mainly exemplified by including two keys, and as shown in the structural schematic diagram shown in fig. 1, the embodiment of the present invention includes a key module 1, an inverter circuit module 2, a key state latch module 3, and a system power control module 4, which are connected in sequence, and further includes an MCU circuit module 5 connecting the key module 1 and the key state latch module 3;
the key module 1 at least comprises a first key unit 11 and a second key unit 12 which are connected with the MCU circuit module 5 and the phase inverter circuit module 2, and the first key unit 11 and the second key unit 12 are respectively provided with a first key SB1 and a second key SB 2;
the first key unit 11 is configured to collect a working state of the first key SB1, and output a first key state signal Button _ on1 to the inverter circuit module 2 and output a first key working signal 2up _ Button1 to the MCU circuit module 5 when the first key SB1 is pressed;
the second key unit 12 is configured to collect a working state of the second key SB2, and output a second key state signal Button _ on2 to the inverter circuit module 2 and output a second key working signal 2up _ Button2 to the MCU circuit module 5 when the second key SB2 is pressed;
in the embodiment of the present invention, the key module 1 acquires the working state of the key when the system is in the sleep state, and outputs a key state signal Button _ onN to the inverter circuit module 2 and a key working signal 2up _ Button n to the MCU circuit module 5 when the key is pressed;
in this embodiment, the first button SB1 and the second button SB2 are mechanical buttons.
The first key unit 11 is provided with a first diode D1, a second diode D2, a first resistor R1, a second resistor R2 and a first capacitor C1 in addition to the first key SB 1;
a first Pin1 and a second Pin2 at one end of the switch inside the first button SB1 are both grounded, a third Pin3 and a fourth Pin4 at the other end are communicated with each other inside, and the outside of the third Pin3 of the first button SB1 is also connected with the cathode of the first diode D1, the cathode of the second diode D2 and the fourth Pin4 of the first button SB 1; the anode of the first diode D1 is used for outputting the first key state signal Button _ on1 to the inverter circuit module 2 when the first key SB1 is pressed; the anode of the second diode D2 is connected with one end of the first resistor R1 and one end of the second resistor R2, the other end of the first resistor R1 is connected with a non-constant power supply VCC2, and the other end of the second resistor R2 is used for outputting the first key operation signal 2up _ button1 to the first key detection terminal GPIO1 of the MCU circuit module 5 when the first key SB1 is pressed, and is grounded through the first capacitor C1.
In this embodiment, the voltage of the non-constant power supply VCC2 in the system sleep state is 0V, and the voltage returns to normal after the system is awakened.
The second key unit 12 includes a third diode D3, a fourth diode D4, a third resistor R3, a fourth resistor R4 and a second capacitor C2, in addition to a second key SB 2;
a first Pin1 and a second Pin2 at one end of the switch inside the second button SB2 are both grounded, a third Pin3 and a fourth Pin4 at the other end are communicated with each other inside, and the outside of the third Pin3 of the second button SB2 is also connected with the cathode of the third diode D3, the cathode of the fourth diode D4 and the fourth Pin4 of the second button SB 2; the anode of the third diode D3 is used for outputting the second key state signal Button _ on2 to the inverter circuit module 2 when the second key SB2 is pressed; the positive pole of the fourth diode D4 is connected with one end of the third resistor R3 and one end of the fourth resistor R4, the other end of the third resistor R3 is connected with the non-constant power supply VCC2, and the other end of the fourth resistor is used for outputting the second key operation signal 2up _ button2 to the second key detection terminal GPIO2 of the MCU circuit module 5 when the second key SB2 is pressed, and is grounded through the second capacitor C2.
The inverter circuit module 2 comprises a first MOS transistor N1, fifth to eighth resistors R5 to R8 and a third capacitor C3;
a source S of the first MOS transistor N1 is grounded to GND, a drain D is connected to the key state latch module 3 and to a constant power supply VCC1 through the sixth resistor R6, and a gate G is connected to one end of the seventh resistor R7, one end of the eighth resistor R8, and one end of the third capacitor C3; the other end of the eighth resistor R8 and the other end of the third capacitor C3 are grounded; the other end of the seventh resistor R7 is connected with the key module 1 and is connected with the constant power supply VCC1 through the fifth resistor R5;
the voltage of the constant power supply VCC1 is normal in a system sleep state and after the system is awakened; the first MOS transistor N1 is an N-channel enhancement type MOS transistor.
In this embodiment, the inverter circuit module 2 performs level inversion on the received key state signal Button _ onN, and outputs a wakeup signal Button _ wakeup to the key state latch module 3;
the key state latch module 3 comprises a D flip-flop chip U1, ninth to seventeenth resistors R9 to R17, fourth to eighth capacitors C4 to C8, and a first triode Q1;
a power supply input terminal VCC of the D flip-flop chip U1 is connected to the constant power supply VCC1 and one end of the sixth capacitor C6, and the other end of the sixth capacitor C6 is grounded;
asynchronous reset input end of D flip-flop chip U1
The collector C of the first triode Q1, one end of the fifth capacitor C5 and one end of the ninth resistor R9 are connected, the other end of the fifth capacitor C5 is grounded GND, and the other end of the ninth resistor R9 is connected to the constant power supply VCC 1; an emitter E of the first triode Q1 is grounded GND, a base B is connected to one end of the fourth capacitor C4, one end of the tenth resistor R10 and one end of the eleventh resistor R11, the other end of the fourth capacitor C4 and the other end of the eleventh resistor R11 are grounded, and the other end of the tenth resistor R10 is connected to the sleep logic control terminal GPIO4 of the MCU circuit block 5;
the data input end D of the D flip-flop chip U1 is connected with the constant power supply VCC1 through the twelfth resistor R12;
a clock input end CP of the D flip-flop chip U1 is connected with a drain D of the first MOS transistor N1 through the thirteenth resistor R13, and the clock input end CP is also connected with a first RC parallel filter circuit formed by the fifteenth resistor R15 and the seventh capacitor C7 and then grounded;
asynchronous digital input end of D flip-flop chip U1
The fourteenth resistor R14 is connected with the constant power supply VCC 1;
the equidirectional output end Q of the D trigger chip U1 is connected with a power supply enabling end of a system power supply control module 4 and is also connected with one end of the sixteenth resistor R16; the other end of the sixteenth resistor R16 is connected with a key awakening control end GPIO3 of the MCU circuit module 5, and is also connected with a second RC parallel filter circuit consisting of the seventeenth resistor R17 and the eighth capacitor C8 and then is grounded;
the reverse output end of the D flip-flop chip U1
Vacant;
the ground terminal GND of the D flip-flop chip U1 is grounded.
In the embodiment of the present invention, the key state latch module 3 controls the system power control module 4 according to the sleep logic control signal up2_ button _ wake _ clear, so that the voltage of the system power is zero, the MCU circuit module 5 does not operate, and the system enters a sleep state;
the key state latch module 3 further latches according to the wakeup signal Button _ wakeup, and outputs a System Power enable signal System _ Power _ EN to the System Power control module 4, so as to control the System Power voltage, so that the MCU circuit module 5 starts to operate, and the System is awakened. The embodiment of the invention realizes the key latching function through the key state latching module 3, reduces the volume and also reduces the cost.
The functional table of the D flip-flop chip U1 is shown in table 1:
TABLE 1
Wherein, in table 1:
l: a low level;
h: a high level;
x: are not considered for the moment;
In the embodiment of the invention, the asynchronous reset input terminal of the D flip-flop chip U1
The asynchronous setting input end is effective at low level
Active low.
The system power control module 4 comprises eighteenth resistor R18 to twenty-first resistor R21, ninth capacitor C9 to eleventh capacitor C11, first magnetic bead L1, second MOS transistor P1 and second triode Q2;
a source S of the second MOS transistor P1 is connected to the constant power supply VCC1, a drain D is connected to one end of the first magnetic bead L1, and a gate G is connected to a collector C of the second triode Q2 through the nineteenth resistor R19; an emitter E of the second triode Q2 is grounded, a base B is connected with one end of a twentieth resistor R20, one end of a twenty-first resistor R21 and one end of an eleventh capacitor C11, the other end of the twentieth resistor R20 is connected with a homodromous output end Q of the D flip-flop chip U1, and the other end of the twenty-first resistor R21 and the other end of the eleventh capacitor C11 are grounded;
the other end of the first magnetic bead L1 is connected with a System Power VCC _ System _ Power and passes through the tenth capacitor C10 is grounded, and the eighteenth resistor R18 and the two ends of a third RC parallel filter circuit consisting of the ninth capacitor C9 are respectively connected with the source S and the grid G of the second MOS tube.
In this embodiment, the System Power control module 4 controls enabling of the System Power VCC _ System _ Power according to the System Power enable signal System _ Power _ EN, so as to enable the MCU circuit module 5 to operate;
in this embodiment, the second MOS transistor P1 is a P-channel enhancement MOS transistor; the second triode Q2 is an NPN type triode.
The MCU circuit module 5 comprises an MCU chip U2;
the MCU chip U2 at least comprises the first key detection terminal GPIO1, the second key detection terminal GPIO2, the key wake-up control terminal GPIO3 and the sleep logic control terminal GPIO 4.
When the system is converted from the working state to the sleep state, the sleep logic control terminal GPIO4 of the MCU circuit module 5 outputs a sleep logic control signal up2_ button _ wake _ clear to the key state latch module 3, and then the system power is controlled to be zero by the system power control module 4, so that the MCU circuit module 5 stops working normally and the system enters the sleep state;
in a normal working state of the system, when one of the keys is pressed, the key wake-up control terminal GPIO3 of the MCU circuit module 5 determines that the key of the system is pressed according to the received key wake-up signal 2up _ button _ wakeup; the MCU circuit module 5 also determines whether a key is pressed according to the received key operation signal 2up _ button n, thereby performing a specific function.
The embodiment of the invention divides the circuit into different working states, and the specific working principle of each state is as follows:
1) the working principle of the normal working state to the dormant state is as follows:
when the MCU chip U2 receives a command that a system is going to enter a sleep state, the MCU circuit module 5 outputs the sleep logic control signal up2_ button _ wake _ clear through the sleep logic control terminal GPIO4 thereof, and at this time, the sleep logic control signal up2_ button _ wake _ clear is at a high level; the sleep logic control signal up2_ button _ wake _ clear is transmitted to the base B of the first transistor Q1 after passing through the voltage division of the tenth resistor R10, the eleventh resistor R11 and the filtering of the fourth capacitor C4 in the key state latch module 3, so that the first transistor Q1 is turned on, and thus, the asynchronous reset input of the D flip-flop U1 is turned on
The input level signal is low level, because under the normal working state of the system, the asynchronous setting input end of the D trigger chip U1
The input level signal is the high level, and can be known from table 1, D flip-flop chip U1 the System Power enable signal System _ Power _ EN that syntropy output Q was exported is the low level, and passes through in the System Power control module 4 twentieth resistance R20, twenty first resistance R21 partial pressure with transmit to after the filtering of eleventh electric capacity C11 the base B of second triode Q2, make second triode Q2 does not conduct, and at this moment, the grid G of second MOS pipe P1 is the high level, second MOS pipe P1 does not conduct, the voltage of System Power VCC _ System _ Power is 0V, MCU circuit module 5 is out of work, and the System gets into the dormant state.
2) The working principle of the sleep state is as follows:
when the System is in a dormant state, the voltage of the System Power supply VCC _ System _ Power is 0V, the voltage of the non-constant Power supply VCC2 is 0V, the voltage of the constant Power supply VCC1 is normal, and the System Power supply enable signal System _ Power _ EN output by the equidirectional output end Q of the D flip-flop chip U1 is at a low level;
when the first key SB1 is not pressed, the first key SB1 is equivalent to an open circuit, and therefore, no current flows through the first diode D1, and at this time, the constant power supply VCC1 is filtered by the fifth resistor R5, the seventh resistor R7, the eighth resistor R8, and the third capacitor C3 in the inverter circuit module 2 and then transmitted to the gate G of the first MOS transistor N1, so that the first MOS transistor N1 is in saturation conduction, and the wakeup signal Button _ wakeup up output by the inverter circuit module 2 is at a low level; then, the wake-up signal Button _ wakeup is transmitted to the clock input end CP of the D flip-flop chip U1 after passing through the voltage division of the thirteenth resistor R13, the fifteenth resistor R15 and the filtering of the seventh capacitor C7 in the key state latch module 3, and as can be known from table 1, the clock input end CP is only effective for a rising edge signal, so that the same-direction output end Q of the D flip-flop chip U1 still outputs the System Power enable signal System _ Power _ EN of a low level;
the System Power enable signal System _ Power _ EN warp in the System Power control module 4 twentieth resistance R20, twenty first resistance R21 partial pressure with eleventh electric capacity C11 transmits after the filtering base B of second triode Q2, make second triode Q2 does not switch on, second MOS pipe P1's grid G is the high level, second MOS pipe P1 does not switch on, the voltage of System Power VCC _ System _ Power is 0V, MCU circuit module 5 is out of work, and the System is in dormant state.
3) In the dormant state, the working principle of the key for realizing the function of the awakening system is as follows:
for convenience of description, the operation principle is mainly described in the first key wake-up system, and the operation principle of the nth key SBn (n is 1,2 …) wake-up system is the same as that of the first key;
in a sleep state, when the first key SB1 is pressed, the first key SB1 is shorted to ground, the first diode D1 has a current flowing through, the voltage of the first key state signal Button _ on1 output by the first key unit 11 is 0.7V, i.e. low level, and is transmitted to the gate G of the first MOS transistor N1 in the inverter circuit module 2 after being divided by the seventh resistor R7, the eighth resistor R8 and the third capacitor C3, so that the first MOS transistor N1 is not turned on, the wake-up signal Button _ wakeup is changed from low level to high level, i.e. a rising edge signal is generated, and the rising edge signal is transmitted to the clock chip CP input terminal of the D flip-flop U1 after being divided by the thirteenth resistor R13, the fifteenth resistor R15 and the seventh capacitor C7 in the key state latch module 3, in a sleep state, the data input terminal D and the asynchronous reset input terminal of the D flip-flop chip U1
And an asynchronous set-number input
As can be seen from table 1, the System Power enable signal System _ Power _ EN output by the equidirectional output end Q of the D flip-flop chip U1 is at a high level, and is filtered by the twentieth resistor R20, the twenty-first resistor R21 and the eleventh capacitor C11 in the System Power control module 4 and then transmitted to the base B of the second triode Q2, so that the second triode Q2 is not turned on, the gate G of the second MOS transistor P1 is at a low level, the second MOS transistor P1 is turned on, the voltage of the System Power VCC _ System _ Power is equal to the voltage of the VCC1 Power, the MCU circuit module 5 starts to operate, and the System is awakened;
meanwhile, the key state latch module 3 divides the System Power enable signal System _ Power _ EN of high level by the sixteenth resistor R16 and the seventeenth resistor R17 and filters the System Power enable signal System _ Power _ EN by the eighth capacitor C8, and outputs the key wake-up signal 2up _ button _ wakeup to the MCU chip U2 of the MCU circuit module 5, at this time, the key wake-up signal 2up _ button _ wakeup is of high level, and the MCU chip U2 detects the key wake-up signal 2up _ button _ wakeup as of high level by the key wake-up control terminal GPIO3, and then it is determined that the System is woken up by the first key wake-up block 1, so as to perform related functional operations.
4) Under the normal operating condition, the operating principle of realizing the specific function by the key is as follows:
when the System is in a normal working state, the voltages of the System Power supply VCC _ System _ Power, the constant Power supply VCC1 and the non-constant Power supply VCC2 are all normal, and the homodromous output end Q of the D trigger chip U1 outputs a high level;
when the first key SB1 is not pressed, the first key SB1 corresponds to an open circuit, and thus, no current flows through the second diode D2; at this time, after the voltage signal of the non-constant power supply VCC2 passes through the current limiting of the first resistor R1 and the second resistor R2 and the filtering of the first capacitor C1, the first key operation signal 2up _ button1 with high level is output to the first key detection terminal GPIO1 of the MCU chip U2; after the first key detection terminal GPIO1 of the MCU chip U2 detects that the input level is high, it may be determined that the first key SB1 is not pressed;
when the first key SB1 is pressed, the first key SB1 is shorted to ground, so that a current flows through the second diode D2, and at this time, the anode voltage of the second diode D2 is 0.7V, i.e., low level, and this low level signal is current-limited by the second resistor R2 and filtered by the first capacitor C1, and then outputs the first key operation signal 2up _ button1 to the first key detection terminal GPIO1 of the MCU chip U2, and at this time, the first key operation signal 2up _ button1 is low level; after the first key detection terminal GPIO1 of the MCU chip U2 detects that the input level is low, it can determine that the first key SB1 is pressed, thereby performing this key-specific function. The operation principle of the nth key SBn (n is 1,2 …) to implement other specific functions is the same as that of the first key SB1, and is not described herein again.
According to the key circuit with the system awakening function and the specific function, which is provided by the embodiment of the invention, the problems that the number of keys is large and the material management is inconvenient due to the fact that the traditional awakening key and the specific function key are independent respectively are solved through the key module 1, the phase inverter circuit module 2, the key state latch module 3, the system power supply control module 4 and the MCU circuit module 5 which is connected with the key module 1 and the key state latch module 3, and the awakening key is required to be provided with the latch function, so that the size is large and the cost is high are solved, the effects of the awakening function and the specific function of a single key system are realized, the number of keys is reduced, the occupied space is reduced, and the appearance is beautified; meanwhile, the embodiment of the invention realizes the system awakening function through the common key without additionally adding the awakening key, saves the power consumption generated by the awakening key in the prior art, reduces the key type and the material cost, is convenient for material management, and has simple circuit, high stability and strong anti-interference capability.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.
Claims (10)
1. A key circuit with both system wake-up function and specific function is characterized in that: the key state latch circuit comprises a key module (1), a phase inverter circuit module (2), a key state latch module (3) and a system power supply control module (4) which are sequentially connected, and further comprises an MCU circuit module (5) which is connected with the key module (1) and the key state latch module (3);
the MCU circuit module (5) is used for outputting a dormancy logic control signal to the key state latch module (3) when the system is converted from a working state to a dormancy state;
the key state latch module (3) is used for controlling the output voltage of the system power supply control module (4) to be zero according to the dormancy logic control signal so as to enable the MCU circuit module (5) not to work;
the key module (1) is used for collecting the working state of the key when the system is in a dormant state, outputting a key state signal to the phase inverter circuit module (2) when the key is pressed down, and outputting a key working signal to the MCU circuit module (5);
the phase inverter circuit module (2) is used for carrying out phase inversion on the received key state signal and outputting a wake-up signal to the key state latch module (3);
the key state latch module (3) is also used for latching according to the wake-up signal and outputting a system power supply enable signal to the system power supply control module (4);
the system power supply control module (4) is used for outputting a system power supply according to the system power supply enabling signal so as to enable the MCU circuit module (5) to work;
the MCU circuit module (5) is also used for executing specific functions according to the key working signals in a working state.
2. The key circuit of claim 1 having both a wake-up function and a special function, wherein: the key module (1) at least comprises a first key unit (11) and a second key unit (12) which are connected with the MCU circuit module (5) and the phase inverter circuit module (2), and the first key unit (11) and the second key unit (12) are respectively provided with a first key (SB1) and a second key (SB 2);
the first key unit (11) is used for acquiring the working state of the first key (SB1), outputting a first key state signal to the inverter circuit module (2) when the first key (SB1) is pressed, and outputting a first key working signal to the MCU circuit module (5);
the second key unit (12) is used for collecting the working state of the second key (SB2), outputting a second key state signal to the phase inverter circuit module (2) when the second key (SB2) is pressed, and outputting a second key working signal to the MCU circuit module (5).
3. The key circuit of claim 2 having both a wake-up function and a special function, wherein: the first key unit (11) is provided with a first diode (D1), a second diode (D2), a first resistor (R1), a second resistor (R2) and a first capacitor (C1) besides the first key (SB 1);
a first Pin (Pin1) and a second Pin (Pin2) at one end of the internal switch of the first key (SB1) are both grounded, a third Pin (Pin3) and a fourth Pin (Pin4) at the other end are communicated internally, and the outside of the third Pin (Pin3) of the first key (SB1) is also connected with the cathode of the first diode (D1), the cathode of the second diode (D2) and the fourth Pin (Pin4) of the first key (SB 1); an anode of the first diode (D1) is used for outputting the first key state signal to the inverter circuit module (2) when the first key (SB1) is pressed; the positive pole of second diode (D2) is connected the one end of first resistance (R1) with the one end of second resistance (R2), non-permanent power supply (VCC2) is connected to the other end of first resistance (R1), the other end of second resistance (R2) is used for when first button (SB1) is pressed the output first button working signal extremely the first button detection terminal (GPIO1) of MCU circuit module (5), and through first electric capacity (C1) ground connection.
4. A push-button circuit having both wake-up and special function functions as claimed in claim 3, wherein: the second key unit (12) is provided with a third diode (D3), a fourth diode (D4), a third resistor (R3), a fourth resistor (R4) and a second capacitor (C2) besides the second key (SB 2);
a first Pin (Pin1) and a second Pin (Pin2) at one end of the internal switch of the second key (SB2) are both grounded, a third Pin (Pin3) and a fourth Pin (Pin4) at the other end are communicated internally, and the outside of the third Pin (Pin3) of the second key (SB2) is also connected with the cathode of the third diode (D3), the cathode of the fourth diode (D4) and the fourth Pin (Pin4) of the second key (SB 2); an anode of the third diode (D3) is used to output the second key state signal to the inverter circuit module (2) when the second key (SB2) is pressed; an anode of the fourth diode (D4) is connected to one end of the third resistor (R3) and one end of the fourth resistor (R4), the other end of the third resistor (R3) is connected to the non-constant power supply (VCC2), and the other end of the fourth resistor (R4) is used for outputting the second key operation signal to the second key detection terminal (GPIO2) of the MCU circuit module (5) when the second key (SB2) is pressed, and is grounded through the second capacitor (C2).
5. The key circuit of claim 4 having both wake-up and special features, wherein: the inverter circuit module (2) comprises a first MOS transistor (N1), fifth to eighth resistors (R5 to R8) and a third capacitor (C3);
the source (S) of the first MOS transistor (N1) is grounded, the drain (D) is connected with the key state latch module (3) and is connected with a constant power supply (VCC1) through the sixth resistor (R6), and the gate (G) is connected with one end of the seventh resistor (R7), one end of the eighth resistor (R8) and one end of the third capacitor (C3); the other end of the eighth resistor (R8) and the other end of the third capacitor (C3) are grounded; the other end of the seventh resistor (R7) is connected with the key module (1) and is connected with the constant power supply (VCC1) through the fifth resistor (R5).
6. The key circuit of claim 5 having both wake-up and special features, wherein: the key state latch module (3) comprises a D flip-flop chip (U1), ninth resistors (R9) to seventeenth resistors (R17), fourth capacitors (C4) to eighth capacitors (C8) and a first triode (Q1);
a power supply input end (VCC) of the D trigger chip (U1) is connected with the constant power supply (VCC1) and one end of the sixth capacitor (C6), and the other end of the sixth capacitor (C6) is grounded;
an asynchronous reset input of the D flip-flop chip (U1)
The collector (C) of the first triode (Q1), one end of the fifth capacitor (C5) and one end of the ninth resistor (R9) are connected, the other end of the fifth capacitor (C5) is grounded, and the other end of the ninth resistor (R9) is connected with the constant power supply (VCC 1); an emitter (E) of the first triode (Q1) is grounded, a base (B) is connected with one end of the fourth capacitor (C4), one end of the tenth resistor (R10) and one end of the eleventh resistor (R11), the other end of the fourth capacitor (C4) and the other end of the eleventh resistor (C11) are grounded, and the other end of the tenth resistor (R10) is connected with a sleep logic control end (GPIO4) of the MCU circuit module (5);
the data input end (D) of the D flip-flop chip (U1) is connected with the constant power supply (VCC1) through the twelfth resistor (R12);
a clock input end (CP) of the D trigger chip (U1) is connected with a drain electrode (D) of the first MOS tube (N1) through the thirteenth resistor (R13), and the clock input end (CP) is also connected with a first RC parallel filter circuit formed by the fifteenth resistor (R15) and the seventh capacitor (C7) and then grounded;
an asynchronous digital input terminal of the D flip-flop chip (U1)
-connecting said constant supply source (VCC1) through said fourteenth resistor (R14);
the same-direction output end (Q) of the D trigger chip (U1) is connected with a power supply enabling end of a system power supply control module (4) and is also connected with one end of the sixteenth resistor (R16); the other end of the sixteenth resistor (R16) is connected with a key awakening control end (GPIO3) of the MCU circuit module (5), and is also connected with a second RC parallel filter circuit consisting of the seventeenth resistor (R17) and the eighth capacitor (C8) and then is grounded;
an inverted output terminal of the D flip-flop chip (U1)
Vacant;
the grounding end (GND) of the D trigger chip (U1) is grounded.
7. The key circuit of claim 6 having both wake-up and special features, wherein: the system power supply control module (4) comprises eighteenth resistor (R18) to twenty-first resistor (R21), ninth capacitor (C9) to eleventh capacitor (C11), first magnetic bead (L1), second MOS tube (P1) and second triode (Q2);
a source electrode (S) of the second MOS transistor (P1) is connected with the constant power supply (VCC1), a drain electrode (D) is connected with one end of the first magnetic bead (L1), and a grid electrode (G) is connected with a collector electrode (C) of the second triode (Q2) through the nineteenth resistor (R19); an emitter (E) of the second triode (Q2) is grounded, a base (B) is connected with one end of a twentieth resistor (R20), one end of a twenty-first resistor (R21) and one end of an eleventh capacitor (C11), the other end of the twentieth resistor (R20) is connected with a same-direction output end (Q) of the D flip-flop chip (U1), and the other end of the twenty-first resistor (R21) and the other end of the eleventh capacitor (C11) are grounded;
the other end of the first magnetic bead (L1) is connected with a system power supply and is grounded through the tenth capacitor (C10), and two ends of a third RC parallel filter circuit consisting of the eighteenth resistor (R18) and the ninth capacitor (C9) are respectively connected with the source (S) and the grid (G) of the second MOS tube (P1).
8. The key circuit of claim 6 having both wake-up and special features, wherein: the MCU circuit module (5) comprises an MCU chip (U2);
the MCU chip (U2) at least comprises the first key detection terminal (GPIO1), the second key detection terminal (GPIO2), the key wake-up control terminal (GPIO3) and the sleep logic control terminal (GPIO 4).
9. The key circuit of claim 2 having both a wake-up function and a special function, wherein: the first key (SB1) and the second key (SB2) are mechanical keys.
10. The key circuit according to claim 5 or 7, wherein the key circuit has both a wake-up function and a specific function, and further comprises: the first MOS tube (N1) is an N-channel enhancement type MOS tube;
the second MOS tube (P1) is a P-channel enhancement type MOS tube;
the second triode (Q2) is an NPN type triode.
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| CN114859771A (en) * | 2022-03-31 | 2022-08-05 | 北京航天时代光电科技有限公司 | Motion data acquisition and control circuit |
| CN117134469A (en) * | 2023-10-25 | 2023-11-28 | 深圳市龙之源科技股份有限公司 | Battery electric quantity management circuit and method and solar camera |
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| CN103558774A (en) * | 2013-09-24 | 2014-02-05 | 康佳集团股份有限公司 | Arbitrary key wakeup control device and terminal |
| CN103838346A (en) * | 2014-03-14 | 2014-06-04 | 深圳市国显科技股份有限公司 | Method for unlocking household appliance intelligent control system automatically after household appliance intelligent control system is woken and control circuit thereof |
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| US20130283077A1 (en) * | 2012-04-20 | 2013-10-24 | Hon Hai Precision Industry Co., Ltd. | Wake-up circuit and electronic device |
| CN103558774A (en) * | 2013-09-24 | 2014-02-05 | 康佳集团股份有限公司 | Arbitrary key wakeup control device and terminal |
| CN103838346A (en) * | 2014-03-14 | 2014-06-04 | 深圳市国显科技股份有限公司 | Method for unlocking household appliance intelligent control system automatically after household appliance intelligent control system is woken and control circuit thereof |
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| CN114859771A (en) * | 2022-03-31 | 2022-08-05 | 北京航天时代光电科技有限公司 | Motion data acquisition and control circuit |
| CN114859771B (en) * | 2022-03-31 | 2023-08-29 | 北京航天时代光电科技有限公司 | Motion data acquisition and control circuit |
| CN117134469A (en) * | 2023-10-25 | 2023-11-28 | 深圳市龙之源科技股份有限公司 | Battery electric quantity management circuit and method and solar camera |
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