CN219018791U - Time-sharing multiplexing circuit for key detection and level detection - Google Patents
Time-sharing multiplexing circuit for key detection and level detection Download PDFInfo
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Abstract
The utility model provides a time-sharing multiplexing circuit for key detection and level detection, which comprises a micro-control circuit with a multiplexing end, a field effect transistor, a second voltage comparator, a power key detection pin, a key input detection module and an external level input end, wherein the key input detection module is connected with the micro-control circuit, the non-inverting input end of the second voltage comparator is used for inputting reference voltage, the inverting input end of the second voltage comparator is connected with the power key detection pin, the output end of the second voltage comparator is used for outputting a level detection signal to the micro-control circuit, the micro-control circuit is used for outputting a control signal to the grid electrode of the field effect transistor, the drain electrode of the field effect transistor is connected with a battery power supply, and the source electrode of the field effect transistor is connected with the power key detection pin. The utility model realizes the key function multiplexing and the external input high level detection function at the same time, thereby achieving the purposes of reducing the occupied space of the circuit and reducing the hardware cost.
Description
Technical Field
The utility model relates to the technical field of electronic circuits, in particular to a time-sharing multiplexing circuit suitable for key detection and level detection of a power driver.
Background
The portable wireless charging is a portable device integrating charging and wireless power supply, and can enter a low-power consumption standby mode when no other external device consumes power. However, as the current battery safety problem is prominent, manufacturers of various devices pay more and more attention to battery safety, mechanisms such as battery management and high-temperature protection are added, when the electric quantity or temperature of the battery reaches a certain set threshold, the devices can adopt a charging stopping mode to reduce the temperature of the battery, the safety is improved, and the battery is restored to be charged after the temperature of the battery is reduced.
In a mobile wireless charging device, a key detection function and an external level detection function are generally provided, and when a system is not awakened, whether a key is pressed down is detected to awaken the system; when the system wakes up, it is necessary to detect whether the level signal is inputted from the outside in real time. Then, there is no time-sharing multiplexing circuit capable of distinguishing between external input high level and key detection, and both circuits are required to be independently arranged to realize functions, so that the number of components is large, the occupied space of the circuit is large, the space utilization rate is low, and the hardware cost is high.
Disclosure of Invention
The time-sharing multiplexing circuit for key detection and level detection can realize key function multiplexing and external input high-level detection simultaneously, thereby achieving the purposes of reducing the occupied space of the circuit and hardware cost.
The utility model realizes the above purpose through the following technical scheme:
a time division multiplexing circuit for key detection and level detection, comprising: the micro-control circuit is provided with a multiplexing end, a field effect transistor, a second voltage comparator, a power key detection pin, a key input detection module and an external level input end, wherein the key input detection module is respectively connected with the micro-control circuit and the power key detection pin, the non-inverting input end of the second voltage comparator is used for inputting a reference voltage, the inverting input end of the second voltage comparator is connected to the power key detection pin, the output end of the second voltage comparator is used for outputting a level detection signal to the micro-control circuit, the micro-control circuit is used for outputting a control signal to the grid electrode of the field effect transistor, the drain electrode of the field effect transistor is connected with a battery power supply, and the source electrode of the field effect transistor is connected with the power key detection pin;
the external level input end is connected with the power key detection pin and is used for providing an external level input signal.
The key input detection module comprises a key switch and a first voltage comparator, wherein the key switch is connected with the power key detection pin and is used for providing key signals, the non-inverting input end of the first voltage comparator is used for inputting a battery power source with a preset numerical range, the inverting input end of the first voltage comparator is connected to the power key detection pin, and the output end of the first voltage comparator is used for outputting key detection signals to the micro control circuit 。
The micro-control circuit is further used for outputting a driving control signal to the driving circuit, and the driving circuit controls the grid electrode of the field effect transistor.
The power supply circuit comprises a first voltage comparator, a second voltage comparator and a first pull-up resistor, wherein the first pull-up resistor is connected between a power supply pin and an output end of the first voltage comparator, and the second pull-up resistor is connected between a power supply pin and the output end of the second voltage comparator.
The circuit further comprises a voltage dividing circuit composed of a first resistor and a second resistor, wherein the first end of the first resistor is connected to the inverting input end of the first voltage comparator and the second end of the second resistor, the second end of the first resistor is connected with the key input detection module, and the first end of the second resistor is connected with the source electrode of the field effect transistor.
In a further aspect, the circuit further includes a third resistor connected between the inverting input terminal of the second voltage comparator and the external level input terminal.
In a further scheme, the field effect tube is used for communicating the key input detection module with the power supply channel of the first voltage comparator, when the key input detection module is detected to output a key signal, the voltage of the input power supply VIN is smaller than 1/3 battery power after the input power supply VIN is divided by the first resistor and the second resistor, and the output end of the first voltage comparator outputs a high level;
when the key input detection module is detected to not output a key signal, the voltage of the input power supply VIN is larger than 1/3 battery power supply, and the output end of the first voltage comparator outputs a low level.
In a further aspect, when the external level input terminal is detected to input a high level, the voltage of the input power VIN is higher than the Vref voltage, and the output terminal of the second voltage comparator outputs a low level.
In a further aspect, when the external level input terminal is detected to be in a high resistance state, the voltage of the input power VIN is lower than the voltage of Vref, and the output terminal of the second voltage comparator outputs a high level.
In a further scheme, the field effect transistor is a PMOS transistor.
In a further scheme, the field effect transistor is an NMOS transistor.
Therefore, the utility model provides the time-sharing multiplexing circuit for key detection and external level input detection, which has the main functions of distinguishing external input high level from key detection, is ingenious in design, can realize the integration of key detection and external input high level detection, can save the work of hardware design, can save the space of board layout design, and can also reduce the hardware design cost of the circuit.
The utility model is described in further detail below with reference to the drawings and the detailed description.
Drawings
FIG. 1 is a schematic circuit diagram of an embodiment of a time-division multiplexing circuit for key detection and level detection according to the present utility model.
Fig. 2 is a schematic circuit diagram of an external key detection in an embodiment of a time division multiplexing circuit for key detection and level detection according to the present utility model.
FIG. 3 is a timing diagram illustrating operation of the voltage comparator when the system is not awake according to an embodiment of the time division multiplexing circuit for key detection and level detection of the present utility model.
Fig. 4 is a schematic circuit diagram of an embodiment of a time division multiplexing circuit for key detection and level detection according to the present utility model with respect to external input level detection.
FIG. 5 is a timing diagram illustrating operation of the voltage comparator during system wake-up in an embodiment of a time division multiplexing circuit for key detection and level detection according to the present utility model.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present utility model more clear, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. It will be apparent that the described embodiments are some, but not all, embodiments of the utility model. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present utility model fall within the protection scope of the present utility model.
Referring to fig. 1, a time division multiplexing circuit for key detection and level detection according to the present utility model includes: the micro control circuit 10 with multiplexing end, the driving circuit 20, the field effect transistor Q1, the second voltage comparator U2, the power KEY detection pin KEY, the KEY input detection module and the external level input end, the KEY input detection module includes the KEY switch K1, the first voltage comparator U1, the in-phase input end of the first voltage comparator U1 is used for inputting 1/3 battery power VCC1, the inverting input end of the first voltage comparator U1 is connected to the power KEY detection pin KEY, the output end of the first voltage comparator U1 is used for outputting KEY detection signal to the micro control circuit 10, the in-phase input end of the second voltage comparator U2 is used for inputting the reference voltage Vref, the inverting input end of the second voltage comparator U2 is connected to the power KEY detection pin KEY, the output end of the second voltage comparator U2 is used for outputting the level detection signal to the micro control circuit 10, the micro control circuit 10 is used for outputting control signal to the grid electrode of the field effect transistor Q1, the micro control circuit 10 can also be used for outputting driving control signal to the driving circuit 20, the grid electrode of the field effect transistor Q1 is connected to the drain electrode of the field effect transistor Q1, the drain electrode of the field effect transistor Q1 is connected to the drain electrode of the field effect transistor Q1;
the external level input end is connected with the power KEY detection pin KEY and used for providing an external level input signal, and the KEY switch K1 is connected with the power KEY detection pin KEY and used for providing a KEY signal.
The first pull-up resistor is connected between the power supply pin and the output end of the first voltage comparator U1, and the second pull-up resistor is connected between the power supply pin and the output end of the second voltage comparator U2.
In this embodiment, the circuit further includes a voltage divider circuit including a resistor R1 and a resistor R2, where a first end of the resistor R1 is connected to an inverting input end of the first voltage comparator U1 and a second end of the resistor R2, the second end of the resistor R1 is connected to the key input detection module, and the first end of the resistor R2 is connected to a source electrode of the field effect transistor Q1.
In this embodiment, the circuit further includes a resistor R3, and the resistor R3 is connected between the inverting input terminal of the second voltage comparator U2 and the external level input terminal.
In this embodiment, the field effect transistor Q1 is configured to connect the key input detection module with the path of the first voltage comparator U1, when the key input detection module detects that the key input detection module outputs a key signal, the voltage of the input power source VIN is less than 1/3 of the battery power source after the input power source VIN is divided by the resistor R1 and the resistor R2, and the output end of the first voltage comparator U1 outputs a high level.
When the key input detection module is detected to not output a key signal, the voltage of the input power supply VIN is larger than 1/3 of the battery power supply VCC1, and the output end of the first voltage comparator U1 outputs a low level.
When the PMOS transistor is turned on, if the key input detection module is not pressed, vin=vcc 1, and Vout of the first voltage comparator U1 is high; when the PMOS tube is opened, if the key input detection module is pressed down, the voltage is divided by the resistors R2 and R1, vin <1/3VCC1, and Vout is low; and finally, transmitting the result of the first voltage comparator U1 into a main control part.
When the input of the high level from the external level input terminal is detected, the voltage of the input power source VIN is higher than the voltage of Vref, and the low level is output from the output terminal of the second voltage comparator U2.
When the external level input terminal is detected to be in a high resistance state, the voltage of the input power source VIN is lower than the Vref voltage, and the output terminal of the second voltage comparator U2 outputs a high level.
Wherein, when Vin > Vref when the external input is high, vout of the second voltage comparator U2 outputs low level; when the external is in a high resistance state, vin < Vref, the Vout of the second voltage comparator U2 outputs a high level; and finally, transmitting the comparison result to a main control part.
Preferably, the field effect transistor Q1 of the present embodiment is a PMOS transistor, and the field effect transistor Q1 of the present embodiment is not limited to a PMOS transistor, but may be an NMOS transistor or other switching unit having a switch-on function.
Preferably, the key input detection module includes a key switch K1, and the key input detection module is not limited to the key switch, but may be other key input or detection units with key input and detection functions.
In practical application, when the system is not woken up, as shown in fig. 2, other modules of the system are in an inactive state, and only the key is detected to be pressed down to wake up the system. Whether the external key switch K1 is pressed down is detected by opening the PMOS tube at regular time. If the external key switch K1 is not pressed, the voltage of the input power Vin is equal to the battery power VCC1, and the voltage is compared by the first voltage comparator U1, and the VOUT of the first voltage comparator U1 outputs a high level; if the external key is pressed, the voltage of the input power Vin is smaller than 1/3 of the battery power VCC1 through the voltage division of the resistor R2 and the resistor R1, and the voltage is compared by the first voltage comparator U1, and the VOUT of the first voltage comparator U1 outputs a low level. The comparison result is then transferred to the micro control circuit 10 by the first voltage comparator U1, and the operation sequence is shown in fig. 3.
After the system wakes up, as shown in fig. 4, when the external input high level is performed, the voltage of the input power Vin is higher than the voltage of Vref, and the VOUT of the second voltage comparator U2 outputs a low level by comparing with the voltage of Vref by the second voltage comparator U2, if the external input high level is detected, the system cannot detect whether the key is pressed, so that the key detection result is not processed when the external output high level is logically processed; when the outside is in a high resistance state (namely, the outside is provided with a floating state, neither a high level nor a low level is output, the purpose is that the high resistance state does not influence key detection, if the input is low, the system can collide with key detection, so that the system can recognize that the key is pressed down all the time), the input power Vin voltage is lower than Vref voltage, the voltage is compared by the second voltage comparator U2, the Vout of the second voltage comparator U2 outputs the high level, and as no external input exists, namely, the Vin foot cannot be influenced by the external level, the Vin foot is only pulled up to VCC1 or divided by the resistor R2 and the resistor R1, at the moment, the system repeats the key detection flow to judge whether the key is pressed down, at the moment, the working sequence is shown in fig. 5, as shown in fig. 3 and 5, key detection is carried out at t1, and level detection is carried out at t 2.
Therefore, the utility model provides the time-sharing multiplexing circuit for key detection and external level input detection, which has the main functions of distinguishing external input high level from key detection, is ingenious in design, can realize the integration of key detection and external input high level detection, can save the work of hardware design, can save the space of board layout design, and can also reduce the hardware design cost of the circuit.
The above embodiments are only preferred embodiments of the present utility model, and the scope of the present utility model is not limited thereto, but any insubstantial changes and substitutions made by those skilled in the art on the basis of the present utility model are intended to be within the scope of the present utility model as claimed.
Claims (10)
1. A time division multiplexing circuit for key detection and level detection, comprising:
the micro-control circuit is provided with a multiplexing end, a field effect transistor, a second voltage comparator, a power key detection pin, a key input detection module and an external level input end, wherein the key input detection module is respectively connected with the micro-control circuit and the power key detection pin, the non-inverting input end of the second voltage comparator is used for inputting a reference voltage, the inverting input end of the second voltage comparator is connected to the power key detection pin, the output end of the second voltage comparator is used for outputting a level detection signal to the micro-control circuit, the micro-control circuit is used for outputting a control signal to the grid electrode of the field effect transistor, the drain electrode of the field effect transistor is connected with a battery power supply, and the source electrode of the field effect transistor is connected with the power key detection pin;
the external level input end is connected with the power key detection pin and is used for providing an external level input signal.
2. The time division multiplexing circuit for key detection and level detection according to claim 1, wherein:
the key input detection module comprises a key switch and a first voltage comparator, wherein the key switch is connected with the power key detection pin and is used for providing key signals, the in-phase input end of the first voltage comparator is used for inputting a battery power supply with a preset numerical range, the inverting input end of the first voltage comparator is connected to the power key detection pin, and the output end of the first voltage comparator is used for outputting key detection signals to the micro control circuit.
3. The time division multiplexing circuit for key detection and level detection according to claim 1, wherein:
the micro-control circuit is also used for outputting a driving control signal to the driving circuit, and the driving circuit controls the grid electrode of the field effect transistor.
4. The time division multiplexing circuit for key detection and level detection according to claim 2, wherein:
the circuit also comprises a voltage dividing circuit composed of a first resistor and a second resistor, wherein the first end of the first resistor is connected to the inverting input end of the first voltage comparator and the second end of the second resistor, the second end of the first resistor is connected with the key input detection module, and the first end of the second resistor is connected with the source electrode of the field effect transistor.
5. The time division multiplexing circuit for key detection and level detection according to claim 4, wherein:
the circuit further includes a third resistor connected between the inverting input of the second voltage comparator and the external level input.
6. The time division multiplexing circuit for key detection and level detection according to claim 5, wherein:
the field effect tube is used for communicating the key input detection module with the power supply channel of the first voltage comparator, when the key input detection module is detected to output a key signal, the voltage of the input power supply VIN is smaller than 1/3 battery power after the input power supply VIN is divided by the first resistor and the second resistor, and the output end of the first voltage comparator outputs a high level;
when the key input detection module is detected to not output a key signal, the voltage of the input power supply VIN is larger than 1/3 battery power supply, and the output end of the first voltage comparator outputs a low level.
7. The time division multiplexing circuit for key detection and level detection according to claim 5, wherein:
when the external level input end is detected to input a high level, the voltage of the input power source VIN is higher than the Vref voltage, and the output end of the second voltage comparator outputs a low level.
8. The time division multiplexing circuit for key detection and level detection according to claim 7, wherein:
when the external level input end is detected to be in a high resistance state, the voltage of the input power source VIN is lower than the Vref voltage, and the output end of the second voltage comparator outputs a high level.
9. The time-division multiplexing circuit for key detection and level detection according to any one of claims 1 to 8, wherein:
the field effect transistor is a PMOS transistor.
10. The time-division multiplexing circuit for key detection and level detection according to any one of claims 1 to 8, wherein:
the field effect transistor is an NMOS transistor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223377234.7U CN219018791U (en) | 2022-12-14 | 2022-12-14 | Time-sharing multiplexing circuit for key detection and level detection |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202223377234.7U CN219018791U (en) | 2022-12-14 | 2022-12-14 | Time-sharing multiplexing circuit for key detection and level detection |
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| CN219018791U true CN219018791U (en) | 2023-05-12 |
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