CN217546013U - Power-on reset and power-off detection circuit and electronic equipment - Google Patents

Abstract

The utility model discloses a power-on reset and power-down detection circuit and electronic equipment belongs to electronic circuit technical field. The power-on reset and power-off detection circuit comprises a power-on reset module and a power-off interrupt module; the power-on reset module is respectively electrically connected with a main power supply of the electronic equipment, the first power supply and a reset pin of the MCU module and is used for controlling the MCU module to realize a power-on reset function when the main power supply is powered on; the power-down interrupt module is respectively electrically connected with a main power supply of the electronic equipment, the first power supply and the wake-up pin of the MCU module and is used for controlling the MCU module to realize the power-down interrupt wake-up function when the main power supply is powered down. By the circuit, when the electronic equipment cannot be reset and continuously work when the MCU module is halted on the premise of not adding an external lead, the electronic equipment can continuously work after the electronic equipment is plugged and unplugged; and ensuring that the electronic equipment senses the power failure of the main power supply at the first time, and awakening the electronic equipment in time to continuously complete the corresponding service logic.

Description

Power-on reset and power-off detection circuit and electronic equipment

Technical Field

The utility model relates to an electronic circuit technical field especially relates to a power-on reset and power failure detection circuit and electronic equipment.

Background

With the development of scientific technology, electronic devices (such as vehicle-mounted controllers, vehicle-mounted trackers, and the like) are increasingly widely applied to automobiles, motorcycles, and electric vehicles. In order to meet the requirement of a vehicle-mounted extremely reliable use scene, vehicle-mounted electronic equipment needs to meet the requirement of waterproof and dustproof reliable use, so that most of electronic equipment is subjected to great treatment on sealing performance, such as glue pouring or other sealing modes. Due to the processing, the electronic equipment can still run smoothly in a plurality of severe working scenes, and the most real functional data are shown to the user. The electronic equipment generally supplies power by switching the main power supply and the standby power supply, but the electronic equipment still has small probability of failure, functional disorder or other system abnormity in use and cannot be normally used, at the moment, the standby power supply of the electronic equipment is switched to work after the main power supply of the electronic equipment is powered off, and the equipment is very difficult to disassemble and restart due to excellent structural sealing property, so that a reliable method for resetting the equipment is urgently needed at the moment, and the equipment returns to the initial state to continuously work.

The vehicle-mounted electronic equipment does not always run normally, when a vehicle is flamed out, in order to meet the power consumption requirement of the whole vehicle, the electronic equipment needs to enter a low power consumption mode of the electronic equipment, and at the moment, if the power supply of the whole vehicle is abnormally disconnected, namely the main power supply of the electronic equipment is disconnected, the electronic equipment needs to be awakened in time, so that the electronic equipment can complete the service logic after the power failure of the whole vehicle under the working of a standby power supply.

SUMMERY OF THE UTILITY MODEL

In view of this, an object of the embodiments of the present invention is to provide a power-on reset and power-down detection circuit and an electronic device, so as to solve the technical problem that the electronic device cannot be reset after a fault of the existing electronic device and cannot be waken up in time after the power-down of the main power source to complete the logic service thereof.

The utility model provides an above-mentioned technical problem adopted technical scheme as follows:

according to an aspect of the embodiments of the present invention, there is provided a power-on reset and power-down detection circuit, which includes a power-on reset module and a power-down interrupt module;

the power-on reset module is respectively electrically connected with a main power supply of the electronic equipment, a first power supply and a reset pin of the MCU module and is used for controlling the MCU module to realize a power-on reset function when the main power supply is powered on;

the power failure interrupt module is respectively electrically connected with a main power supply of the electronic equipment, the first power supply and the wake-up pin of the MCU module and is used for controlling the MCU module to realize the power failure interrupt wake-up function when the main power supply is powered down.

Optionally, the power-on reset and power-off detection circuit further includes a control signal generation module, and the power-on reset module and the power-off interruption module are electrically connected to the main power supply through the control signal generation module, respectively.

Optionally, the control signal generation module includes a first switch, a second switch, and first to fourth resistors;

the first switch comprises a first N-channel MOS tube, the second switch comprises a second N-channel MOS tube, one end of a first resistor is electrically connected with a main power supply, the other end of the first resistor is electrically connected with one end of a second resistor and a grid electrode of the first N-channel MOS tube, the other end of the second resistor and a source electrode of the first N-channel MOS tube are grounded, a drain electrode of the first N-channel MOS tube is electrically connected with a power failure interrupt module, one end of a third resistor and the grid electrode of the second N-channel MOS tube, the other end of the third resistor is electrically connected with a first power supply, a drain electrode of the second N-channel MOS tube is electrically connected with one end of a power-on reset module and one end of a fourth resistor, the source electrode of the second N-channel MOS tube is grounded, the other end of the fourth resistor is electrically connected with the first power supply, and the first power supply is the standby power supply or is obtained by the standby power supply through voltage conversion.

Optionally, the power-on reset module includes a first flip-flop and a first delay circuit;

the clock pin of the first trigger is electrically connected with the drain electrode of the second N-channel MOS tube, the preset bit pin and the data input pin are respectively electrically connected with the first power supply, the data output pin is electrically connected with the reset pin of the MCU module, and the reset pin is electrically connected with the first delay circuit.

Optionally, the first trigger is a first D trigger triggered by a rising edge, and a-Q pin of the first D trigger is electrically connected to a reset pin of the MCU module.

Optionally, the first delay circuit comprises a fifth resistor and a first capacitor;

one end of the fifth resistor is electrically connected with a-Q pin of the first D trigger and the reset pin of the MCU module respectively, the other end of the fifth resistor is electrically connected with the reset pin of the first D trigger and one end of the first capacitor respectively, and the other end of the first capacitor is grounded.

Optionally, the power down interrupt module includes a second trigger and a second delay circuit;

the clock pin of the second trigger is electrically connected with the drain electrode of the first N-channel MOS tube, the preset bit pin and the data input pin are respectively electrically connected with the first power supply, the data output pin is electrically connected with the awakening pin of the MCU module, and the reset pin is electrically connected with the second delay circuit.

Optionally, the second trigger is a second D trigger triggered by a rising edge, and a Q pin of the second D trigger is electrically connected to a wakeup pin of the MCU module.

Optionally, the second delay circuit comprises a sixth resistor and a second capacitor;

one end of the sixth resistor is electrically connected with a-Q pin of the second D trigger, the other end of the sixth resistor is electrically connected with a reset pin of the second D trigger and one end of the second capacitor respectively, and the other end of the second capacitor is grounded.

According to the utility model discloses another aspect of the embodiment provides an electronic equipment, and this electronic equipment includes that the aforesaid is gone up to reset and falls the electric detection circuitry.

The embodiment of the utility model provides an among power-on reset and power failure detection circuit and the electronic equipment, including power-on reset module and power failure interrupt module; the power-on reset module is respectively electrically connected with a main power supply of the electronic equipment, the first power supply and a reset pin of the MCU module and is used for controlling the MCU module to realize a power-on reset function when the main power supply is powered on; the power failure interrupt module is respectively electrically connected with a main power supply of the electronic equipment, the first power supply and the wake-up pin of the MCU module and is used for controlling the MCU module to realize the power failure interrupt wake-up function when the main power supply is powered down. Through the power-on reset and power-off detection circuit provided by the embodiment of the utility model, when the electronic equipment can not be reset and continuously work when the MCU module is halted on the premise of not adding an external lead, the electronic equipment can be continuously worked after the electronic equipment is plugged and unplugged through the circuit; and on the premise of not increasing the timing awakening power consumption, the electronic equipment is ensured to sense the power failure of the main power supply at the first time, and the electronic equipment is awakened in time so as to continuously complete the corresponding service logic.

Drawings

The invention will be further explained with reference to the drawings and examples, wherein:

fig. 1 is a schematic diagram of an embodiment of a power-on reset and power-down detection circuit provided by the present invention;

fig. 2 is a schematic diagram of another embodiment of the power-on reset and power-off detection circuit provided by the present invention;

FIG. 3 is a schematic diagram of a circuit connection of one embodiment of a control signal generation module provided by the present invention;

fig. 4 is a schematic circuit connection diagram of an embodiment of a power-on reset module provided by the present invention;

fig. 5 is a schematic circuit diagram of an embodiment of a power down interrupt module according to the present invention.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

In the following description, suffixes such as "module", "part", or "unit" used to denote elements are used only for the convenience of description of the present invention, and have no specific meaning in itself. Thus, "module", "component" or "unit" may be used mixedly.

Example one

In order to solve the technical problem that the current electronic device cannot be reset after a fault occurs and the main power supply fails to wake up the electronic device in time after power down to complete the logic service of the electronic device, the embodiment provides a power-on reset and power down detection circuit 10, please refer to fig. 1, fig. 1 is a schematic diagram of an embodiment of the power-on reset and power down detection circuit. The power-on reset and power-off detection circuit 10 comprises a power-on reset module 11 and a power-on reset module 12; the power-on reset module 11 is electrically connected to a main power supply of the electronic device, a first power supply VCC and a reset pin MCU _ RST of the MCU module, and is configured to control the MCU module to implement a power-on reset function when the main power supply is powered on; the power-on reset module 12 is electrically connected to a main power supply of the electronic device, the first power supply VCC, and a wake-up pin MCU _ PWR _ INT of the MCU module, and is configured to control the MCU module to implement a power-off interrupt wake-up function when the main power supply is powered off.

In this embodiment, it should be noted that the power-on reset and power-down detection circuit 10 of this embodiment is applicable to an electronic device powered by a main power supply and a standby power supply in a switching manner, and is particularly applicable to an electronic device which has good sealing performance and is difficult to disassemble and reset when a fault occurs.

Specifically, the power-on reset and power-off detection circuit 10 controls the MCU module to implement a power-on reset function through the power-on reset module 11 when the main power supply is powered on, and controls the MCU module to implement a power-off interrupt wake-up function through the power-on reset module 12 when the main power supply is powered off. Therefore, when the electronic equipment cannot be reset and continuously works after the MCU module is halted on the premise of not adding an external lead, the electronic equipment can continuously work after the electronic equipment is plugged and unplugged through the circuit; and on the premise of not increasing the timing awakening power consumption, the electronic equipment is ensured to sense the power failure of the main power supply at the first time, and is awakened in time so as to continuously complete the corresponding service logic.

In an embodiment, please refer to fig. 2, fig. 2 is a schematic diagram of another embodiment of the power-on reset and power-off detection circuit according to the present invention. The power-on reset and power-off detection circuit 10 further includes a control signal generation module 13, and the power-on reset module 11 and the power-on reset module 12 are electrically connected to the main power supply through the control signal generation module 13, respectively.

In this embodiment, the control signal generating module 13 is electrically connected to a main power supply, and when the main power supply is powered on, generates a power reset signal PWR _ RST, and controls the power-on reset module 11 to generate a power-on reset signal MCU _ RST of the MCU module, so that the MCU module is controlled by a reset pin MCU _ RST of the MCU module to implement a power-on reset function; when the main power supply is powered off, a power supply interruption control signal PWR _ INT is generated, the power-on reset module 12 is controlled to generate an MCU module power supply interruption signal MCU _ PWR _ INT, and therefore the MCU module is controlled to realize the power-off interruption awakening function through an awakening pin MCU _ PWR _ INT of the MCU module. Therefore, when the electronic equipment is solved that the MCU module is halted and the electronic equipment cannot be reset and continuously works on the premise of not adding an external lead, the electronic equipment is continuously operated after the electronic equipment is plugged and unplugged through the circuit; and on the premise of not increasing the timing awakening power consumption, the electronic equipment is ensured to sense the power failure of the main power supply at the first time, and is awakened in time so as to continuously complete the corresponding service logic.

In one embodiment, please refer to fig. 3, fig. 3 is a circuit connection diagram of an embodiment of the control signal generating module according to the present invention. The control signal generating module 13 includes a first switch, a second switch, and first to fourth resistors R3 to R6; the first switch includes first N channel MOS pipe Q1, the second switch includes second N channel MOS pipe Q2, first resistance R3's one end is connected with the main power electricity, the other end is connected with second resistance R4's one end and first N channel MOS pipe Q1's grid electricity respectively, second resistance R4's the other end and first N channel MOS pipe Q1's source ground connection, first N channel MOS pipe Q1's drain electrode respectively with power-on reset module 12, third resistance R5's one end and second N channel MOS pipe Q2's grid electricity are connected, third resistance R5's the other end and first power VCC electricity are connected, second N channel MOS pipe Q2's drain electrode respectively with power-on reset module 11 and fourth resistance R6's one end electricity is connected, source ground connection, fourth resistance R6's the other end with first power VCC electricity is connected, first power VCC be stand-by power source or obtained through voltage transformation.

In this embodiment, the control signal generating module 13 may, but is not limited to, employ a first switch, a second switch, and first to fourth resistors R3 to R6, where the first switch may, but is not limited to, employ a first N-channel MOS transistor Q1, and the second switch may, but is not limited to, employ a second N-channel MOS transistor Q2. When the main power supply is powered on, the first N-channel MOS transistor Q1 is turned on because the gate thereof is at a high level, the drain thereof is pulled down from the high level to a low level, and further, the gate of the second N-channel MOS transistor Q2 electrically connected to the drain thereof is pulled down to a low level, so that the second N-channel MOS transistor Q2 is turned off from on, and thus the drain of the second N-channel MOS transistor Q2 is pulled up from the low level to the high level by the first power supply VCC, and a power supply reset signal PWR _ RST from low to high is generated. When the main power supply is powered off, the first N-channel MOS transistor Q1 is turned off due to the low level of the gate thereof, and the drain thereof is pulled up to the high level from the low level by the first power supply VCC, generating a power supply interruption control signal PWR _ INT from low to high.

In one embodiment, the power-on reset module 11 includes a first flip-flop and a first delay circuit; the clock pin of the first trigger is electrically connected with the drain electrode of the second N-channel MOS tube Q2, the preset bit pin and the data input pin are respectively electrically connected with the first power supply VCC, the data output pin is electrically connected with the reset pin of the MCU module, and the reset pin is electrically connected with the first delay circuit.

In this embodiment, the power-on reset module 11 may adopt, but is not limited to, a first flip-flop and a first delay circuit. Please refer to fig. 4, fig. 4 is a schematic diagram of a circuit connection of an implementation manner of the power-on reset module provided by the present invention, wherein, taking as an example that the first D flip-flop is a first D flip-flop U1A triggered by a rising edge, the first delay circuit is an RC delay circuit composed of a fifth resistor R1 and a first capacitor C1, a clock pin CLK of the first D flip-flop is electrically connected to a drain of the second N-channel MOS transistor Q2, i.e., electrically connected to a power reset signal PWR _ RST, a preset pin PR and a data input pin D are respectively electrically connected to the first power VCC, a-Q pin of the first D flip-flop U1A is respectively electrically connected to a reset pin MCU _ RST of the MCU module and one end of the fifth resistor R1, the other end of the fifth resistor R1 is respectively electrically connected to a reset pin CLR of the first D flip-flop U1A and one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded. When the main power supply is powered on, the control signal generation module 13 generates a power supply reset signal PWR _ RST from low to high, so that a rising edge signal is formed on a clock pin CLK of the first D flip-flop U1A, the output state of the first D flip-flop U1A is changed, a-Q pin of the first D flip-flop U1A is changed from high level to low level, and the pin acts on a reset pin MCU-RST of the MCU module, so that a power-on reset function is realized. Then, the first capacitor C1 of the first delay circuit composed of the fifth resistor R1 and the first capacitor C1 discharges, when the voltage on the first capacitor C1 is lower than the threshold voltage of the reset pin CLR of the first D flip-flop U1A, the first D flip-flop U1A clears the set, and the-Q pin thereof changes from the low level to the high level, wherein the duration of the first delay generated by the first delay circuit can be adjusted by adjusting the values of the fifth resistor R1 and the first capacitor C1, so that the power-on reset module 11 capable of adjusting the reset time is completed.

In one embodiment, the power-on reset module 12 includes a second flip-flop U2A and a second delay circuit; a clock pin of the second trigger U2A is electrically connected with a drain electrode of the first N-channel MOS tube Q1, a preset pin and a data input pin are respectively electrically connected with the first power VCC, a data output pin is electrically connected with a wakeup pin of the MCU module, and a reset pin is electrically connected with the second delay circuit.

In this embodiment, the power-on reset module 12 may include, but is not limited to, a second flip-flop U2A and a second delay circuit. Please refer to fig. 5, fig. 5 is a schematic diagram of a circuit connection of an embodiment of the power-on reset module provided by the present invention, wherein, taking as an example that the second flip-flop U2A is a D flip-flop triggered by a rising edge, and the first delay circuit is an RC delay circuit composed of a sixth resistor R2 and a second capacitor C2, a clock pin CLK of the second flip-flop U2A is electrically connected to a drain of the first N-channel MOS transistor Q1, i.e., electrically connected to a power interrupt control signal PWR _ INT, a preset pin PR and a data input pin D are respectively electrically connected to the first power VCC, a Q pin of the second D flip-flop is electrically connected to a wakeup pin MCU _ PWR _ INT and an electrical connection of the MCU module, one end of the sixth resistor R2 is electrically connected to a-Q pin of the second D flip-flop, the other end of the sixth resistor R2 is electrically connected to one end of the reset pin CLR of the second D flip-flop and one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded. When the main power supply is powered off, a power supply interruption control signal PWR _ INT from low to high is generated by the control signal generation module 13, so that a rising edge signal is formed on a clock pin CLK of the second D flip-flop, the output state of the second D flip-flop is changed, a Q pin of the second D flip-flop changes from low level to high level, and the rising edge signal is applied to a wakeup pin MCU _ PWR _ INT of the MCU module to realize a power-off interruption wakeup function, wherein the Q pin of the second D flip-flop changes from high level to low level, then, a second capacitor C2 of a second delay circuit composed of a sixth resistor R2 and a second capacitor C2 discharges, when the voltage on the second capacitor C2 is lower than the threshold voltage of a reset pin CLR of the second D flip-flop, the second D flip-flop clears the setting, the Q pin of the second D flip-flop changes from high level to low level, and the Q pin changes from low level to high level, wherein the duration of a second delay generated by the second delay circuit can be adjusted by adjusting the values of the sixth resistor R2 and the second capacitor C2, so that the power-on reset module 12 with adjustable time is powered on.

The power-on reset and power-down detection circuit 10 in the embodiment comprises a power-on reset module 11 and a power-on reset module 12; the power-on reset module 11 is electrically connected to a main power supply of the electronic device, a first power supply VCC, and a reset pin MCU _ RST of the MCU module, respectively, and is configured to control the MCU module to implement a power-on reset function when the main power supply is powered on; the power-on reset module 12 is electrically connected to a main power supply of the electronic device, the first power supply VCC, and a wake-up pin MCU _ PWR _ INT of the MCU module, and is configured to control the MCU module to implement a power-off interrupt wake-up function when the main power supply is powered off. By the power-on reset and power-off detection circuit 10 provided by the embodiment, when the situation that the MCU module is halted and the electronic equipment cannot be reset and continuously works can be solved on the premise of not adding an external lead, the electronic equipment can continuously work after the electronic equipment is plugged and unplugged through the circuit; and on the premise of not increasing the timing awakening power consumption, the electronic equipment is ensured to sense the power failure of the main power supply at the first time, and the electronic equipment is awakened in time so as to continuously complete the corresponding service logic.

Example two

An embodiment of the utility model provides an electronic equipment, this electronic equipment include the power-on reset and fall electric detection circuitry 10 of above-mentioned embodiment one. The electronic equipment of the embodiment can solve the problem that the MCU module is halted, the electronic equipment cannot be reset and continuously works on the premise of not adding an external lead, and the electronic equipment can continuously work after the electronic equipment is plugged and unplugged through the circuit; and on the premise of not increasing the timing awakening power consumption, the electronic equipment is ensured to sense the power failure of the main power supply at the first time, and the electronic equipment is awakened in time so as to continuously complete the corresponding service logic. The specific structure of the power-on reset and power-off detection circuit 10 is as described in the first embodiment, and is not described herein again.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

The number of the embodiment of the present invention is only for description, and does not represent the advantages or disadvantages of the embodiment.

While the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many modifications may be made by one skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (10)

1. A power-on reset and power-off detection circuit is characterized by comprising a power-on reset module and a power-off interrupt module;

the power-on reset module is respectively electrically connected with a main power supply of the electronic equipment, a first power supply and a reset pin of the MCU module and is used for controlling the MCU module to realize a power-on reset function when the main power supply is powered on;

the power failure interrupt module is respectively electrically connected with a main power supply of the electronic equipment, the first power supply and the wake-up pin of the MCU module and is used for controlling the MCU module to realize the power failure interrupt wake-up function when the main power supply is powered down.

2. The power-on reset and power-down detection circuit of claim 1, further comprising a control signal generation module, wherein the power-on reset module and the power-down interrupt module are electrically connected to the main power source through the control signal generation module, respectively.

3. The power-on-reset and power-down detection circuit according to claim 2, wherein the control signal generation module comprises a first switch, a second switch, and first to fourth resistors;

the first switch comprises a first N-channel MOS tube, the second switch comprises a second N-channel MOS tube, one end of a first resistor is electrically connected with a main power supply, the other end of the first resistor is electrically connected with one end of a second resistor and a grid electrode of the first N-channel MOS tube, the other end of the second resistor and a source electrode of the first N-channel MOS tube are grounded, a drain electrode of the first N-channel MOS tube is electrically connected with the power failure interrupt module, one end of a third resistor and the grid electrode of the second N-channel MOS tube, the other end of the third resistor is electrically connected with the first power supply, a drain electrode of the second N-channel MOS tube is electrically connected with one end of a power-on reset module and one end of a fourth resistor, the source electrode of the second N-channel MOS tube is grounded, the other end of the fourth resistor is electrically connected with the first power supply, and the first power supply is a standby power supply or is obtained by voltage conversion of the standby power supply.

4. The power-on-reset and power-down detection circuit of claim 3, wherein the power-on-reset module comprises a first flip-flop and a first delay circuit;

the clock pin of the first trigger is electrically connected with the drain electrode of the second N-channel MOS tube, the preset bit pin and the data input pin are respectively electrically connected with the first power supply, the data output pin is electrically connected with the reset pin of the MCU module, and the reset pin is electrically connected with the first delay circuit.

5. The power-on reset and power-down detection circuit according to claim 4, wherein the first flip-flop is a first D flip-flop triggered by a rising edge, and a-Q pin of the first D flip-flop is electrically connected with a reset pin of the MCU module.

6. The power-on-reset and power-down detection circuit of claim 5, wherein the first delay circuit comprises a fifth resistor and a first capacitor;

one end of the fifth resistor is electrically connected with a-Q pin of the first D trigger and a reset pin of the MCU module respectively, the other end of the fifth resistor is electrically connected with the reset pin of the first D trigger and one end of the first capacitor respectively, and the other end of the first capacitor is grounded.

7. The power-on-reset and power-down detection circuit of claim 3, wherein the power-down interrupt module comprises a second flip-flop and a second delay circuit;

the clock pin of the second trigger is electrically connected with the drain electrode of the first N-channel MOS tube, the preset bit pin and the data input pin are respectively electrically connected with the first power supply, the data output pin is electrically connected with the awakening pin of the MCU module, and the reset pin is electrically connected with the second delay circuit.

8. The power-on reset and power-off detection circuit according to claim 7, wherein the second flip-flop is a second D flip-flop triggered by a rising edge, and a Q pin of the second D flip-flop is electrically connected to a wake-up pin of the MCU module.

9. The power-on-reset and power-down detection circuit of claim 8, wherein the second delay circuit comprises a sixth resistor and a second capacitor;

one end of the sixth resistor is electrically connected with a-Q pin of the second D trigger, the other end of the sixth resistor is electrically connected with a reset pin of the second D trigger and one end of the second capacitor respectively, and the other end of the second capacitor is grounded.

10. An electronic device, characterized in that it comprises a power-on-reset and power-down detection circuit as claimed in any one of claims 1-9.

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