CN202798617U - B-type LXI (LAN eXtensions for Instrumentation) arbitrary waveform generator - Google Patents

Abstract

The utility model relates to a B-type LXI (LAN eXtensions for Instrumentation) arbitrary waveform generator, which comprises a B-type LXI interface module, an arbitrary waveform generator function module and an LED indicating module. The B-type LXI interface module comprises an embedded processor circuit, an IEEE 1588 trigger management circuit, a FLASH storage circuit, a DDR (double date rate) dynamic storage circuit and an LAN (local area network) interface communication circuit. The arbitrary waveform generator function module comprises a bus interface circuit, an SDRAM (synchronous dynamic random access memory) storage circuit, an FPGA (field programmable gate array) control circuit, a time generation circuit, a DAC (digital to analog converter) conversion circuit, a filter circuit, a direct-current biasing circuit, an attenuator circuit, a high and low gain circuit and a calibration circuit, and one end of the bus interface circuit is connected with the B-type LXI interface module. The B-type LXI arbitrary waveform generator provided by the utility model is based on the LXI bus standards.

Description

Category-B LXI AWG (Arbitrary Waveform Generator)

Technical field

The utility model relates to a kind of category-B LXI bus AWG (Arbitrary Waveform Generator) circuit.

Background technology

Agilent and VXI Technology company have proposed a kind of new instrument bus-LXI (LAN eXtensions for Instrumentation) in 2004.The LXI instrument need not be special core bus cabinet and Zero greeve controller, directly utilize the standard LAN interface of universal PC, reduced to a great extent the development and application cost.And LAN to be industry the most stable and life cycle is the longest and in the opened industrial standard of development, each manufacturer is easy to existing instrument product is transplanted on the LAN platform, and these all provide convenience for setting up wider distributed automatic measuring and controlling system.The LXI bus standard has defined the chronometer time synchronizing function based on IEEE1588 simultaneously, has introduced for the first time the concept that time-based triggers in the thermometrically field, is easy to make up real-time testing system.

Along with the development of thermometrically technology, require also more and more higher to testing required driving source in the signal testing.Require signal source can produce the sophisticated signal waveform on the one hand, require on the other hand the bandwidth of signal to want enough large.In this case, existing signal source does not mostly satisfy this demand.Particularly in distributed measurement and control system, require tester to have the programming remote control function, existing bus such as GPIB, PCI/PXI etc. can't well meet the demands, the solution of the AWG (Arbitrary Waveform Generator) system of LXI bus standard involve that random waveform produces, signal bandwidth is high, be easy to set up the problem such as distributed measurement and control system.The IEEE 1588 chronometer time synchronous protocols that the category-B instrument of this LXI bus has have been realized the Remote triggering synchronizing function of instrument in nanosecond, can play a significant role in ATS (Automatic Test System).

The utility model content

Based on the LXI bus standard, the utility model provides a kind of category-B LXI AWG (Arbitrary Waveform Generator).

Technical solution of the present utility model:

Category-B LXI AWG (Arbitrary Waveform Generator), its special character is:

Comprise category-B LXI interface module, AWG (Arbitrary Waveform Generator) functional module and LED indicating module;

Described category-B LXI interface module comprises that flush bonding processor circuit, IEEE 1588 trigger management circuit, FLASH memory circuit, DDR dynamic memory circuit and LAN interface telecommunication circuit;

The flush bonding processor circuit is be used to providing and the network interface of controlling computer communication, realizing procedure stores and process relevant LXI bus protocol;

IEEE 1588 triggers management circuit for the treatment of 1588 agreements, manages 1588 associated trigger and extraction time stamp;

The FLASH memory circuit is used for memory system data and application program;

The DDR dynamic memory circuit is used for the dynamic datastore data, for the reading of application program, carry out buffering is provided;

The LAN interface telecommunication circuit provides and the hardware path of controlling computer communication;

The AWG (Arbitrary Waveform Generator) functional module comprises bus interface circuit, SDRAM memory circuitry, FPGA control circuit, clock generation circuit, DAC change-over circuit, filter circuit, dc bias circuit, attenuator circuit, height gain circuitry and calibration circuit,

One end of described bus interface circuit and category-B LXI interface module interconnect, the other end of described bus interface circuit and DAC change-over circuit interconnect, described DAC change-over circuit is exported to filter circuit, described filter circuit is exported to the height gain circuitry, described height gain circuitry is exported to attenuator circuit, described attenuator circuit is exported to dc bias circuit, and the bigoted circuit of described direct current is exported to the DAC change-over circuit

Described FPGA control circuit and DAC change-over circuit, filter circuit, SDRAM memory circuitry and calibration circuit interconnect, and described calibration circuit and attenuator circuit interconnect.

Above-mentioned flush bonding processor circuit comprises PowerPC processor (U1), described PowerPC processor (U1) comprises internal bus interface (U1A), DDR sdram controller interface (U1B), local bus interface (U1C), network MAC interface (U1G), master clock and IO mouth (U1D), described internal bus interface (U1A) and pci interface (2) communication connection, described DDR sdram controller interface (U1B) provides address, data and control link for the DDR dynamic memory circuit; Described local bus interface (U1C) provides interface for the FLASH memory circuit, described network MAC interface (U1G) provides two-way adaptive network path, and the first via links to each other with the LAN interface telecommunication circuit, the second tunnel be used for triggering PPS clock and the I/O port that management circuits provide IEEE 1588 agreements to IEEE 1588; Master clock is used to the clock input of PowerPC processor in described master clock and the IO mouth (U1D), and the IO mouth is used for triggering management circuit to IEEE 1588 to be provided triggering passage and provide control port to the LED indicating module.

Above-mentioned category-B LXI interface module also comprises for the GPIB/USB interface circuit of realizing GPIB/USB hardware path, local bus interface (U1C) is also for the gpib interface circuit provides interface, and described GPIB/USB interface circuit is connected with local bus interface (U1C).

Above-mentioned IEEE 1588 triggers management circuits and comprises programmable logic device FPGA (U20), the LLD[0:7 of described programmable logic device FPGA (U20)] data wire is connected with the local bus circuit of PowerPC processor (U1); The F1588_IO of described programmable logic device FPGA (U20) is connected with the IEEE1588I/O port of PowerPC processor (U1); Programmable logic device FPGA (U20) output is connected with the PPS pulse per second (PPS) F1588_CLKOUT pin of LAN interface circuit.

Above-mentioned FLASH memory circuit comprises the NOR FLASH chip (U6) be used to the 32MB that finishes the storage of program and data, the first address latch chip (U4), the second address latch chip (U5) and the gate circuit (U7) that is used for data buffering, described the first address latch chip (U4), the second address latch chip (U5), gate circuit (U7) is connected successively, form buffer circuit, the NOR FLASH chip (U6) of described 32MB is connected with local bus interface (U1C) circuit of PowerPC processor by buffer circuit;

Described DDR dynamic memory circuit comprises a DDR SDRAM storage chip (U2) the 2nd DDR SDRAM storage chip (U3) of two parallel connections, and a described DDR SDRAM storage chip (U2) all is connected with DDR sdram controller interface (U1B) with the 2nd DDR SDRAM storage chip (U3);

Described LAN interface telecommunication circuit comprises network PHY chip (U12), inverter (U13), voltage controlled oscillator (Y2) and ∏ type low pass filter, signal (CP_OUT) after the PWM pulse-width modulation of the input reception programmable logic device FPGA (U20) of described amplifier (U13), the reverse signal of signal (CP_OUT) is to the input of ∏ type low pass filter after the output output PWM pulse-width modulation of described amplifier (U13), the output of described ∏ type low pass filter is connected with voltage controlled oscillator (Y2) control end, and the output of described voltage controlled oscillator (Y2) is connected with network PHY chip (U12).

The LED indicating module comprises drive circuit (U50), the first common cathode Tricolor LED (D1), the second common cathode Tricolor LED (D2) and the 3rd common cathode Tricolor LED (D3), described the first common cathode Tricolor LED (D1) is connected with drive circuit (U1), and described the second common cathode Tricolor LED (D2) and the 3rd common cathode Tricolor LED (D3) and the master clock of PowerPC processor are connected U1D with the IO mouth) the IO mouth be connected.

Above-mentioned LAN interface telecommunication circuit comprises network PHY chip (U12), inverter (U13), voltage controlled oscillator (Y2) and ∏ type low pass filter, the input of described amplifier U13 receives after the PWM pulse-width modulation of programmable logic device FPGA (U20) behind the signal (CP_OUT), reverse signal by inverter (U13) output CP_OUT, the reverse signal of the input termination CP_OUT of ∏ type low pass filter, the output of ∏ type low pass filter is sent into voltage controlled oscillator (Y2) control end, and the output of described voltage controlled oscillator (Y2) is connected with network PHY chip (U12);

Above-mentioned GPIB/USB interface circuit comprises gpib interface chip (U10), USB interface chip (U29), gpib interface chip (U10) links to each other with local bus interface (U1C), and USB interface chip (U29) links to each other with the local bus interface (U1C) of PowerPC processor.

Also comprise in above-mentioned DDR sdram controller interface (U1B) and the DDR dynamic memory circuit connection line build-out resistor (RN16～RN26),

Also be provided with clock distribution chip (U43) on the clock input link of described master clock and IO mouth (U1D) and PowerPC processor,

Described DDR dynamic memory circuit comprises that also terminating resistor and voltage drive chip (U44), the input of a described DDRSDRAM storage chip (U2) is connected to terminating resistor (R176-R180), and the input of described the 2nd DDR SDRAM storage chip (U3) is connected to terminating resistor (R171-R184).

The FPGA control circuit comprises bus interface, command register, status register, configuration register, sequential register, Wave data buffer cell, SDRAM control interface, logical circuit of clock, main control logic and analog channel interface,

Described command register, status register and configuration register all interconnect with bus interface and main control logic,

Described sequential register and Wave data buffer cell all interconnect with main control logic and SDRAM control interface,

Described logical circuit of clock and analog channel interface all interconnect with main control logic.

The advantage that the utility model has:

1, the utility model is by the LXI bus interface, host computer (computer) downloads to category-B LXI interface module with sample (SAMPLE) data and the control command thereof of random waveform by LAN interface, after the interface module circuit is finished protocol analysis, data and control command thereof are stored by the MEMORY that local bus downloads to the AWG (Arbitrary Waveform Generator) functional module, produce engine by this Lamb wave shape, data reading to D/A converting circuit, is exported waveform through analog output channels such as filtering, gain, decay.

2, also comprise build-out resistor RN16～RN26 in the utility model DDR sdram controller interface U1B and the DDR dynamic memory circuit connection line, the signal reflex that causes because of impedance matching when eliminating high-speed transfer.

3, also be provided with clock distribution chip U43 on the clock input link of the utility model master clock and IO mouth U1D and PowerPC processor, strengthen clock driving force and clock stability.

4, the utility model DDR dynamic memory circuit comprises that also terminating resistor and voltage drive chip U44, the input of the one DDR SDRAM storage chip U2 is connected to terminating resistor R176-R180, the input of the 2nd DDR SDRAM storage chip U3 is connected to terminating resistor R171-R184, improve the reliability of DDR storage, designed terminating resistor RN[27:34], provide termination voltage VTT and DDR to drive reference voltage MPC_MVREF by U44.

Description of drawings

Fig. 1 is the schematic diagram of the utility model category-B LXI AWG (Arbitrary Waveform Generator);

Fig. 2 is the utility model flush bonding processor circuit theory diagrams;

Wherein Fig. 2 a is U1A, and Fig. 2 b is U1B, and Fig. 2 c is U1C, and Fig. 2 d is U1D, and Fig. 2 e is U1F, and Fig. 2 f is U1G;

Fig. 3 is that the utility model IEEE 1588 triggers the management circuit theory diagrams;

Fig. 4 is the utility model FLASH memory circuit schematic diagram;

Fig. 5 is the utility model DDR dynamic memory circuit schematic diagram;

Fig. 6 is the utility model LAN interface telecommunication circuit schematic diagram;

Fig. 7 is the utility model internal bus interface circuit theory diagrams;

Fig. 8 is the utility model GPIB/USB interface circuit schematic diagram;

Fig. 9 is the utility model LED indicating module schematic diagram;

Figure 10 is the utility model FPGA control circuit schematic diagram;

Figure 11 is the utility model DAC change-over circuit schematic diagram;

Figure 12 is the utility model filter circuit schematic diagram;

Figure 13 is the utility model dc bias circuit schematic diagram;

Figure 14 is the utility model attenuator circuit schematic diagram;

Figure 15 is the utility model height gain circuitry schematic diagram;

Figure 16 is the utility model calibration circuit schematic diagram.

Embodiment

As shown in Figure 1, use the PowerPC processor in the flush bonding processor circuit, dominant frequency is up to 667MHz.In this circuit, the internal bus interface U1A of use 32bit, running frequency 66MHz communicates with the AWG (Arbitrary Waveform Generator) functional module and is connected, and sends packet and instruction bag; DDR sdram controller interface U1B provide address, data and control link for the DDR dynamic memory circuit, increases build-out resistor RN16～RN26, the signal reflex that causes because of impedance matching when eliminating high-speed transfer in each connection line; The mode that local bus U1C employing 32bit address wire and data wire are multiplexing is for the peripheral hardwares such as FLASH, GPIB provide interface; Network MAC interface U1G provides two-way 1000M/100M/10M adaptive network path, the first via directly links to each other with the PHY of LAN interface telecommunication circuit, the second road path provides IEEE 1588 agreements PPS clock and I/O port, CFG_RS[0:3 simultaneously] PowerPC actuation schemes word, the start-up mode of decision systems be set; External series Communications Control Interface U1F provides USB interface, RS232 interface, IIC interface and SPI interface; Among master clock and the IO mouth U1D, use the active crystal oscillator of outside 66MHz as the PowerPC main processor clock, by a clock distribution chip U43, strengthen clock driving force and clock stability, be used as LXI_TRIG[0:7 with the IO mouth] 8 triggering passage and the control port of LED indicating module.

As shown in Figure 2, IEEE 1588 triggers management circuit and adopts programmable logic device FPGA to realize, 8 position datawire LLD[0:7] be connected with the LocalBus of PowerPC, set up the communication between PowerPC processor and the FPGA, also can use the SPI mouth simply to control; LXI_TRIG[0:7] after receiving LXI and setting out, trigger the relevant treatment such as route, simultaneously triggering is sent among the PowerPC, finish trigger action, sending triggering signal also is to trigger lines by these 8 to finish; F1588_IO receives and dispatches 1588 events and processes in FPGA; The 1588PPS pulse per second (PPS) that F_1588_PPS output is processed by FPGA, CP_OUT carries out output signal after the PWM pulse-width modulation through FPGA, be used for adjusting the Internet Transmission clock, F1588_CLKOUT receives the PPS pulse per second (PPS) by network PHY output, and LAN_X1 receives the network PHY crystal oscillator clock.When needs were adjusted network clocking, LAN_X1 fed back to the current network clock among the FPGA, and FPGA is by certain PWM algorithm, and output CP_OUT adjusts present clock.

As shown in Figure 3, the FLASH memory circuit adopts the NOR FLASH of 32MB to finish program and data storage, and U6 is connected with the LocalBus of PowerPC, uses the address latch chip U4/U5 of 2 16bit, the gate circuit U7 of 1 16bit carries out data buffering, puies forward the signal high stability.

As shown in Figure 4, the DDR dynamic memory circuit is realized the high-speed cache of data, use the 16bitDDR SDRAM storage chip U2/U3 of 2 64MB directly to link to each other with PowerPC DDR controller, in order to improve the reliability of DDR storage, designed terminating resistor RN[27:34], provide termination voltage VTT and DDR to drive reference voltage MPC_MVREF by U44.

As shown in Figure 5, U12 is the network PHY chip, provides network communication interface between host computer and category-B LXI AWG (Arbitrary Waveform Generator), simultaneously hardware extraction IEEE 1588 timestamps.U13 carries out after receiving the CP_OUT signal oppositely, the ∏ type low pass filter by being formed by C68, C62, C67, R58 then, and general all the time PWM modulation signal CP_OUT sends into voltage controlled oscillator Y2 control end, carries out the adjustment of local network clock.U[15:19] and toggle switch SW1 provide the actuation schemes word for system.

As shown in Figure 6, P2 and P3 are internal bus interface, and interface and the AWG (Arbitrary Waveform Generator) functional module communication interface of 32bti, 66MHz is provided.

As shown in Figure 7, except LAN interface, this category-B LXI AWG (Arbitrary Waveform Generator) can also use GPIB to communicate by letter with host computer with USB interface.U10 is special-purpose gpib interface chip, for so that the GPIB voltage matches of the PowerPC port voltage of 3.3V and 5V uses U9 with the 16bit buffer gate circuit of voltage transitions.USB interface uses the U29 special chip directly to link to each other with PowerPC, realizes USB2.0 communication protocol.RS232 is debug port, uses the U31 special chip, prints startup and Debugging message by RS232 in debug process.

As shown in Figure 8, LED indicating module circuit is according to LXI v1.3 standard design, and D1 is common cathode 3 look light-emitting diodes, cooperates the U1 drive circuit, and standby and power indication is provided; D2 and D3 carry out respectively the indication of network connection state and IEEE 1588 states directly by the IO port controlling of PowerPC.

As shown in Figure 9, the bus interface circuit of AWG (Arbitrary Waveform Generator) functional module adopts the parallel bus interface of 32bit, 66MHz directly to link to each other with the P3 internal bus interface with the P2 of category-B LXI interface module, for category-B LXI interface module and AWG (Arbitrary Waveform Generator) functional module provide data and instruction path.After this bus interface circuit receives data and instruction, information is sent in the FPGA control circuit of Figure 11, be designed with the state of a control machine of a special use among the FPGA, realization is with the two-way communication of bus interface circuit, and the data of the SDRAM by a two-port RAM buffering bus interface circuit and Figure 10.Adopt 4 SDRAM chip U[13:14], U[16:17] realize that the plate of 256MB carries memory space.Sdram controller and waveform generation engine and triggering control section are realized by FPGA.Sdram controller is finished two aspect work, when downloading data, bus interface circuit is become to meet the data flow of SDRAM memory sequential through the data transformation of sequential conversion; When waveform generation, the data in the SDRAM memory are sent in the waveform generation engine on the other hand.

As shown in figure 10, the FPGA control circuit has been realized the dual port RAM function, for SDRAM and bus interface circuit provide outside the control interface, has most importantly realized waveform generation engine function.Waveform generation engine modules mainly is the control register according to controller inside, shape information, and the host computer configuration informations such as Wave data are carried out computing, obtain the required waveform length of current waveform, waveform first address, wave band length, cycle-index; After triggering signal arrives, fetch data from SDRAM according to output mode and send to analog circuit, finally be convertible into the data flow that DAC changes that is used for of continuous 16 bit widths of maximum 100MSPS.

As shown in figure 11, analog channel comes from the main DAC of system, and the DAC chip U38 that selects in this patent has the D/A switching rate that is up to 400M, inner PLL frequency multiplier and optional Clock dividers., MDA_D[15..0] data flow that provides for FPGA, after U38 converts analog signal to, by holding wire MDA_VOUT to low-pass filter circuit.The analog signal of U38 output is the magnitude of current, turns the voltage amplifier through the U39 electric current and changes.Amplifier U39 input power is got ± 5V, and the highest Slew Rate reaches 1200V/us ,-three dB bandwidth 225MHz, and the highest sample frequency 400M of U38, and Slew Rate is equivalent to 2V/T=800V/us under worst case, meets design requirement.

As shown in figure 12, could recover correct waveform in view of the DAC data reconstruction needs filtering high frequency picture frequency to disturb, it is very precipitous therefore to require filtering characteristic to need, and adopts by C[207:213] and L[23:25] 7 rank Low-pass Elliptic Filters realizations.

As shown in figure 13, biasing circuit is realized by the U43 of 12 Bits Serial DAC, because the maximum 1.25mA of DAC output current, therefore need to add the one-level follower, drive VREF, follower is elected U13 as, the state of U43 behind the electrification reset is 00H, namely is biased to 0, RESETSEL pin and connects " 0 ".

As shown in figure 14, attenuator circuit directly uses ∏ type resistor network attenuator circuit to realize.Attenuator circuit is in order to realize the output than great dynamic range, and the decay maximum can reach 51DB, is divided into pre-decay and POST decay, uses preposition decay can reduce the distortion of signal.Decay does not change signal to noise ratio, but the signal noise after the gain mainly is comprised of noise and amplifier noise after the previous stage decay, if the noise after the decay through behind the gain amplifier still less than amplifier noise, just can improve the signal to noise ratio after the gain.Pre-decay (PRE-AMP) scope is 0～12DB, step-length 3DB, and main attenuation range is 0～36DB, step-length 12DB, the 3DB adjustable extent of cooperation DAC built-in chip type, user-programmable 0.01DB step-length can realize that the decay of 0.01DB precision is big or small.

As shown in figure 15, in the high gain circuit, the amplifier supply power voltage is ± 15V, and the output voltage Slew Rate is-13.6V～13.6V, if when output resistance is 50 Ω in the situation of output short-circuit, output current will reach 250mA, has surpassed the limit of chip.In order to increase output current, adopted 3 amplifier U[45:47] output in parallel, output current is improved 3 times, the caloric value of single amplifier also reduces greatly, has avoided that chip burns when output short-circuit.Add isolation resistance at input; The output connecting resistance is isolated output on the one hand, the required output impedance of the system that realizes on the other hand.

Broadband, ultra-low-distortion amplifier U[48:49 are selected in the low-gain channel].Method for designing and high gain circuit are similar.

As shown in figure 16, calibration circuit adopts 24 AD chip U51, cooperates amplifier U50 to realize calibration, selects calibration mode or normal mode of operation by relay LS9.Adopt the method for sectional calibration, from [0,3.5], (3.5,6.5], (6.5,9.5], (9.5,12.5] ... (and 54.5,57.5] totally 19 sections.To every section signalling channel that use is fixing, change current gain to regulate actual gain.For example (0,3.5] section, change current gain and make output signal approach respectively 0DB and 3.5DB, record issues gain values, obtains according to this gain calibration constant of this section.

Claims (10)

1.B class LXI AWG (Arbitrary Waveform Generator) is characterized in that:

Comprise category-B LXI interface module, AWG (Arbitrary Waveform Generator) functional module and LED indicating module;

Described category-B LXI interface module comprises that flush bonding processor circuit, IEEE 1588 trigger management circuit, FLASH memory circuit, DDR dynamic memory circuit and LAN interface telecommunication circuit;

The flush bonding processor circuit is be used to providing and the network interface of controlling computer communication, realizing procedure stores and process relevant LXI bus protocol;

IEEE 1588 triggers management circuit for the treatment of 1588 agreements, manages 1588 associated trigger and extraction time stamp;

The FLASH memory circuit is used for memory system data and application program;

The DDR dynamic memory circuit is used for the dynamic datastore data, for the reading of application program, carry out buffering is provided;

The LAN interface telecommunication circuit provides and the hardware path of controlling computer communication;

The AWG (Arbitrary Waveform Generator) functional module comprises bus interface circuit, SDRAM memory circuitry, FPGA control circuit, clock generation circuit, DAC change-over circuit, filter circuit, dc bias circuit, attenuator circuit, height gain circuitry and calibration circuit,

One end of described bus interface circuit and category-B LXI interface module interconnect, the other end of described bus interface circuit and DAC change-over circuit interconnect, described DAC change-over circuit is exported to filter circuit, described filter circuit is exported to the height gain circuitry, described height gain circuitry is exported to attenuator circuit, described attenuator circuit is exported to dc bias circuit, and the bigoted circuit of described direct current is exported to the DAC change-over circuit

Described FPGA control circuit and DAC change-over circuit, filter circuit, SDRAM memory circuitry and calibration circuit interconnect, and described calibration circuit and attenuator circuit interconnect.

2. category-B LXI AWG (Arbitrary Waveform Generator) according to claim 1 is characterized in that:

Described flush bonding processor circuit comprises PowerPC processor (U1), described PowerPC processor (U1) comprises internal bus interface (U1A), DDR sdram controller interface (U1B), local bus interface (U1C), network MAC interface (U1G), master clock and IO mouth (U1D), described internal bus interface (U1A) and pci interface (2) communication connection, described DDR sdram controller interface (U1B) provides address, data and control link for the DDR dynamic memory circuit; Described local bus interface (U1C) provides interface for the FLASH memory circuit, described network MAC interface (U1G) provides two-way adaptive network path, and the first via links to each other with the LAN interface telecommunication circuit, the second tunnel be used for triggering PPS clock and the I/O port that management circuits provide IEEE 1588 agreements to IEEE 1588; Master clock is used to the clock input of PowerPC processor in described master clock and the IO mouth (U1D), and the IO mouth is used for triggering management circuit to IEEE 1588 to be provided triggering passage and provide control port to the LED indicating module.

3. category-B LXI AWG (Arbitrary Waveform Generator) according to claim 1 and 2 is characterized in that:

Described category-B LXI interface module comprises that also local bus interface (U1C) is also for the gpib interface circuit provides interface for the GPIB/USB interface circuit of realizing GPIB/USB hardware path, and described GPIB/USB interface circuit is connected with local bus interface (U1C).

4. category-B LXI AWG (Arbitrary Waveform Generator) according to claim 3 is characterized in that:

Described IEEE 1588 triggers management circuits and comprises programmable logic device FPGA(U20), described programmable logic device FPGA(U20) LLD[0:7] data wire is connected with the local bus circuit of PowerPC processor (U1); Described programmable logic device FPGA(U20) F1588_IO is connected with the IEEE1588 I/O port of PowerPC processor (U1); Programmable logic device FPGA(U20) output is connected with the PPS pulse per second (PPS) F1588_CLKOUT pin of LAN interface circuit.

5. category-B LXI AWG (Arbitrary Waveform Generator) according to claim 4 is characterized in that:

Described FLASH memory circuit comprises be used to the NOR FLASH chip (U6), the first address latch chip (U4), the second address latch chip (U5) of the 32MB that finishes the storage of program and data and the gate circuit (U7) that is used for data buffering, described the first address latch chip (U4), the second address latch chip (U5), gate circuit (U7) are connected successively, form buffer circuit, the NOR FLASH chip (U6) of described 32MB is connected with local bus interface (U1C) circuit of PowerPC processor by buffer circuit;

Described DDR dynamic memory circuit comprises a DDR SDRAM storage chip (U2) the 2nd DDR SDRAM storage chip (U3) of two parallel connections, and a described DDR SDRAM storage chip (U2) all is connected with DDR sdram controller interface (U1B) with the 2nd DDR SDRAM storage chip (U3);

Described LAN interface telecommunication circuit comprises network PHY chip (U12), inverter (U13), voltage controlled oscillator (Y2) and ∏ type low pass filter, the input reception programmable logic device FPGA(U20 of described amplifier (U13)) signal (CP_OUT) after the PWM pulse-width modulation, the reverse signal of signal (CP_OUT) is to the input of ∏ type low pass filter after the output output PWM pulse-width modulation of described amplifier (U13), the output of described ∏ type low pass filter is connected with voltage controlled oscillator (Y2) control end, and the output of described voltage controlled oscillator (Y2) is connected with network PHY chip (U12).

6. category-B LXI AWG (Arbitrary Waveform Generator) according to claim 5, it is characterized in that: the LED indicating module comprises drive circuit (U50), the first common cathode Tricolor LED (D1), the second common cathode Tricolor LED (D2) and the 3rd common cathode Tricolor LED (D3), described the first common cathode Tricolor LED (D1) is connected with drive circuit (U1), and described the second common cathode Tricolor LED (D2) and the 3rd common cathode Tricolor LED (D3) and the master clock of PowerPC processor are connected U1D with the IO mouth) the IO mouth be connected.

7. category-B LXI AWG (Arbitrary Waveform Generator) according to claim 6, it is characterized in that: described LAN interface telecommunication circuit comprises network PHY chip (U12), inverter (U13), voltage controlled oscillator (Y2) and ∏ type low pass filter, the input of described amplifier U13 receives programmable logic device FPGA(U20) the PWM pulse-width modulation after behind the signal (CP_OUT), reverse signal by inverter (U13) output CP_OUT, the reverse signal of the input termination CP_OUT of ∏ type low pass filter, the output of ∏ type low pass filter is sent into voltage controlled oscillator (Y2) control end, and the output of described voltage controlled oscillator (Y2) is connected with network PHY chip (U12);

8. category-B LXI AWG (Arbitrary Waveform Generator) according to claim 7, it is characterized in that: described GPIB/USB interface circuit comprises gpib interface chip (U10), USB interface chip (U29), gpib interface chip (U10) links to each other with local bus interface (U1C), and USB interface chip (U29) links to each other with the local bus interface (U1C) of PowerPC processor.

9. category-B LXI AWG (Arbitrary Waveform Generator) according to claim 8 is characterized in that:

Also comprise in described DDR sdram controller interface (U1B) and the DDR dynamic memory circuit connection line build-out resistor (RN16～RN26),

Also be provided with clock distribution chip (U43) on the clock input link of described master clock and IO mouth (U1D) and PowerPC processor,

Described DDR dynamic memory circuit comprises that also terminating resistor and voltage drive chip (U44), the input of a described DDRSDRAM storage chip (U2) is connected to terminating resistor (R176-R180), and the input of described the 2nd DDR SDRAM storage chip (U3) is connected to terminating resistor (R171-R184).

10. category-B LXI AWG (Arbitrary Waveform Generator) according to claim 9, it is characterized in that: the FPGA control circuit comprises bus interface, command register, status register, configuration register, sequential register, Wave data buffer cell, SDRAM control interface, logical circuit of clock, main control logic and analog channel interface

Described command register, status register and configuration register all interconnect with bus interface and main control logic,

Described sequential register and Wave data buffer cell all interconnect with main control logic and SDRAM control interface,

Described logical circuit of clock and analog channel interface all interconnect with main control logic.

Images