CN202798616U

CN202798616U - Undervoltage latch circuit

Info

Publication number: CN202798616U
Application number: CN 201220485348
Authority: CN
Inventors: 王晓娟; 王纪云; 周晓东
Original assignee: Zhengzhou Dandian Technology Software Co Ltd
Current assignee: Zhengzhou Dandian Technology Software Co Ltd
Priority date: 2012-09-21
Filing date: 2012-09-21
Publication date: 2013-03-13
Anticipated expiration: 2022-09-21

Abstract

The utility model discloses an undervoltage latch circuit. The anode of a schottky barrier diode of the circuit is grounded, a cathode is connected to a grid of a first P-channel Metal Oxide Semiconductor (PMOS) transistor, a grid of a second PMOS transistor, a grid of a first N-channel metal oxide semiconductor (NMOS) transistor and a grid of an NMOS transistor and is connected to a voltage source through a resistor (RC) circuit, an output end of an undervoltage latch voltage signal is connected to a drain of a second PMOS transistor, a drain of the first NMOS transistor, a grid of a third PMOS transistor and a grid of a third NMOS transistor, the source of the first PMOS transistor is connected to the voltage source, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor and the source of the third PMOS transistor, the source of the second NMOS transistor is grounded, the drain of the second NMOS transistor is connected to the source of the first NMOS transistor and the source of the third NMOS transistor, the drain of the third PMOS transistor is grounded and the drain of the third NMOS transistor is connected to the voltage source. The circuit is simple in structure, capable of saving cost and low in power consumption.

Description

Undervoltage latch circuit

Technical field

The utility model relates to a kind of undervoltage latch circuit.

Background technology

In PC and portable electric appts, generally all have central processing element, storage device and peripheral circuit, suddenly outage of external power supply or cell voltage reduce, and all can have influence on work or the data processed, therefore need to latch voltage when the voltage appearance is under-voltage.Existing undervoltage latch circuit complex structure, oneself power consumption is larger, is unfavorable for the application at portable type electronic product.

The utility model content

Goal of the invention of the present utility model is: for the problem of above-mentioned existence, provide a kind of undervoltage latch circuit.

The technical solution adopted in the utility model is such: a kind of undervoltage latch circuit, described circuit comprises the under-voltage voltage signal output end that latchs, and also comprises three PNP transistors, three NPN transistor, Schottky barrier diodes and the RC circuit that is made of electric capacity and resistance parallel connection.

The plus earth of described Schottky barrier diode, negative electrode is connected to the grid of the transistorized grid of a PMOS, the transistorized grid of the 2nd PMOS, the first nmos pass transistor and the grid of the second nmos pass transistor, and this negative electrode also is connected to voltage source by the RC circuit; Under-voltagely latch the grid that voltage signal output end is connected to drain electrode, the transistorized grid of the 3rd POS and the 3rd nmos pass transistor of the transistorized drain electrode of the 2nd PMOS, the first nmos pass transistor; The transistorized source electrode of a described PMOS is connected to voltage source, and drain electrode is connected to the transistorized source electrode of the 2nd PMOS and the transistorized source electrode of the 3rd PMOS; The source ground of described the second nmos pass transistor, drain electrode is connected to the source electrode of the first nmos pass transistor and the source electrode of the 3rd nmos pass transistor; The transistorized grounded drain of described the 3rd PMOS; The drain electrode of described the 3rd nmos pass transistor is connected to voltage source.

In the utility model foregoing circuit, a described PMOS transistor, the 2nd PMOS transistor and the 3rd PMOS transistor are the identical PMOS transistor of parameter.

In the utility model foregoing circuit, described the first nmos pass transistor, the second nmos pass transistor and the 3rd nmos pass transistor are the identical nmos pass transistor of parameter.

In sum, owing to adopted technique scheme, the beneficial effects of the utility model are: circuit structure is simple, saves cost, and oneself power consumption is low.

Description of drawings

Fig. 1 is the circuit theory diagrams of the utility model undervoltage latch circuit.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in detail.

In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.

As shown in Figure 1, be the circuit theory diagrams of the utility model undervoltage latch circuit.

A kind of undervoltage latch circuit of the present utility model, this circuit comprises the under-voltage voltage signal output end Vout that latchs, and also comprises three PNP transistor P1～P3, three NPN transistor N1～N3, Schottky barrier diode Z1 and the RC circuit that is made of capacitor C 1 and resistance R 1 parallel connection.

Elaborate below in conjunction with the annexation between above-mentioned each electronic devices and components of 1 pair of the utility model of accompanying drawing: the plus earth GND of described Schottky barrier diode Z1, negative electrode is connected to the grid of a PMOS transistor P1, the grid of the 2nd PMOS transistor P2, the grid of the first nmos pass transistor N1 and the grid of the second nmos pass transistor N2, and this negative electrode also is connected to voltage source V DD by the RC circuit; The under-voltage voltage signal output end Vout that latchs is connected to the drain electrode of the 2nd PMOS transistor P2, the drain electrode of the first nmos pass transistor N1, the grid of the 3rd POS transistor P3 and the grid of the 3rd nmos pass transistor N3; The source electrode of a described PMOS transistor P1 is connected to voltage source V DD, and drain electrode is connected to the source electrode of the 2nd PMOS transistor P2 and the source electrode of the 3rd PMOS transistor P3; The source ground GND of described the second nmos pass transistor N2, drain electrode is connected to the source electrode of the first nmos pass transistor N1 and the source electrode of the 3rd nmos pass transistor N3; The grounded drain GND of described the 3rd PMOS transistor P3; The drain electrode of described the 3rd nmos pass transistor N3 is connected to voltage source V DD.

In the utility model foregoing circuit, a described PMOS transistor P1, the 2nd PMOS transistor P2 and the 3rd PMOS transistor P3 are the identical PMOS transistor of parameter.

In the utility model foregoing circuit, described the first nmos pass transistor N1, the second nmos pass transistor N2 and the 3rd nmos pass transistor N3 are the identical nmos pass transistor of parameter.

The above only is preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.

Claims

1. undervoltage latch circuit, comprise the under-voltage voltage signal output end (Vout) that latchs, it is characterized in that, also comprise three PNP transistors (P1～P3), three NPN transistor (N1～N3), Schottky barrier diode (Z1) and by electric capacity (C1) and resistance (R1) the RC circuit that consists of in parallel;

The plus earth (GND) of described Schottky barrier diode (Z1), negative electrode is connected to the grid of a PMOS transistor (P1), the grid of the 2nd PMOS transistor (P2), the grid of the first nmos pass transistor (N1) and the grid of the second nmos pass transistor (N2), and this negative electrode also is connected to voltage source (VDD) by the RC circuit; The under-voltage voltage signal output end (Vout) that latchs is connected to the drain electrode of the 2nd PMOS transistor (P2), the drain electrode of the first nmos pass transistor (N1), the grid of the 3rd POS transistor (P3) and the grid of the 3rd nmos pass transistor (N3); The source electrode of a described PMOS transistor (P1) is connected to voltage source (VDD), and drain electrode is connected to the source electrode of the 2nd PMOS transistor (P2) and the source electrode of the 3rd PMOS transistor (P3); The source ground (GND) of described the second nmos pass transistor (N2), drain electrode is connected to the source electrode of the first nmos pass transistor (N1) and the source electrode of the 3rd nmos pass transistor (N3); The grounded drain (GND) of described the 3rd PMOS transistor (P3); The drain electrode of described the 3rd nmos pass transistor (N3) is connected to voltage source (VDD).

2. undervoltage latch circuit according to claim 1 is characterized in that, a described PMOS transistor (P1), the 2nd PMOS transistor (P2) and the 3rd PMOS transistor (P3) are the identical PMOS transistor of parameter.

3. undervoltage latch circuit according to claim 1 is characterized in that, described the first nmos pass transistor (N1), the second nmos pass transistor (N2) and the 3rd nmos pass transistor (N3) are the identical nmos pass transistor of parameter.