CN202259304U - Double-table-board silicon wafer for manufacturing chips - Google Patents
Double-table-board silicon wafer for manufacturing chips Download PDFInfo
- Publication number
- CN202259304U CN202259304U CN2011203969199U CN201120396919U CN202259304U CN 202259304 U CN202259304 U CN 202259304U CN 2011203969199 U CN2011203969199 U CN 2011203969199U CN 201120396919 U CN201120396919 U CN 201120396919U CN 202259304 U CN202259304 U CN 202259304U
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- Prior art keywords
- junction
- isolation channel
- back side
- silicon wafer
- junction isolation
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Abstract
The utility model discloses a double-table-board silicon wafer for manufacturing chips. The double-table-board silicon wafer comprises a silicon wafer body (1), wherein a front-side PN junction (2) and a back-side PN junction (3) are respectively arranged on the front side and the back side of the silicon wafer body (1); front-side PN junction isolation grooves (4) dividing the front-side PN junction (2) are formed on the front side of the silicon wafer body (1) at intervals; back-side PN junction isolation grooves (5) dividing the back-side PN junction (3) are formed on the back side of the silicon wafer body (1) at intervals; and the distance between the adjacent front-side PN junction isolation grooves (4) is different from that between the adjacent back-side PN junction isolation grooves (5). As the PN junction isolation grooves with different spaces therebetween are provided, the distance between the parts of the silicon wafer with minimum thicknesses is increased, the breaking probability of the silicon wafer in the production process is lowered, and the product qualification rate is improved while the difficulty in manufacturing the double-table-board silicon wafer is lowered; and the double-table-board silicon wafer for manufacturing chips has the advantages of simple structure, low manufacturing cost, high qualification rate, low monocrystalline defects and suitability for popularized use.
Description
Technical field
The utility model relates to the silicon chip that is used to make chip, specifically a kind of two table top silicon chips that are used to make chip.
Background technology
At present, general two table tops or the single table surface silicon wafer to manufacture chip of adopting.No matter be two table tops silicon chip or or the silicon chip of single table surface, all need on silicon chip, make PN junction and PN junction isolation channel; The PN junction isolation channel spacing of making on wherein two table top silicon chips equates and is symmetrical, makes that the fragment of two table top silicon chips is many, and the scribing equipment precision requirement that chip is cut apart is higher, causes the qualification rate of chip lower; Need spreading for a long time through high temperature logical isolation of PN junction isolation channel on the single table surface silicon chip caused defective to monocrystalline silicon in addition, causes the chip qualification rate low, and cost is higher, and consistency is relatively poor.
Summary of the invention
The purpose of the utility model is the defective to prior art, provide a kind of simple in structure, make easily, single-crystal fault is low, product percent of pass is high and the two table top silicon chips that are used to make chip of low cost of manufacture.
The purpose of the utility model solves through following technical scheme:
A kind of two table top silicon chips that are used to make chip; Comprise silicon chip; The front and back of said silicon chip is respectively equipped with front PN junction and back side PN junction; Wherein the front of silicon chip is arranged at intervals with the front PN junction isolation channel of separating the front PN junction, and silicon chip back is arranged at intervals with the back side PN junction isolation channel of separating back side PN junction; Spacing between spacing between the said adjacent front surfaces PN junction isolation channel and the adjacent back side PN junction isolation channel does not wait.
Spacing between the described adjacent front surfaces PN junction isolation channel is less than the spacing between the PN junction isolation channel of the adjacent back side.
The setting of staggering each other of described front PN junction isolation channel and back side PN junction isolation channel.
Described front PN junction isolation channel and back side PN junction isolation channel are deep-slotted chip breaker.
The radius of said front PN junction isolation channel is less than the radius of back side PN junction isolation channel.
The height of the PN junction upper edge, bottom to front of said front PN junction isolation channel is greater than the thickness of front PN junction.
The height of the PN junction lower edge, bottom to the back side of said back side PN junction isolation channel is greater than the thickness of back side PN junction.
Described silicon chip adopts N type silicon chip or P type silicon chip.
The utility model is compared prior art has following advantage:
The utility model is through being provided with two-layer PN junction on the just back of the body surface of silicon chip; And the mode of the PN junction isolation channel that spacing varies in size is set on double-deck PN junction; The distance at the minimum place of silicon wafer thickness is strengthened; Reduce the cracked in process of production probability of silicon chip, when reducing two table top silicon chip manufacture difficulty, improved the qualification rate of product.
The product structure of the utility model is simple, production cost is low, and the product percent of pass height and the single-crystal fault that prepare are low, suitable promoting the use of.
Description of drawings
Accompanying drawing 1 is the structural representation of the utility model.
Wherein: 1-silicon chip; 2-front PN junction; 3-back side PN junction; 4-front PN junction isolation channel; 5-back side PN junction isolation channel.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment; Further illustrate the utility model; Should understand this embodiment only be used to the utility model is described and be not used in the restriction utility model scope; After having read the utility model, those skilled in the art all fall within the application's accompanying claims institute restricted portion to the modification of the various equivalent form of values of the utility model.
As shown in Figure 1: a kind of two table top silicon chips that are used to make chip; Comprise silicon chip 1; Silicon chip 1 can adopt N type or P type silicon chip according to actual needs; Front and back at silicon chip 1 is respectively equipped with front PN junction 2 and back side PN junction 3, and this front PN junction 2 all is after mixing impurity in the silicon chip 1, to form with back side PN junction 3, and front PN junction 2 evenly is arranged on the front and back of silicon chip 1 with back side PN junction 3.Be arranged at intervals with the front PN junction isolation channel 4 of separating front PN junction 2 in the front of silicon chip 1, this front PN junction isolation channel 4 is a deep-slotted chip breaker, and the height of PN junction 2 upper edges, bottom to front of front PN junction isolation channel 4 is greater than the thickness of front PN junction 2; The back side of silicon chip 1 is arranged at intervals with the back side PN junction isolation channel 5 of separating back side PN junction 3, and this back side PN junction isolation channel 5 is a deep-slotted chip breaker, and the height of PN junction 3 lower edges, bottom to the back side of back side PN junction isolation channel 5 is greater than the thickness of back side PN junction 3.Front PN junction isolation channel 4 and back side PN junction isolation channel 5 setting of staggering each other in addition; Not only the radius of front PN junction isolation channel 4 is less than the radius of back side PN junction isolation channel 5, and the spacing between the adjacent front surfaces PN junction isolation channel 4 is less than the spacing between the adjacent back side PN junction isolation channel 5.
The utility model is through being provided with two-layer PN junction on the just back of the body surface of silicon chip; And the mode of the PN junction isolation channel that spacing varies in size is set on double-deck PN junction; The distance at the minimum place of silicon wafer thickness is strengthened; Reduce the cracked in process of production probability of silicon chip, when reducing two table top silicon chip manufacture difficulty, improved the qualification rate of product; The characteristics that product has is simple in structure, production cost is low, the product percent of pass height and the single-crystal fault that prepare are low, suitable promoting the use of.
The technology that the utility model does not relate to all can realize through prior art.
Claims (8)
1. two table top silicon chips that are used to make chip; Comprise silicon chip (1); The front and back that it is characterized in that said silicon chip (1) is respectively equipped with front PN junction (2) and back side PN junction (3); Wherein the front of silicon chip (1) is arranged at intervals with the front PN junction isolation channel (4) of separating front PN junction (2), and the back side of silicon chip (1) is arranged at intervals with the back side PN junction isolation channel (5) of separating back side PN junction (3); Spacing between spacing between the said adjacent front surfaces PN junction isolation channel (4) and the adjacent back side PN junction isolation channel (5) does not wait.
2. the two table top silicon chips that are used to make chip according to claim 1 is characterized in that spacing between the described adjacent front surfaces PN junction isolation channel (4) is less than the spacing between the adjacent back side PN junction isolation channel (5).
3. the two table top silicon chips that are used to make chip according to claim 1 and 2 is characterized in that the setting of staggering each other of described front PN junction isolation channel (4) and back side PN junction isolation channel (5).
4. the two table top silicon chips that are used to make chip according to claim 1 is characterized in that described front PN junction isolation channel (4) and back side PN junction isolation channel (5) are deep-slotted chip breaker.
5. the two table top silicon chips that are used to make chip according to claim 4 is characterized in that the radius of the radius of said front PN junction isolation channel (4) less than back side PN junction isolation channel (5).
6. the two table top silicon chips that are used to make chip according to claim 1, the height of bottom to front PN junction (2) upper edge that it is characterized in that said front PN junction isolation channel (4) is greater than the thickness of front PN junction (2).
7. the two table top silicon chips that are used to make chip according to claim 1, the height of bottom to back side PN junction (3) lower edge that it is characterized in that said back side PN junction isolation channel (5) is greater than the thickness of back side PN junction (3).
8. the two table top silicon chips that are used to make chip according to claim 1 is characterized in that described silicon chip (1) adopts N type silicon chip or P type silicon chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203969199U CN202259304U (en) | 2011-10-18 | 2011-10-18 | Double-table-board silicon wafer for manufacturing chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203969199U CN202259304U (en) | 2011-10-18 | 2011-10-18 | Double-table-board silicon wafer for manufacturing chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202259304U true CN202259304U (en) | 2012-05-30 |
Family
ID=46120502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011203969199U Withdrawn - After Issue CN202259304U (en) | 2011-10-18 | 2011-10-18 | Double-table-board silicon wafer for manufacturing chips |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202259304U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332466A (en) * | 2011-10-18 | 2012-01-25 | 宜兴市环洲微电子有限公司 | Double-mesa silicon chip for manufacturing chip |
-
2011
- 2011-10-18 CN CN2011203969199U patent/CN202259304U/en not_active Withdrawn - After Issue
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332466A (en) * | 2011-10-18 | 2012-01-25 | 宜兴市环洲微电子有限公司 | Double-mesa silicon chip for manufacturing chip |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20120530 Effective date of abandoning: 20130306 |
|
| RGAV | Abandon patent right to avoid regrant |