CN201514935U

CN201514935U - Single crystal wafer with asymmetric chamfer at edge

Info

Publication number: CN201514935U
Application number: CN200920093957XU
Authority: CN
Inventors: 商亚峰; 姚志勇; 常江; 李昱鑫
Original assignee: Jilin Sino Microelectronics Co Ltd
Current assignee: Jilin Sino Microelectronics Co Ltd
Priority date: 2009-07-07
Filing date: 2009-07-07
Publication date: 2010-06-23
Anticipated expiration: 2019-07-07

Abstract

The utility model relates to a single crystal wafer with an asymmetric chamfer at the edge, which belongs to the technical field of the manufacture of semiconductor devices. The chamfer of the edge of the traditional single crystal wafer is a symmetrical chamfer; when a diffusion layer at one side of the single crystal wafer is removed, the chamfer of the edge is changed into an asymmetric chamfer; and the asymmetric chamfer has large stress, is easy to cause edge collapse and dark stripe fragments, raises the fragment rate and increases the cost. The single crystal wafer concerned in the utility model is an intermediate product in the manufacture process of the semiconductor devices, is formed by cutting a silicon single crystal bar processed by a rolling circle, is in a wafer state and is divided into two layers, i.e. a removing layer and a retaining layer. The chamfer of the edge of the single crystal wafer is the asymmetric chamfer. Moreover, corresponding to the condition that the single crystal wafer is divided into the removing layer and the retaining layer, the chamfer of the edge of the single crystal wafer is also divided into two parts, i.e. the chamfer of the removing layer and the chamfer of the retaining layer, and the chamfer of the retaining layer is the symmetrical chamfer. The utility model is applied to the processing procedure of a substrate slice in the field of the manufacture of the semiconductor devices.

Description

The asymmetric chamfering single-chip in edge

Technical field

The asymmetric chamfering single-chip in the edge of the utility model is a kind of intermediate products in semiconductor device chip manufacturing process, belongs to the semiconductor device processing technology field.

Background technology

In the grinding field, the technology that edge of work corner angle are removed is called chamfering, and the edge of work shape of process chamfering is also referred to as chamfering.From the chamfering section, that chamfer shape has is circular-arc, oblique line shape etc.For laminar workpiece, when both sides of edges all has chamfering and chamfer shape identical, constitute a kind of symmetrical chamfering, the chamfering of both sides of edges is with respect to being positioned at laminar workpiece one half thickness place and being parallel to the plane symmetry of laminar surface of the work.

To cut into single-chip through the silicon single crystal bar of round as a ball processing, the single chip edge surface ratio is more coarse, has corner angle, burr, collapses defective such as limit, even crack and other defect also can occur, causes the single chip edge mechanical strength to reduce, and also has particle contaminant.This just need be with the single chip edge chamfering to eliminate described defective.See shown in Figure 1ly, chamfering is exactly grinding single-chip 1 edge, obtains arc angling 2, perhaps trapezoidal chamfering 3 is seen shown in Figure 2ly, is called R type chamfering, T type chamfering at the single-chip manufacture field, all belonging to symmetrical chamfering, is two types of chamferings that single-chip generally adopts.It is terminal and perpendicular to the distance h=T/2 of the straight line on single-chip surface, T is a single-chip thickness that chamfering has been on the summit of chamfering.

As the substrate slice of making semiconductor chip, require single-chip after through diffusion, the diffusion layer of a side to be removed, the single-chip with R type chamfering or T type chamfering that uses is after processing through described removal at present, the single chip edge both sides chamfering of this moment is with respect to the single-chip one half thickness place that is positioned at this moment and to be parallel to the plane on single-chip surface asymmetric, constitute asymmetric chamfering, see Fig. 3, shown in Figure 4, this asymmetric plane strain is big, cause collapsing limit, dark line fragment easily, fragment rate rises, and cost increases.

The utility model content

Collapse limit and dark line fragment problems in order to solve single-chip what follow-up diffusion layer removed that the processing back occurs, reduce fragment rate, reduce production costs, we have proposed a key name is the technical scheme of the asymmetric chamfering single-chip in edge.

The utility model is to realize like this, related single-chip is a kind of intermediate products in fabrication of semiconductor device, form by silicon single crystal bar cutting through round as a ball processing, be the disk shape, be divided into two-layer, see shown in Figure 5, promptly remove layer 4 and retaining layer 5, it is characterized in that the single chip edge chamfering is asymmetric chamfering, and, with single-chip be divided into remove layer 4 and retaining layer 5 corresponding, the single chip edge chamfering also is divided into two parts, promptly removes layer chamfering 6 and retaining layer chamfering 7, and retaining layer chamfering 7 is symmetrical chamfering.

The technique effect of the technical scheme of the utility model is, the edge has the single-chip of asymmetric chamfering after the process diffusion technology, a side diffusion layer that needs to remove is removed layer 4 exactly, the single-chip of removing behind this removal layer 4 has only retaining layer 5, at this moment single chip edge chamfering just has only retaining layer chamfering 7, and retaining layer chamfering 7 is with respect to being positioned at retaining layer 5 one half thickness places and being parallel to the plane symmetry on single-chip surface, so retaining layer chamfering 7 is a kind of symmetrical chamferings, see shown in Figure 6, thereby the reason of stress cause collapse the limit, dark line fragment phenomenon reduces, improve rate of finished products, reduced cost.In the actual production course of processing, because the fragment rate that edge stress causes is reduced to 0.3%, fragment rate is reduced to 0.75% in follow-up chip manufacturing proces.

Description of drawings

Fig. 1 is the R type symmetry chamfering schematic diagram in the single chip edge chamfering of prior art.Fig. 2 is the T type symmetry chamfering schematic diagram in the single chip edge chamfering of prior art.Fig. 3 is that edge R type symmetry chamfering became asymmetric chamfering schematic diagram after the single-chip of prior art was removed a side diffusion layer.Fig. 4 is that edge T type symmetry chamfering became asymmetric chamfering schematic diagram after the single-chip of prior art was removed a side diffusion layer.Fig. 5 is that the single chip edge chamfering of the utility model is a kind of asymmetric chamfering schematic diagram, the double accompanying drawing that makes an abstract of this figure.Fig. 6 is that the single-chip of the utility model is removed layer to be removed the back edge chamfering be a kind of symmetrical chamfering schematic diagram.

Embodiment

Of the present utility model is such specific implementation, related single-chip is a kind of intermediate products in fabrication of semiconductor device, it is the diffusion and furbishing sheet (DW) that is used for making the substrate slice of chip, form by silicon single crystal bar cutting through round as a ball processing, be the disk shape, thickness is 535+10 μ m, be divided into two-layer, see shown in Figure 5, promptly remove layer 4 and retaining layer 5, the single chip edge chamfering is asymmetric chamfering, it is asymmetric with respect to being positioned at single-chip one half thickness place and being parallel to the plane on single-chip surface to be the single chip edge chamfering, and, with single-chip be divided into remove layer 4 and retaining layer 5 corresponding, the single chip edge chamfering also is divided into two parts, promptly removes layer chamfering 6 and retaining layer chamfering 7, retaining layer chamfering 7 is symmetrical chamfering, and promptly retaining layer chamfering 7 is with respect to being positioned at retaining layer 5 one half thickness places and being parallel to the plane symmetry on single-chip surface.Remove layer chamfering 6 one end and single-chip surface and intersect, the other end links to each other with an end of retaining layer chamfering 7, and intersect on another surface of the other end of retaining layer chamfering 7 and single-chip.It is terminal and perpendicular to the distance h of the straight line on single-chip surface that retaining layer chamfering 7 has been on the summit of single chip edge chamfering ₁In 130 ± 100 mu m ranges, the summit of single chip edge chamfering to " cross to remove layer chamfering 6 and single-chip surface intersection point and perpendicular to the single-chip surface " the distance h of straight line ₂In 500 ± 100 mu m ranges, the angle theta on the extended line of single chip edge chamfering and single-chip surface is in 30 ± 2 ° of scopes.

Claims

1. asymmetric chamfering single-chip in edge, related single-chip is a kind of intermediate products in fabrication of semiconductor device, form by silicon single crystal bar cutting through round as a ball processing, be the disk shape, be divided into two-layer, promptly remove layer (4) and retaining layer (5), it is characterized in that, the single chip edge chamfering is asymmetric chamfering, and, with single-chip be divided into remove layer (4) and retaining layer (5) corresponding, the single chip edge chamfering also is divided into two parts, promptly remove layer chamfering (6) and retaining layer chamfering (7), retaining layer chamfering (7) is symmetrical chamfering.

2. the asymmetric chamfering single-chip in edge according to claim 1, it is characterized in that, remove layer chamfering (6) one end and single-chip surface and intersect, the other end links to each other with an end of retaining layer chamfering (7), and intersect on another surface of the other end of retaining layer chamfering (7) and single-chip.

3. the asymmetric chamfering single-chip in edge according to claim 1, it is characterized in that, single-chip thickness is 535 ± 10 μ m, the summit of single chip edge chamfering be retaining layer chamfering (7) terminal and perpendicular to the distance (h1) of the straight line on single-chip surface in 130 ± 100 mu m ranges, the summit of single chip edge chamfering be remove layer chamfering (6) and single-chip surface intersection point, and in 500 ± 100 mu m ranges, the angle (θ) on the extended line of single chip edge chamfering and single-chip surface is in 30 ± 2 ° of scopes perpendicular to the distance (h2) of the straight line on single-chip surface.