CN202257350U - DC voltage deviation canceling circuit - Google Patents
DC voltage deviation canceling circuit Download PDFInfo
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- CN202257350U CN202257350U CN2011203958512U CN201120395851U CN202257350U CN 202257350 U CN202257350 U CN 202257350U CN 2011203958512 U CN2011203958512 U CN 2011203958512U CN 201120395851 U CN201120395851 U CN 201120395851U CN 202257350 U CN202257350 U CN 202257350U
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Abstract
A DC voltage deviation canceling circuit comprises a first input end, a second input end, a balancer, a limiting amplifier, a first output end, a second output end, a low-pass filter and a canceling control circuit, wherein the canceling control circuit comprises a first capacitor connected with the first input end, a second capacitor connected with the second input end, a first resistor connected with the first capacitor, a second resistor connected with the first resistor, a third resistor connected with the second resistor, a fourth resistor connected with the third resistor, a fifth resistor, a first field-effect transistor connected with the fifth resistor, the second resistor and the third resistor, a second field-effect transistor connected with the third resistor, the fourth resistor and the low-pass filter, and a third field-effect transistor connected with the first resistor, the second resistor and the low-pass filter. The DC voltage deviation canceling circuit reduces the load of a high-speed path.
Description
Technical field
The utility model relates to a kind of variation and eliminates circuit, refers to that especially a kind of dc voltage offset simple in structure, that common mode input is controlled and the feedback gain adjustment scope is bigger eliminates circuit.
Background technology
In serial data transmission system; In the time will carrying out differential signal transmission; Because of the loss of differential signal on transmission medium, cause in the transmission course of differential signal, the common mode voltage of differential signal can squint; Transmitting terminal and receiving end can produce DC coupling, finally cause the DC voltage of input differential signal to squint.
In addition, because the power supply situation of transmission line terminal device and incomplete same, a plurality of factors such as incomplete coupling of equipment itself and load stack up, and can reduce the error margins of signal sampling to a certain extent, make the bit error rate raise.Therefore be necessary to provide a kind of dc voltage offset simple in structure, that common mode input is controlled and the feedback gain adjustment scope is bigger to eliminate circuit.
Summary of the invention
In view of above content, be necessary to provide a kind of dc voltage offset simple in structure, that common mode input is controlled and the feedback gain adjustment scope is bigger to eliminate circuit.
A kind of dc voltage offset is eliminated circuit; Said dc voltage offset is eliminated the elimination control circuit that low-pass filter and that second output terminal, that first output terminal, that limiting amplifier, that balanced device, that circuit comprises that a first input end, one second input end, link to each other with said first input end and said second input end links to each other with said balanced device links to each other with said limiting amplifier links to each other with said limiting amplifier links to each other with said balanced device and said limiting amplifier links to each other with said low-pass filter, said balanced device, said first input end and said second input end, and said elimination control circuit comprises the 3rd FET that second FET and that the 4th resistance that the 3rd resistance, one that second resistance, one that first resistance, one that second electric capacity, one that first electric capacity, one that links to each other with said first input end links to each other with said second input end links to each other with said first electric capacity links to each other with said first resistance links to each other with said second resistance links to each other with said the 3rd resistance, first FET, that one the 5th resistance, one links to each other with said the 5th resistance, said second resistance and said the 3rd resistance link to each other with said the 3rd resistance, said the 4th resistance and said low-pass filter links to each other with said first resistance, said second resistance and said low-pass filter.
Preferably; Said first input end links to each other with an end of said first electric capacity; The other end of said first electric capacity links to each other with an end of said first resistance and a first input end of said balanced device; Said second input end links to each other with an end of said second electric capacity, and the other end of said second electric capacity links to each other with an end of said the 4th resistance and one second input end of said balanced device.
Preferably; The other end of said first resistance and the common drain electrode that is connected said the 3rd FET of an end of said second resistance, the grid of an end of the other end of said second resistance, said the 3rd resistance, an end of said the 5th resistance and said first FET, the common reference voltage end that connects of drain electrode.
Preferably; The common drain electrode that connects said second FET of the other end of the other end of said the 3rd resistance and said the 4th resistance; The grid of said second FET links to each other with one second output terminal of said low-pass filter, and the grid of said the 3rd FET links to each other with one first output terminal of said low-pass filter.
Preferably, the other end of said the 5th resistance connects a power end, the common earth terminal that connects of the source class of the source class of said first FET, said second FET and the source class of said the 3rd FET.
Preferably; One first output terminal of said balanced device and one second input end of said low-pass filter are connected a first input end of said limiting amplifier jointly; One second output terminal of said balanced device and a first input end of said low-pass filter are connected one second input end of said limiting amplifier jointly; One first output terminal of said limiting amplifier connects said first output terminal, and one second output terminal of said limiting amplifier connects said second output terminal.
Relative prior art; The utility model dc voltage offset elimination circuit will be eliminated control module and be located between input end and the balanced device; Input end with directly being sent to balanced device after the dc voltage offset elimination has reduced the high speed channel load, has promoted the speed that dc voltage offset is eliminated; And the utility model has been realized the control to common mode input through to extracting the control of size of current, and is simple in structure, and the feedback gain adjustment scope is big.
Description of drawings
Fig. 1 eliminates the system architecture diagram of circuit preferred embodiments for the utility model dc voltage offset.
Fig. 2 eliminates the circuit diagram of circuit preferred embodiments for the utility model dc voltage offset.
Embodiment
See also Fig. 1, the utility model dc voltage offset is eliminated the elimination control circuit that low-pass filter and that second output terminal, that first output terminal, that limiting amplifier, that balanced device, that the circuit preferred embodiments comprises that a first input end, one second input end, link to each other with this first input end and this second input end links to each other with this balanced device links to each other with this limiting amplifier links to each other with this limiting amplifier links to each other with this balanced device and this limiting amplifier links to each other with this low-pass filter, this balanced device, this first input end and this second input end.This first input end and this second input end are used to import a pair of differential signal.This first output terminal and this second output terminal are used to export a pair of differential signal of eliminating after the dc voltage offset.This balanced device is used for the differential signal of the distortion of this first input end and the input of this second input end is adjusted, with the loss of compensate for poor sub-signal spectrum component on transmission medium.This limiting amplifier is used to control the amplitude of the differential signal of this first output terminal and the output of this second output terminal.This low-pass filter is used for the high frequency spectrum energy that filtering receives, and the low frequency spectrum energy is sent to the elimination control module.This elimination control module is used to eliminate the skew of the DC voltage that this low-pass filter transmits.
See also Fig. 2, Fig. 2 eliminates the physical circuit figure of circuit preferred embodiments for the utility model dc voltage offset.Wherein, This first input end is first input end INP; This second input end is the second input end INN, and this balanced device is balanced device EQ, and this limiting amplifier is limiting amplifier LA; This first output terminal is the first output terminal OUTP; This second output terminal is the second output terminal OUTN, and this low-pass filter is low-pass filter LF, and this elimination control circuit comprises one first capacitor C 1, one second capacitor C 2, one first resistance R 1, one second resistance R 2, one the 3rd resistance R 3, one the 4th resistance R 4, one the 5th resistance R 5, one first FET M1, one second FET M2 and one the 3rd FET M3.
The physical circuit annexation that the utility model dc voltage offset is eliminated the circuit preferred embodiments is following: this first input end INP links to each other with an end of this first capacitor C 1, and the other end of this first capacitor C 1 links to each other with an end of this first resistance R 1 and the first input end of this balanced device EQ.This second input end INN links to each other with an end of this second capacitor C 2, and the other end of this second capacitor C 2 links to each other with an end of the 4th resistance R 4 and one second input end of this balanced device EQ.The other end of this first resistance R 1 and an end of this second resistance R 2 are connected the drain electrode of the 3rd FET M3 jointly, the grid of an end of the other end of this second resistance R 2, the 3rd resistance R 3, an end of the 5th resistance R 5 and this first FET M1, the common reference voltage end Vref that connects of drain electrode.The other end of the other end of the 3rd resistance R 3 and the 4th resistance R 4 connects the drain electrode of this second FET M2 jointly.The grid of this second FET M2 links to each other with one second output terminal of this low-pass filter LF, and receives the voltage Vcmn of this low-pass filter LF output.The grid of the 3rd FET M3 links to each other with one first output terminal of this low-pass filter LF, and receives the voltage Vcmp of this low-pass filter LF output.The other end of the 5th resistance R 5 connects a power end VDD, the common earth terminal GND that connects of the source class of the source class of this first FET M1, this second FET M2 and the source class of the 3rd FET M3.One first output terminal of this balanced device EQ and one second input end of this low-pass filter are connected a first input end of this limiting amplifier jointly, and one second output terminal of this balanced device EQ and a first input end of this low-pass filter are connected one second input end of this limiting amplifier jointly.One first output terminal of this limiting amplifier connects this first output terminal OUTP, and one second output terminal of this limiting amplifier connects this second output terminal OUTN.
The principle of work that the utility model dc voltage offset is eliminated the circuit preferred embodiments is following: this first capacitor C 1 is at a distance from straight coupling capacitance with this second capacitor C 2; The resistance of this second resistance R 2 equates with the resistance of the 3rd resistance R 3; The resistance of this first resistance R 1 equates with the resistance of the 4th resistance R 4, and the resistance of the resistance of this second resistance R 2 and the 3rd resistance R 3 is far smaller than the resistance of this first resistance R 1 and the resistance of the 4th resistance R 4.
The signal of supposing this first input end INP input does not have dc voltage offset, and the direct current of this second input end INN input signal is pressed with skew.After differential signal process this balanced device EQ and this low-pass filter LF of this first input end INP and this second input end INN input, difference output dc voltage Vcmp and DC voltage Vcmn.
Owing to flow through the electric current of this second FET M2 be:
;
K=
wherein;
is the mobility of FET technology; Cox is the gate oxide thickness of FET technology, and Vth is the threshold voltage of FET.
Because the resistance of the 4th resistance R 4 is far longer than the resistance of the 3rd resistance R 3, so the drain voltage Vd of this second FET M2 is approximately equal to the DC voltage Vn of this second input end INN input signal.
Then:
.
Therefore can find out from above two formulas; The value of the 3rd resistance R 3 and reference voltage Vref is invariable; Then DC voltage Vcmn and electric current
are proportional; The DC voltage Vn of input signal and electric current
relation of being inversely proportional to, the DC voltage Vn of input signal and the DC voltage Vcmn relation of being inversely proportional to.
When the direct current of the second input end INN is pressed with skew; DC voltage Vcmn through behind balanced device EQ and the low-pass filter LF can change; Thereby cause this second FET M2 from the circuit that the 3rd resistance R 3 and the 4th resistance R 4 are formed, to extract current Ib; Because the DC voltage Vn and electric current
relation of being inversely proportional to of input signal; Therefore the DC voltage Vn of input signal also can change; DC voltage Vn after the variation further is input to entire circuit, and up to the skew of eliminating DC voltage, this dc voltage offset is eliminated circuit and is in steady state (SS).
In like manner; When the direct current of first input end INP is pressed with skew; DC voltage Vcmp through behind balanced device EQ and the low-pass filter LF can change; Thereby cause the 3rd FET M3 from the circuit that this first resistance R 1 and this second resistance R 2 are formed, to extract electric current
; Because relation also is inversely proportional to for the DC voltage Vp of input signal and electric current
; Therefore the DC voltage Vp of input signal also can change; DC voltage Vp after the variation further is input to entire circuit; Up to the skew of eliminating DC voltage, this dc voltage offset is eliminated circuit and is in steady state (SS).
The utility model dc voltage offset elimination circuit will be eliminated control module and be located between input end and the balanced device; With the input end that directly is sent to balanced device after the dc voltage offset elimination; Reduce the high speed channel load, promoted the speed that dc voltage offset is eliminated; And the utility model has been realized the control to common mode input through to extracting the control of size of current, and is simple in structure, and the feedback gain adjustment scope is big.
Claims (6)
1. a dc voltage offset is eliminated circuit; It is characterized in that: said dc voltage offset is eliminated the elimination control circuit that low-pass filter and that second output terminal, that first output terminal, that limiting amplifier, that balanced device, that circuit comprises that a first input end, one second input end, link to each other with said first input end and said second input end links to each other with said balanced device links to each other with said limiting amplifier links to each other with said limiting amplifier links to each other with said balanced device and said limiting amplifier links to each other with said low-pass filter, said balanced device, said first input end and said second input end, and said elimination control circuit comprises the 3rd FET that second FET and that the 4th resistance that the 3rd resistance, one that second resistance, one that first resistance, one that second electric capacity, one that first electric capacity, one that links to each other with said first input end links to each other with said second input end links to each other with said first electric capacity links to each other with said first resistance links to each other with said second resistance links to each other with said the 3rd resistance, first FET, that one the 5th resistance, one links to each other with said the 5th resistance, said second resistance and said the 3rd resistance link to each other with said the 3rd resistance, said the 4th resistance and said low-pass filter links to each other with said first resistance, said second resistance and said low-pass filter.
2. dc voltage offset as claimed in claim 1 is eliminated circuit; It is characterized in that: said first input end links to each other with an end of said first electric capacity; The other end of said first electric capacity links to each other with an end of said first resistance and a first input end of said balanced device; Said second input end links to each other with an end of said second electric capacity, and the other end of said second electric capacity links to each other with an end of said the 4th resistance and one second input end of said balanced device.
3. dc voltage offset as claimed in claim 2 is eliminated circuit; It is characterized in that: the other end of said first resistance and the common drain electrode that is connected said the 3rd FET of an end of said second resistance, the grid of an end of the other end of said second resistance, said the 3rd resistance, an end of said the 5th resistance and said first FET, the common reference voltage end that connects of drain electrode.
4. dc voltage offset as claimed in claim 3 is eliminated circuit; It is characterized in that: the common drain electrode that connects said second FET of the other end of the other end of said the 3rd resistance and said the 4th resistance; The grid of said second FET links to each other with one second output terminal of said low-pass filter, and the grid of said the 3rd FET links to each other with one first output terminal of said low-pass filter.
5. dc voltage offset as claimed in claim 4 is eliminated circuit; It is characterized in that: the other end of said the 5th resistance connects a power end, the common earth terminal that connects of the source class of the source class of said first FET, said second FET and the source class of said the 3rd FET.
6. dc voltage offset as claimed in claim 5 is eliminated circuit; It is characterized in that: one first output terminal of said balanced device and one second input end of said low-pass filter are connected a first input end of said limiting amplifier jointly; One second output terminal of said balanced device and a first input end of said low-pass filter are connected one second input end of said limiting amplifier jointly; One first output terminal of said limiting amplifier connects said first output terminal, and one second output terminal of said limiting amplifier connects said second output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203958512U CN202257350U (en) | 2011-10-18 | 2011-10-18 | DC voltage deviation canceling circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203958512U CN202257350U (en) | 2011-10-18 | 2011-10-18 | DC voltage deviation canceling circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202257350U true CN202257350U (en) | 2012-05-30 |
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ID=46118564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011203958512U Withdrawn - After Issue CN202257350U (en) | 2011-10-18 | 2011-10-18 | DC voltage deviation canceling circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202257350U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102340301A (en) * | 2011-10-18 | 2012-02-01 | 四川和芯微电子股份有限公司 | Direct current voltage offset cancellation circuit and system |
| CN103984384A (en) * | 2014-05-09 | 2014-08-13 | 中国电子科技集团公司第七研究所 | Self-adaptive tracking circuit of middle-point level |
-
2011
- 2011-10-18 CN CN2011203958512U patent/CN202257350U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102340301A (en) * | 2011-10-18 | 2012-02-01 | 四川和芯微电子股份有限公司 | Direct current voltage offset cancellation circuit and system |
| CN102340301B (en) * | 2011-10-18 | 2013-09-04 | 四川和芯微电子股份有限公司 | Direct current voltage offset cancellation circuit and system |
| CN103984384A (en) * | 2014-05-09 | 2014-08-13 | 中国电子科技集团公司第七研究所 | Self-adaptive tracking circuit of middle-point level |
| CN103984384B (en) * | 2014-05-09 | 2015-09-30 | 中国电子科技集团公司第七研究所 | Mid point level adaptive tracing circuit |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20120530 Effective date of abandoning: 20130904 |
|
| RGAV | Abandon patent right to avoid regrant |