CN103984384A - Self-adaptive tracking circuit of middle-point level - Google Patents

Self-adaptive tracking circuit of middle-point level Download PDF

Info

Publication number
CN103984384A
CN103984384A CN201410196817.0A CN201410196817A CN103984384A CN 103984384 A CN103984384 A CN 103984384A CN 201410196817 A CN201410196817 A CN 201410196817A CN 103984384 A CN103984384 A CN 103984384A
Authority
CN
China
Prior art keywords
point level
datum
level
mid point
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410196817.0A
Other languages
Chinese (zh)
Other versions
CN103984384B (en
Inventor
徐红霞
郑澍鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 7 Research Institute
Original Assignee
CETC 7 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 7 Research Institute filed Critical CETC 7 Research Institute
Priority to CN201410196817.0A priority Critical patent/CN103984384B/en
Publication of CN103984384A publication Critical patent/CN103984384A/en
Application granted granted Critical
Publication of CN103984384B publication Critical patent/CN103984384B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Superheterodyne Receivers (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

The invention discloses a self-adaptive tracking circuit of a middle-point level. The self-adaptive tracking circuit is characterized in that coarse adjustment and fine adjustment are carried out on a reference level provided for an AD (Analog-Digital) chip so as to track the middle-point level; no matter how the level drifts, the difference value between the reference level and the middle-point level keeps below a threshold value, so that demodulation data outputted by the AD chip is correct. The coarse-adjustment mode comprises the following steps of measuring middle-point level values and temperature-voltage values under different temperatures in advance, establishing a corresponding relation between the middle-point level values and the temperature-voltage values, finding the corresponding relation to use the middle-point level value corresponding to the current temperature-voltage value as a coarse adjustment value; the fine-adjustment mode comprises the following step of determining the direction of the fine adjustment according to quantities of related codes 0 and 1 in sampling data of the AD chip; the stepping of the fine adjustment adapts to the processability of an adopted device. From the above, the self-adaptive tracking circuit disclosed by the invention has the advantages that due to adoption of the mode of self-adaptive tracking, the difference between the middle-point level and the reference level is eliminated, the influence of drifting of the middle-point level on the demodulation data is avoided, and the reliable communication under the severe environmental temperature is ensured.

Description

Mid point level adaptive tracing circuit
Technical field
The present invention relates to wireless communication technology field, particularly relate to a kind of mid point level adaptive tracing circuit.
Background technology
Wireless communication system receives signal and often adopts superhet, and its principle of work as shown in Figure 1.The frequency discrimination of superhet is generally being processed through the Low Medium Frequency after treatment of frequency conversion amplification filtering several times, and common frequency detection mode has direct frequency discrimination (as pulsimeter numerical expression frequency-discrimination method) and indirect frequency discrimination (as waveform transformation method, phase-locked link demodulation method and frequency modulation negative feedback demodulation method, orthogonal frequency-discrimination method etc.).
Current orthogonal frequency-discrimination method is modal a kind of frequency detection mode, and its principle of work as shown in Figure 2.Which is mainly passed through 90 of intermediate-freuqncy signal ° of phase shifts, then carry out product with the intermediate-freuqncy signal of self and recover modulation signal, finally carry out filtering out-of-band-signal by low-pass filter, give AD chip sampled signal and carry out digital processing or the direct output audio signal of process audio driven filtering.
The phase shift network of orthogonal frequency detection mode is made up of inductance and electric capacity, in the time realizing the phase shift of Low Medium Frequency (as the intermediate frequency 455kHz signal in common superhet), need to participate in the inductance of resonance and the reactance of electric capacity increases, inductance is generally selected by coil winding magnetic core mode and is promoted induction reactance, by changing the inductance of suitably adjusting induction reactance in magnetic core position also referred to as middle week.In cause, there is ferrite magnetic material all inside, under high and low temperature environment, magnetic permeability can change, the inductance value in middle week changes thereupon, therefore middle week is a temperature sensitive device, can cause that resonance frequency off-centring causes the mid point level skew (output characteristics is as shown in Figure 3) of output, inconsistent with the datum that AD chip provides, when their difference exceedes thresholding, cause the demodulating data of AD output abnormal, Wireless Telecom Equipment cannot receive correct data.
General employing every straight or comparer tracking mode eliminated this mid point level skew, but these two kinds of modes are more suitable for voice communication.Because in frequency-hopping communication system due to the burst of data, and may there is longer company 0 or connect 1 in data stream, if adopt capacitance or comparer tracking mode, can cause loss of data, cannot proper communication at rugged environment temperature, and every Nogata formula and comparer tracking mode because there is the long time that discharges and recharges, so response speed is slow, cause bursty data to be made mistakes, thereby be not suitable for frequency-hopping communication system.
Summary of the invention
Based on above-mentioned situation, the present invention proposes a kind of mid point level adaptive tracing circuit, bring the problem of mid point level skew to solve simulation frequency discrimination, realize the skew of adaptive tracing mid point level, under rugged surrounding temperature, ensure reliable communication.For this reason, the technical scheme of employing is as follows.
A kind of mid point level adaptive tracing circuit, comprises AD chip, programmable logic device (PLD) and datum adjustment unit, and described datum adjustment unit comprises temperature sensor, analog-to-digital conversion module, D/A converter module, level adjusting module;
In described datum adjustment unit, environment temperature is converted to analog voltage by described temperature sensor, this analog voltage is converted to digital voltage value by described analog-to-digital conversion module, described level adjusting module reads the digital voltage value that Current Temperatures is corresponding, search the corresponding relation between the mid point level value of superhet demodulation under the different temperatures of measuring in advance and recording and digital voltage value that described temperature sensor records, obtain the mid point level value corresponding with Current Temperatures, using this value as exporting to described AD chip with reference to level after described D/A converter module conversion,
Described AD chip receives the demodulated analog signal of superhet output, according to the datum of described datum adjustment unit output, this demodulated analog signal is carried out to analog to digital conversion sampling, after sampling, be sent to described programmable logic device (PLD), described programmable logic device (PLD) carries out exporting to corresponding equipment after data processing to the demodulated digital signal after sampling, demodulated digital signal is carried out to associated code detection simultaneously, if associated code more than 0 to 1, notify the level adjusting module of described datum adjustment unit to turn datum down, if associated code more than 1 to 0, notify described level adjusting module to tune up datum, described level adjusting module reception notification is also adjusted datum.
Mid point level adaptive tracing circuit of the present invention, complete the sampling of analog to digital and carry out coarse adjustment and fine tuning offering the datum of AD chip, to follow the tracks of mid point level, no matter how mid point level drifts about, difference between datum and mid point level is always remained on below threshold value, thereby the demodulating data of AD chip output is correct.Wherein, the mode of coarse adjustment is mid point level value and the temperature voltage value of measuring in advance under different temperatures, sets up the corresponding relation between the two, searches this corresponding relation using mid point level value corresponding Current Temperatures magnitude of voltage as coarse adjustment value; The mode of fine tuning is according to the direction of how many definite fine tunings of associated code 0 and 1 in AD chip sampled data, and the stepping of fine tuning adapts with the processing power of adopted device.To sum up, this circuit adopts the mode of adaptive tracing, eliminates the difference between mid point level and datum, and the impact of having avoided mid point level to drift about on demodulating data, has ensured the reliable communication under rugged surrounding temperature.
Brief description of the drawings
Fig. 1 is superhet theory diagram;
Fig. 2 is orthogonal frequency discrimination principle schematic;
Fig. 3 is orthogonal frequency discrimination output characteristics schematic diagram;
Fig. 4 is the structural representation of mid point level adaptive tracing circuit of the present invention;
Fig. 5 is the waveform schematic diagram that datum is lower than mid point level;
Fig. 6 is the waveform schematic diagram that datum is higher than mid point level.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is described in further detail.Should be appreciated that embodiment described herein, only in order to explain the present invention, does not limit protection scope of the present invention.
Because causing the mid point level of demodulation under different temperatures, the responsive to temperature characteristic of device under orthogonal frequency detection mode is offset, when difference between the datum that mid point level after being offset and AD (analog to digital conversion) chip provide exceedes thresholding, the demodulating data of AD chip output is abnormal.As long as but the mid point level that the datum that offers AD chip can be followed the tracks of demodulation, the demodulating data of AD chip output is exactly correct.In line with this thought, inventor has designed following adaptive tracing circuit.
Mid point level adaptive tracing circuit of the present invention, as shown in Figure 4, comprise AD chip, programmable logic device (PLD) and datum adjustment unit, described datum adjustment unit comprises temperature sensor, analog-to-digital conversion module (ADC), D/A converter module (DAC), level adjusting module.
The course of work of each unit and module is as follows:
In described datum adjustment unit, environment temperature is converted to analog voltage by described temperature sensor, this analog voltage is converted to digital voltage value by described analog-to-digital conversion module, described level adjusting module reads the digital voltage value that Current Temperatures is corresponding, search the corresponding relation between the mid point level value of superhet demodulation under the different temperatures of measuring in advance and recording and digital voltage value that described temperature sensor records, obtain the mid point level value corresponding with Current Temperatures, after described D/A converter module conversion, export to described AD chip using this value as the coarse adjustment value with reference to level,
Described AD chip receives the demodulated analog signal of superhet output, according to the coarse adjustment value of the datum of described datum adjustment unit output, this demodulated analog signal is carried out to analog to digital conversion sampling, after sampling, be sent to described programmable logic device (PLD), described programmable logic device (PLD) carries out exporting to corresponding equipment after corresponding data processing to the demodulated digital signal after sampling, demodulated digital signal is carried out to associated code detection simultaneously, if associated code more than 0 to 1, notify the level adjusting module of described datum adjustment unit to turn datum down, if associated code more than 1 to 0, notify described level adjusting module to tune up datum, described level adjusting module reception notification also carries out fine tuning to datum, datum after described D/A converter module fine tuning is exported to described AD chip after being converted to simulating signal,
Described AD chip continues the demodulated analog signal of superhet output to carry out analog to digital conversion sampling according to the datum after adjusting.
Known from the above description, the realization of this programme needs to measure in advance mid point level value and the temperature voltage value under various environment temperatures, forms a corresponding table, and deposits in the level adjusting module of datum adjustment unit, for inquiry.After power on circuitry, programmable logic device (PLD) receives AD sampled data, checks whether receive associated code, and judges associated code more than 0 or more than 1.If more than 1, description references level adjustment unit is lower than the mid point level of demodulated analog signal to the datum of AD chip, sees Fig. 5, need to increase reference level value, programmable logic device (PLD) is exported the notification signal that datum increases, and preferably adopts the form of look-at-me.If more than 0, the datum that description references level adjustment unit is exported to AD chip is higher than the mid point level of demodulated analog signal, sees 6, need to reduce reference level value, programmable logic device (PLD) is exported the notification signal that datum reduces, and preferably adopts the form of look-at-me.So, determine the direction of datum fine tuning, and the size of datum fine tuning is relevant with the ability of the deal with data of datum adjustment unit, as adopt the not single-chip microcomputer of isotopic number, figure place is higher, and the stepping of fine tuning can be less, and the precision of fine tuning is higher, but the time of expending is longer, slip-stick artist can go balance according to actual needs.
Datum adjustment unit in this circuit can be with the single-chip microcomputer of temperature sensor or microprocessor (ARM, POWERPC) etc., can be also IC temperature sensor and microprocessor.Programmable logic device (PLD) can be specifically FPGA unit.
To sum up, this programme records demodulation mid point level value and the temperature voltage value under different temperatures, and formation temperature table corresponding to mid point level determined the datum coarse adjustment value that AD samples, associated code detects determines datum fine tuning, realizes the datum adaptive tracing demodulation mid point level of AD sampling.This adaptive method, is equally also applicable to solve the mid point level offset problem that other simulation frequency detection modes (as modes such as waveform transformation method, phase-locked link demodulation method and frequency modulation negative feedback demodulation methods) bring.
The above embodiment has only expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.

Claims (5)

1. a mid point level adaptive tracing circuit, is characterized in that,
Comprise AD chip, programmable logic device (PLD) and datum adjustment unit, described datum adjustment unit comprises temperature sensor, analog-to-digital conversion module, D/A converter module, level adjusting module;
In described datum adjustment unit, environment temperature is converted to analog voltage by described temperature sensor, this analog voltage is converted to digital voltage value by described analog-to-digital conversion module, described level adjusting module reads the digital voltage value that Current Temperatures is corresponding, search the corresponding relation between the mid point level value of superhet demodulation under the different temperatures of measuring in advance and recording and digital voltage value that described temperature sensor records, obtain the mid point level value corresponding with Current Temperatures, using this value as exporting to described AD chip with reference to level after described D/A converter module conversion,
Described AD chip receives the demodulated analog signal of superhet output, according to the datum of described datum adjustment unit output, this demodulated analog signal is carried out to analog to digital conversion sampling, after sampling, be sent to described programmable logic device (PLD), described programmable logic device (PLD) carries out exporting to corresponding equipment after data processing to the demodulated digital signal after sampling, demodulated digital signal is carried out to associated code detection simultaneously, if associated code more than 0 to 1, notify the level adjusting module of described datum adjustment unit to turn datum down, if associated code more than 1 to 0, notify described level adjusting module to tune up datum, described level adjusting module reception notification is also adjusted datum.
2. mid point level adaptive tracing circuit according to claim 1, is characterized in that,
Described datum adjustment unit is single-chip microcomputer or the microprocessor with temperature sensor.
3. mid point level adaptive tracing circuit according to claim 1 and 2, is characterized in that,
Described programmable logic device (PLD) is FPGA unit.
4. mid point level adaptive tracing circuit according to claim 1 and 2, is characterized in that,
The described level adjusting module output precision of datum and the processing figure place of single-chip microcomputer or micro-processing match.
5. mid point level adaptive tracing circuit according to claim 1 and 2, is characterized in that,
Described FPGA unit adopts the mode of interrupting to notify described level adjusting module.
CN201410196817.0A 2014-05-09 2014-05-09 Mid point level adaptive tracing circuit Active CN103984384B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410196817.0A CN103984384B (en) 2014-05-09 2014-05-09 Mid point level adaptive tracing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410196817.0A CN103984384B (en) 2014-05-09 2014-05-09 Mid point level adaptive tracing circuit

Publications (2)

Publication Number Publication Date
CN103984384A true CN103984384A (en) 2014-08-13
CN103984384B CN103984384B (en) 2015-09-30

Family

ID=51276396

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410196817.0A Active CN103984384B (en) 2014-05-09 2014-05-09 Mid point level adaptive tracing circuit

Country Status (1)

Country Link
CN (1) CN103984384B (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6160388A (en) * 1997-12-30 2000-12-12 Texas Instruments Incorporated Sensing of current in a synchronous-buck power stage
CN101533285A (en) * 2009-03-31 2009-09-16 炬力集成电路设计有限公司 A reference voltage buffer circuit
CN102273069A (en) * 2008-11-04 2011-12-07 努吉拉有限公司 Improved power supply stage
CN202257350U (en) * 2011-10-18 2012-05-30 四川和芯微电子股份有限公司 DC voltage deviation canceling circuit
CN103092248A (en) * 2012-12-31 2013-05-08 华为技术有限公司 Feedforward control method and device
CN103186157A (en) * 2011-12-28 2013-07-03 擎泰科技股份有限公司 Linear voltage regulating circuit adaptable to a logic system
CN203151378U (en) * 2011-11-04 2013-08-21 爱特梅尔公司 Power conversion feedback control circuit
CN103650313A (en) * 2011-05-05 2014-03-19 北极砂技术有限公司 DC-DC converter with modular stages

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6160388A (en) * 1997-12-30 2000-12-12 Texas Instruments Incorporated Sensing of current in a synchronous-buck power stage
CN102273069A (en) * 2008-11-04 2011-12-07 努吉拉有限公司 Improved power supply stage
CN101533285A (en) * 2009-03-31 2009-09-16 炬力集成电路设计有限公司 A reference voltage buffer circuit
CN103650313A (en) * 2011-05-05 2014-03-19 北极砂技术有限公司 DC-DC converter with modular stages
CN202257350U (en) * 2011-10-18 2012-05-30 四川和芯微电子股份有限公司 DC voltage deviation canceling circuit
CN203151378U (en) * 2011-11-04 2013-08-21 爱特梅尔公司 Power conversion feedback control circuit
CN103186157A (en) * 2011-12-28 2013-07-03 擎泰科技股份有限公司 Linear voltage regulating circuit adaptable to a logic system
CN103092248A (en) * 2012-12-31 2013-05-08 华为技术有限公司 Feedforward control method and device

Also Published As

Publication number Publication date
CN103984384B (en) 2015-09-30

Similar Documents

Publication Publication Date Title
CN105309039B (en) Envelope extraction device, signal decoding apparatus and short distance non-contact communication device and correlation technique
US9404727B2 (en) Inductive position sensing with single channel interface to multiple resonant sensors
CN1894859B (en) A time signal receiver and decoder
CN103782559A (en) Bi-phase communication demodulation methods and apparatus
JP5805576B2 (en) Resonant type wireless power transmission device
KR20160148035A (en) Systems and methods for measuring power and impedance in wireless power charging systems
US10700903B2 (en) Circuit structure for efficiently demodulating FSK signal in wireless charging device
US20210019019A1 (en) Signal processing system, chip and active stylus
JP2001266102A (en) Demodulator for non-contact chip card
CN110954749B (en) Electric automobile wireless charging phase detection circuit for realizing frequency tracking
CN101933299A (en) Fsk receiver
JP4914501B2 (en) Reception circuit and method for changing Q of resonance circuit
JP2011228826A (en) Interface device
JP4793372B2 (en) Communication apparatus and demodulation method
CN103984384A (en) Self-adaptive tracking circuit of middle-point level
KR101543646B1 (en) Apparatus for TYPE-A Demodulation and Integrated Circuit Card having the same
CN101079648B (en) An ultra-regeneration receiving device
US9093954B2 (en) Bask demodulator and method for demodulating bask modulated signal
JP2009060203A (en) Optical receiving signal interruption detection circuit and optical receiving signal interruption detection method
CN106405205B (en) Zero-crossing detection circuit
US8477879B2 (en) System and method for bi-phase modulation decoding
US20140320264A1 (en) Carrier compensation reader
EP3667935B1 (en) Method and system for operating a communications device that communicates via inductive coupling
CN102761315A (en) Small group delay crystal filter
CN100380805C (en) FM signal receriver and wireless communication device using the receiver

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant