CN105978540B - A kind of postemphasis processing circuit and its method of continuous time signal - Google Patents
A kind of postemphasis processing circuit and its method of continuous time signal Download PDFInfo
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- CN105978540B CN105978540B CN201610356866.5A CN201610356866A CN105978540B CN 105978540 B CN105978540 B CN 105978540B CN 201610356866 A CN201610356866 A CN 201610356866A CN 105978540 B CN105978540 B CN 105978540B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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Abstract
The present invention relates to postemphasis processing circuit and the method for a kind of continuous time signal, which includes：Buffer input signal device, the first variable gain amplifier, the second variable gain amplifier, active level translator, continuous time delay unit and continuous time summing circuit.Method includes：Processing, equilibrium treatment, and driving late-class circuit are amplified to input signal；The control of gain twice is carried out to the output signal after enhanced processing, equilibrium treatment；The signal exported after wherein gain control in controlling gain twice carries out the translation of common mode electrical level；Continuous time signal after being translated to common mode electrical level carries out delay process；The gain signal of another output in time delayed signal and the control of gain twice is subjected to summation operation of postemphasising.Postemphasis processing circuit and its method of a kind of continuous time signal provided by the invention carry out processing of postemphasising to high-speed data signal by controlling voltage swing, improve the accuracy of data transmission.
Description
Technical field
The present invention relates to data communication systems, believe more particularly to a kind of continuous time of non-full swing data communication system
Number postemphasis processing circuit and its method.
Background technology
In common high-speed data signal deaccentuator, all there can be clock to control the shooting sequence of data,
And data are usually the digital signal of the completely amplitude of oscillation, and full swing digital signals control the current-Mode Circuits of output stage, lead to
Switch motion and the load end resistance for crossing input pipe carry out charge and discharge to output load capacitance.Since full swing signal can be protected
The fully on and shutdown of input pipe switch is demonstrate,proved, therefore the tail current of current-Mode Circuits can ensure to be added on load electricity completely substantially
On resistance, in current-mode deaccentuator, the operation coefficient that postemphasises is controlled by tail current source.But when input signal is not
The full amplitude of oscillation when input pipe can not be made fully on and shutdown, just needs the bandwidth problem for considering current-Mode Circuits, due to not at this time
It is different from the bandwidth of broad band amplifier that input switch pipe, load end resistance are formed with tail current size, if data frequency is low
In all bandwidth, then the operation of postemphasising of signal is not influenced, but if data rate is even higher than each between each bandwidth
Bandwidth, at this time postemphasis operation output will mistake, be unable to reach and accurately postemphasis purpose.
Invention content
Present invention aims at solving the above problems, a kind of postemphasis processing circuit and its side of continuous time signal are proposed
Method goes to realize the coefficient that postemphasises, is mainly used in high-speed interface circuit transmitting terminal, believes high-speed data by controlling voltage swing
Number processing of postemphasising is carried out, to improve the accuracy of data transmission.
To achieve the goals above, on the one hand, the present invention provides a kind of processing circuit that postemphasises of continuous time signal, should
Circuit includes：Buffer input signal device, for being amplified processing, equilibrium treatment, and driving late-class circuit to input signal；
First variable gain amplifier is connect with the buffer input signal device, the signal for exporting to buffer input signal device into
Row gain controls；Second variable gain amplifier is connect with buffer input signal device, for what is exported to buffer input signal device
Signal carries out gain control；Active level translator is connect with the first variable gain amplifier, for being put to the first variable gain
The signal of big device output carries out the translation of common mode electrical level；Continuous time delay unit is connect with active level translator, for pair
The continuous time signal of active level translator output carries out delay process；Continuous time summing circuit was used for continuous time
The time delayed signal of delay unit output and the gain signal of the second variable gain amplifier output carry out summation operation of postemphasising.
On the other hand, the present invention provides a kind of processing method of postemphasising of continuous time signal, include the following steps：It is right
Input signal is amplified processing, equilibrium treatment, and driving late-class circuit；To the output letter after enhanced processing, equilibrium treatment
Number carry out gain twice control；The signal exported after wherein gain control in controlling gain twice carries out common mode electrical level
Translation；Delay process is carried out to the continuous time signal exported after the translation of common mode electrical level；Prolong what is exported after delay process
When signal and gain twice control in the gain signal of another output carry out summation operation of postemphasising.
Postemphasis processing circuit and its method of a kind of continuous time signal provided by the invention, by controlling voltage swing
It goes to realize the coefficient that postemphasises, is mainly used in high-speed interface circuit transmitting terminal, processing of postemphasising is carried out to high-speed data signal, with
Improve the accuracy of data transmission.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of the processing circuit that postemphasises of continuous time signal provided in an embodiment of the present invention；
Fig. 2 is a kind of variable gain amplifier of the processing circuit that postemphasises for continuous time signal that inventive embodiments provide
Schematic diagram；
Fig. 3 is a kind of continuous time summation electricity of the processing circuit that postemphasises for continuous time signal that inventive embodiments provide
The schematic diagram on road；
Fig. 4 is a kind of flow chart of the processing method of postemphasising for continuous time signal that inventive embodiments provide.
Specific implementation mode
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
Fig. 1 is a kind of structural schematic diagram of the processing circuit that postemphasises of continuous time signal provided in an embodiment of the present invention.
As shown in Figure 1, the circuit includes：Buffer input signal device 101, the first variable gain amplifier A102, the second variable gain are put
Big device B103, active level translator 104, continuous time delay unit 105 and continuous time summing circuit 106.
Buffer input signal device 101 is used to be amplified processing, equilibrium treatment, and driving rear class electricity to input signal
Road.
First variable gain amplifier A102 is connect with the buffer input signal device 101, for buffer input signal
The signal that device 101 exports carries out gain control, realizes zooming in or out for input signal.
Second variable gain amplifier B103, connect with buffer input signal device 101, for buffer input signal device
The signal of 101 outputs carries out gain control.
Active level translator 104 is connect with the first variable gain amplifier A102, for amplifying to the first variable gain
The signal of device A102 output carries out the translation of common mode electrical level, with ensure late-class circuit be operated in normal common-mode input range it
It is interior.
Active level shifting circuit 104 is mainly used for realizing level conversion function, under the premise of ensureing that AC signal is constant,
It realizes level shift function, suitable DC common-mode input voltage is provided for late-class circuit.
Continuous time delay unit 105 is connect with active level translator 104, for defeated to active level translator 104
The continuous time signal gone out carries out delay process, under the premise of ensureing not changing input signal amplitude, realizes signal delay work(
Energy.
Continuous time summing circuit 106, the time delayed signal and described second for exporting continuous time delay unit 105
The gain signal of variable gain amplifier B103 outputs carries out summation operation of postemphasising.
The embodiment of the present invention can go to realize the coefficient that postemphasises by controlling voltage swing, be mainly used in high-speed interface electricity
Road transmitting terminal carries out processing of postemphasising to high-speed data signal, to improve the accuracy of data transmission.
Fig. 2 is a kind of variable gain amplifier of the processing circuit that postemphasises for continuous time signal that inventive embodiments provide
Schematic diagram.As shown in Fig. 2, the first variable gain amplifier A102 includes：First input transistors 202', the second input crystal
Pipe 202 ", the first load resistance 203' and the second load resistance 203 "；Wherein, the inputs of the first input transistors 202' and second are brilliant
Body pipe 202 " is in parallel by the first load resistance 203' and the second load resistance 203 " respectively, and is grounded via tail current source 201.
Wherein, the third end of the first input transistors 202' and the second input transistors 202 " and buffer input signal device
101 output ends are connected, the first load resistance 203' and the second load resistance 203 " it is in parallel after with active level translator 104
Input terminal connects.
Variable gain amplifier zooms in or out processing to the output signal of buffer input signal device, is ensureing bandwidth
Under the premise of enough, by adjusting the load resistance of variable gain amplifier, to increase to two variable gain amplifiers
Benefit setting, realizes different amplification coefficients, the amplitude processing before operation of completing to postemphasis.
Preferably, the second variable gain amplifier B103 is identical as the circuit structure of the first variable gain amplifier A102.
Fig. 3 is a kind of continuous time summation electricity of the processing circuit that postemphasises for continuous time signal that inventive embodiments provide
The schematic diagram on road.
As shown in figure 3, continuous time summing circuit 106 includes：First current source 501', the second current source 501 ", input
Transistor M1, input transistors M2, input transistors M3, input transistors M4, the load electricity of the first load resistance 503' and second
Resistance 503 "；Wherein, input transistors M1 and the one end input transistors M3 are connect with the first load resistance 503', the other end respectively with
First current source 501' and the connection of the second current source 501 "；Input transistors M2 and the one end input transistors M4 and the second load electricity
503 " connection of resistance, the other end are connect with the first current source 501' and the second current source 501 " respectively.
Wherein, the third end point of input transistors M1 and input transistors M3 and input transistors M2 and input transistors M4
It is not connected with the output end of the output end of continuous time delay unit 105 and the second variable gain amplifier B103.
Preferably, first current source (501') and the second current source (501 ") are identical in continuous time summing circuit 106；It is defeated
It is mutually the same to enter transistor (M1), input transistors (M2), input transistors (M3) and input transistors (M4).
Fig. 4 is a kind of flow chart of the processing method of postemphasising for continuous time signal that inventive embodiments provide.Such as Fig. 4 institutes
Show, the processing method of postemphasising of continuous time signal is completed by step 101-105：
In step 101, processing, equilibrium treatment, and driving late-class circuit are amplified to input signal；
In step 102, the control of gain twice is carried out to the output signal after enhanced processing, equilibrium treatment；
In step 103, the signal exported after the wherein gain control in controlling gain twice carries out common mode electrical level
Translation；
In step 104, the continuous time signal after being translated to common mode electrical level carries out delay process；
In step 105, by the increasing of another output in the time delayed signal exported after delay process and the control of gain twice
Beneficial signal carries out summation operation of postemphasising.
Postemphasis processing circuit and its method of a kind of continuous time signal provided in an embodiment of the present invention, by controlling electricity
The pressure amplitude of oscillation goes to realize the coefficient that postemphasises, and is mainly used in high-speed interface circuit transmitting terminal, postemphasises to high-speed data signal
Processing, to improve the accuracy of data transmission.
Above-described specific implementation mode has carried out further the purpose of the present invention, technical solution and advantageous effect
It is described in detail, it should be understood that the foregoing is merely the specific implementation mode of the present invention, is not intended to limit the present invention
Protection domain, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (6)
1. a kind of processing circuit that postemphasises of continuous time signal, which is characterized in that including：
Buffer input signal device (101), for being amplified processing, equilibrium treatment, and driving late-class circuit to input signal；
First variable gain amplifier A (102) is connect with the buffer input signal device (101), for the input signal
The signal of buffer (101) output carries out gain control；
Second variable gain amplifier B (103) is connect with the buffer input signal device (101), for the input signal
The signal of buffer (101) output carries out gain control；
Active level translator (104) connect with the first variable gain amplifier A (102), for variable to described first
The signal of gain amplifier A (102) outputs carries out the translation of common mode electrical level；
Continuous time delay unit (105) is connect with the active level translator (104), for the active electrical flat turn
The continuous time signal of parallel operation (104) output carries out delay process；
Continuous time summing circuit (106), for the time delayed signal that exports the continuous time delay unit (105) with it is described
The gain signal of second variable gain amplifier B (103) outputs carries out summation operation of postemphasising.
2. circuit according to claim 1, which is characterized in that the first variable gain amplifier A (102) or described
Two variable gain amplifier B (103) include：First input transistors (202'), the second input transistors (202 "), the first load
Resistance (203') and the second load resistance (203 ")；Wherein, the first input transistors (202') and the second input transistors
(202 ") are in parallel by the first load resistance (203') and the second load resistance (203 ") respectively, and via tail current source (201)
Ground connection.
3. circuit according to claim 1, which is characterized in that the continuous time summing circuit (106) includes：First electricity
Stream source (501'), the second current source (501 "), input transistors M1, input transistors M2, input transistors M3, input transistors
M4, the first load resistance (503') and the second load resistance (503 ")；Wherein, input transistors M1 and the one end input transistors M3
It is connect with the first load resistance (503'), the other end is connect with the first current source (501') and the second current source (501 ") respectively；
Input transistors M2 and the one end input transistors M4 are connect with the second load resistance (503 "), the other end respectively with the first current source
(501') and the second current source (501 ") connect.
4. circuit according to claim 3, which is characterized in that first current source (501') and second current source
(501 ") are identical；Input transistors M1, input transistors M2, input transistors M3 and input transistors M4 are mutually the same.
5. circuit according to claim 1, which is characterized in that the basic structure of the continuous time delay unit (105)
By the unit cascaded realization of gain-changeable amplifier circuit.
6. a kind of processing method of postemphasising of continuous time signal, which is characterized in that include the following steps：
Processing, equilibrium treatment, and driving late-class circuit are amplified to input signal；
The control of gain twice is carried out to the output signal after enhanced processing, equilibrium treatment；
The signal exported after wherein gain control in controlling the gain twice carries out the translation of common mode electrical level；
Continuous time signal after being translated to the common mode electrical level carries out delay process；
By the gain signal of another output in the time delayed signal exported after the delay process and the gain twice control
Carry out summation operation of postemphasising.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610356866.5A CN105978540B (en) | 2016-05-26 | 2016-05-26 | A kind of postemphasis processing circuit and its method of continuous time signal |
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| CN201610356866.5A CN105978540B (en) | 2016-05-26 | 2016-05-26 | A kind of postemphasis processing circuit and its method of continuous time signal |
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| CN105978540A CN105978540A (en) | 2016-09-28 |
| CN105978540B true CN105978540B (en) | 2018-09-18 |
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| CN110928824B (en) * | 2019-11-27 | 2021-06-15 | 西安紫光国芯半导体有限公司 | High frequency off-line driver |
| US11475939B2 (en) * | 2020-12-17 | 2022-10-18 | Micron Technology, Inc. | Apparatuses and methods for input buffer power savings |
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| EP0551561A2 (en) * | 1992-01-13 | 1993-07-21 | Samsung Electronics Co. Ltd. | Digital modulators for use with subnyquist sampling of raster-scanned samples of image intensity |
| CN201409126Y (en) * | 2009-04-17 | 2010-02-17 | 苏州亮智科技有限公司 | Clock synchronous circuit in serialization of high-speed parallel data |
| CN102428653A (en) * | 2009-03-17 | 2012-04-25 | 天工新技术有限公司 | SAW-less, LNA-less low noise receiver |
| WO2015196835A1 (en) * | 2014-06-26 | 2015-12-30 | 华为技术有限公司 | Codec method, device and system |
| CN205792493U (en) * | 2016-05-26 | 2016-12-07 | 英特格灵芯片(天津)有限公司 | A kind of process circuit that postemphasising of continuous time signal |
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2016
- 2016-05-26 CN CN201610356866.5A patent/CN105978540B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0551561A2 (en) * | 1992-01-13 | 1993-07-21 | Samsung Electronics Co. Ltd. | Digital modulators for use with subnyquist sampling of raster-scanned samples of image intensity |
| CN102428653A (en) * | 2009-03-17 | 2012-04-25 | 天工新技术有限公司 | SAW-less, LNA-less low noise receiver |
| CN201409126Y (en) * | 2009-04-17 | 2010-02-17 | 苏州亮智科技有限公司 | Clock synchronous circuit in serialization of high-speed parallel data |
| WO2015196835A1 (en) * | 2014-06-26 | 2015-12-30 | 华为技术有限公司 | Codec method, device and system |
| CN205792493U (en) * | 2016-05-26 | 2016-12-07 | 英特格灵芯片(天津)有限公司 | A kind of process circuit that postemphasising of continuous time signal |
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| CN105978540A (en) | 2016-09-28 |
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Effective date of registration: 20210104 Address after: 100094 Room 601, unit 3, 6 / F, building 2, yard 9, FengHao East Road, Haidian District, Beijing Patentee after: Beijing Weihao integrated circuit design Co.,Ltd. Address before: Room 2701-1, building 2, TEDA service outsourcing park, 19 Xinhuan West Road, Binhai New Area, Tianjin, 300457 Patentee before: INTERNATIONAL GREEN CHIP (TIANJIN) Co.,Ltd. |
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Address after: 100094 Room 601, unit 3, 6 / F, building 2, yard 9, FengHao East Road, Haidian District, Beijing Patentee after: Howell analog integrated circuit (Beijing) Co.,Ltd. Address before: 100094 Room 601, unit 3, 6 / F, building 2, yard 9, FengHao East Road, Haidian District, Beijing Patentee before: Beijing Weihao integrated circuit design Co.,Ltd. |
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