CN105808486A - Implementation of a high speed drive circuit with an active inductor as a load - Google Patents
Implementation of a high speed drive circuit with an active inductor as a load Download PDFInfo
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- CN105808486A CN105808486A CN201410830012.7A CN201410830012A CN105808486A CN 105808486 A CN105808486 A CN 105808486A CN 201410830012 A CN201410830012 A CN 201410830012A CN 105808486 A CN105808486 A CN 105808486A
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- load
- circuit
- speed driving
- driving circuit
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Abstract
The invention provides an implementation method for a high speed drive circuit with an active inductor as a load, as shown in figure 1. In the figure, VIP/VIN are differential input signals of a chip and VOP/VON are differential output signals; high speed driving is realized through three-stage drive circuits; the attenuation caused by imperfection of cables can be seen at a transmitting end of high speed serial communication, so that a passive inductor is frequently used on the last-stage drive circuit to absorb a capacitive load; however, the conventional passive inductor is large in area and sensitive to the process temperature, so that the modeling is complicated and the passive inductor is not beneficial to chip integration; to solve the problem, an active inductor circuit is creatively in the high speed drive circuit, the performance the same as that of the passive inductor can be realized, the chip area can be saved and the chip integration is facilitated.
Description
Technical field
The present invention relates to technical field of integrated circuits, the high-speed driving circuit being particularly load with Active inductor circuit.
Background technology
In serial signal communicates, the signal demand that transmitting terminal sends is through cable transmission to receiving terminal, and the length of cable determines according to actual application scenarios.Under normal circumstances, length of cable is more long, and parasitic capacitance is more big, and they are more many to the decay of input signal HFS, in addition when the speed of signal becomes big, decays just more severe.Therefore typically require at transmitting terminal plus passive inductance, compensate the decay of parasitic capacitance.But traditional on-chip inductor area is big, big with technological temperature deviation, modeling complexity, it is unfavorable for integrated chip.The plurality of advantages such as compared to traditional passive inductance, it is little that Active inductor circuit has area, and reliability is high.
Summary of the invention
The present invention is to solve the problems referred to above, it is provided that for the high-speed driving circuit being load with active inductance of serial signal communication receiver, it is possible to by the zero pole point position of register configuration circuit, reach the performance identical with passive inductive load.
Technical scheme is as follows: the high-speed driving circuit being load with active inductance, it is characterised in that: input differential signal VIP/VIN is after two-stage predrive circuit, and output, to main drive circuit, is finally output as differential signal VOP/VON.Predrive circuit is all with resistance for load, and main drive circuit is with Active inductor circuit for load.The tail current source of high-speed driving circuit is controlled by reference voltage VBN.
Described be load with active inductance high-speed driving circuit, it is characterised in that: controlled the grid voltage in cascode current source by VBN, and finally control the electric current of drive circuit, it is achieved that the biasing circuit of low gate source voltage.
Described be load with active inductance high-speed driving circuit, it is characterised in that: progressively amplify high speed signal with two-stage predrive circuit, finally realize the driving of high speed current mode logic level then through main drive circuit.
Described be load with active inductance high-speed driving circuit, it is characterised in that: predrive circuit is with resistance for load, it is achieved current mode logic level driving circuit.
Described be load with active inductance high-speed driving circuit, it is characterised in that: main drive circuit is with Active inductor circuit for load, it is achieved the function of passive inductance.
Described be load with active inductance high-speed driving circuit, it is characterised in that: Active inductor circuit is with MP and RS for signal path load, it is achieved the impedance matching of drive circuit.
Described be load with active inductance high-speed driving circuit, it is characterised in that: use MN to do level conversion, it is provided that the reasonable bias voltage of MP, and outside shifting the parasitic poles of MP grid onto signal bandwidth, the tail current of MN can be regulated by VBN2.
Described be load with active inductance high-speed driving circuit, it is characterised in that: use CZ to regulate the position of parasitic zero point, it is achieved the gain compensation within signal bandwidth, the size of CZ can be regulated by depositor.
Described be load with active inductance high-speed driving circuit, it is characterised in that: use Resd to be placed on the drain electrode of MN, it is possible to effectively to prevent ESD effect, improve the yield of chip.
Described be load with active inductance high-speed driving circuit, it is characterised in that: main drive circuit uses and can pass through to regulate CZ, MP and RS after active load simultaneously and come the position of control circuit zero point and limit, it is achieved best high frequency response.
Beneficial effects of the present invention is as follows:
Adopt with active inductance be load high-speed driving circuit can saving chip area, improve chip reliability.Additionally by register controlled, improve the motility of system.
Accompanying drawing explanation
Fig. 1 is the module-cascade block diagram of the present invention.
Fig. 2 is the active inductance structural representation of the present invention.
Fig. 3 is the main driving circuit structure schematic diagram of high speed of the present invention.
Detailed description of the invention
As shown in figs. 1 and 3.
The high-speed driving circuit being load with active inductance, it is characterised in that: input differential signal VIP/VIN is after two-stage predrive circuit, and output, to main drive circuit, is finally output as differential signal VOP/VON.Predrive circuit is all with resistance for load, and main drive circuit is with Active inductor circuit for load.The tail current source of high-speed driving circuit is controlled by reference voltage VBN.
Described be load with active inductance high-speed driving circuit, it is characterised in that: controlled the grid voltage in cascode current source by VBN, and finally control the electric current of drive circuit, it is achieved that the biasing circuit of low gate source voltage.
Described be load with active inductance high-speed driving circuit, it is characterised in that: progressively amplify high speed signal with two-stage predrive circuit, finally realize the driving of high speed current mode logic level then through main drive circuit.
Described be load with active inductance high-speed driving circuit, it is characterised in that: predrive circuit is with resistance for load, it is achieved current mode logic level driving circuit.
Described be load with active inductance high-speed driving circuit, it is characterised in that: main drive circuit is with Active inductor circuit for load, it is achieved the function of passive inductance.
Described be load with active inductance high-speed driving circuit, it is characterised in that: Active inductor circuit is with MP and RS for signal path load, it is achieved the impedance matching of drive circuit.
Described be load with active inductance high-speed driving circuit, it is characterised in that: use MN to do level conversion, it is provided that the reasonable bias voltage of MP, and outside shifting the parasitic poles of MP grid onto signal bandwidth, the tail current of MN can be regulated by VBN2.
Described be load with active inductance high-speed driving circuit, it is characterised in that: use CZ to regulate the position of parasitic zero point, it is achieved the gain compensation within signal bandwidth, the size of CZ can be regulated by depositor.
Described be load with active inductance high-speed driving circuit, it is characterised in that: use Resd to be placed on the drain electrode of MN, it is possible to effectively to prevent ESD effect, improve the yield of chip.
Described be load with active inductance high-speed driving circuit, it is characterised in that: main drive circuit uses and can pass through to regulate CZ, MP and RS after active load simultaneously and come the position of control circuit zero point and limit, it is achieved best high frequency response.
Claims (10)
1. the high-speed driving circuit being load with active inductance, it is characterised in that: input differential signal VIP/VIN is after two-stage predrive circuit, and output, to main drive circuit, is finally output as differential signal VOP/VON；Predrive circuit is all with resistance for load, and main drive circuit is with Active inductor circuit for load；The tail current source of high-speed driving circuit is controlled by reference voltage VBN.
2. the high-speed driving circuit being load with active inductance according to claim 1, it is characterised in that: controlled the grid voltage in cascode current source by VBN, and finally control the electric current of drive circuit, it is achieved that the biasing circuit of low gate source voltage.
3. serial signal communication receiver signal deteching circuit according to claim 1, it is characterised in that: input common mode electrical level VinN is connected to the grid of two-pass DINSAR prime amplifier.
4. the high-speed driving circuit being load with active inductance according to claim 1, it is characterised in that: predrive circuit is with resistance for load, it is achieved current mode logic level driving circuit.
5. the high-speed driving circuit being load with active inductance according to claim 1, it is characterised in that: main drive circuit is with Active inductor circuit for load, it is achieved the function of passive inductance.
6. the high-speed driving circuit being load with active inductance according to claim 1 or 5, it is characterised in that: Active inductor circuit is with MP and RS for signal path load, it is achieved the impedance matching of drive circuit.
7. the high-speed driving circuit being load with active inductance according to claim 1 or 5, it is characterized in that: use MN to do level conversion, the reasonable bias voltage of MP is provided, and outside shifting the parasitic poles of MP grid onto signal bandwidth, the tail current of MN can be regulated by VBN2.
8. the high-speed driving circuit being load with active inductance according to claim 1 or 5, it is characterised in that: use CZ to regulate the position of parasitic zero point, it is achieved the gain compensation within signal bandwidth, the size of CZ can be regulated by depositor.
9. the high-speed driving circuit being load with active inductance according to claim 1 or 5, it is characterised in that: use Resd to be placed on the drain electrode of MN, it is possible to effectively to prevent ESD effect, improve the yield of chip.
10. the high-speed driving circuit being load with active inductance according to claim 1 or 5, it is characterized in that: main drive circuit can pass through to regulate CZ after using active load simultaneously, MP and RS comes the position of control circuit zero point and limit, it is achieved best high frequency response.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410830012.7A CN105808486A (en) | 2014-12-29 | 2014-12-29 | Implementation of a high speed drive circuit with an active inductor as a load |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410830012.7A CN105808486A (en) | 2014-12-29 | 2014-12-29 | Implementation of a high speed drive circuit with an active inductor as a load |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105808486A true CN105808486A (en) | 2016-07-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410830012.7A Pending CN105808486A (en) | 2014-12-29 | 2014-12-29 | Implementation of a high speed drive circuit with an active inductor as a load |
Country Status (1)
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| CN (1) | CN105808486A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109412579A (en) * | 2018-09-19 | 2019-03-01 | 京微齐力(北京)科技有限公司 | Circuit of current-mode logic driving |
| CN111026214A (en) * | 2019-11-15 | 2020-04-17 | 芯创智（北京）微电子有限公司 | High-speed buffer circuit of active inductive load |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060071695A1 (en) * | 2004-10-05 | 2006-04-06 | Samsung Electronics Co., Ltd. | Signal driving circuits including inverters |
| KR20070042390A (en) * | 2005-10-18 | 2007-04-23 | 삼성에스디아이 주식회사 | Driving circuit of plasma display panel capable of reducing electro-magnetic wave interference |
| CN102142273A (en) * | 2010-01-29 | 2011-08-03 | 海力士半导体有限公司 | Semiconductor integrated circuit |
| CN102856324A (en) * | 2012-09-18 | 2013-01-02 | 厦门大学 | Silicon-based uniwafer photoelectricity integrated receiving chip for plastic optical fiber communication |
| CN203691420U (en) * | 2013-12-20 | 2014-07-02 | 天津大学 | Photoelectric integrated receiver based on standard SiGe BiCMOS technology |
-
2014
- 2014-12-29 CN CN201410830012.7A patent/CN105808486A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060071695A1 (en) * | 2004-10-05 | 2006-04-06 | Samsung Electronics Co., Ltd. | Signal driving circuits including inverters |
| KR20070042390A (en) * | 2005-10-18 | 2007-04-23 | 삼성에스디아이 주식회사 | Driving circuit of plasma display panel capable of reducing electro-magnetic wave interference |
| CN102142273A (en) * | 2010-01-29 | 2011-08-03 | 海力士半导体有限公司 | Semiconductor integrated circuit |
| CN102856324A (en) * | 2012-09-18 | 2013-01-02 | 厦门大学 | Silicon-based uniwafer photoelectricity integrated receiving chip for plastic optical fiber communication |
| CN203691420U (en) * | 2013-12-20 | 2014-07-02 | 天津大学 | Photoelectric integrated receiver based on standard SiGe BiCMOS technology |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109412579A (en) * | 2018-09-19 | 2019-03-01 | 京微齐力(北京)科技有限公司 | Circuit of current-mode logic driving |
| CN111026214A (en) * | 2019-11-15 | 2020-04-17 | 芯创智（北京）微电子有限公司 | High-speed buffer circuit of active inductive load |
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| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160727 |