CN111026214A

CN111026214A - High-speed buffer circuit of active inductive load

Info

Publication number: CN111026214A
Application number: CN201911119531.1A
Authority: CN
Inventors: 沈炎俊; 吴汉明
Original assignee: Elownipmicroelectronics Beijing Co ltd
Current assignee: Elownipmicroelectronics Beijing Co ltd
Priority date: 2019-11-15
Filing date: 2019-11-15
Publication date: 2020-04-17

Abstract

The invention provides a high-speed buffer circuit of an active inductive load, which comprises: the gate of Mn0 is connected with an input signal Vinp; a drain of Mn0, a first terminal of a resistor R0 and an output terminal of the first active inductor are connected to an output node Outn; the source of Mn0, Mn1 and the first terminal of the current source are connected to node Vs; the second end of the current source is grounded; the gate of Mn1 is connected with an input signal Vinn; the drain of Mn1, the first end of the resistor R1 and the output end of the second active inductor are connected to an output node Outp; the second ends of the resistors R0 and R1 and the first input end of the operational amplifier Mopa are connected to the node Vcm; a second input end of the operational amplifier Mopa is connected with a reference voltage Vref, and an output node and first input nodes of the first active inductor and the second active inductor are connected to a Vcmfb node; the second input nodes of the first active inductor and the second active inductor are both connected with a power supply. The invention can reduce the area of the circuit and fix the common-mode output voltage.

Description

High-speed buffer circuit of active inductive load

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a high-speed buffer circuit of an active inductive load.

Background

With the progressive advance of deep submicron processes, the speed that can be achieved by the process is also higher and higher. Because the parasitics of the device itself are reduced, the unity gain frequency is also increased. In many applications such as high-speed interface circuits, a high-speed clock is required to drive many channels simultaneously, and the parasitic capacitance and resistance caused by the high-speed clock are large, so that a high-speed buffer is required to solve the clock transfer. In addition, at the data transmission port, high-speed data output needs to drive large parasitic capacitance such as a pad ball, which also needs a buffer to transfer data with better quality, so that a better eye pattern can be obtained and the error rate is reduced.

At present, a common cache buffer circuit is mainly a current mode logic structure, which has better common mode noise suppression capability, and the load of the cache buffer circuit is realized by a passive resistor. However, as the working speed is higher and higher, if a certain output amplitude is obtained, the time constant of the RC node of the load becomes larger, so that the output of the RC node is slowly changed, and the quality of the output signal is affected. Further, there are cache circuits implemented with passive inductive loads that are relatively reliable and can achieve good data quality, but the area of the passive inductor can be large and the inductor needs to be separated from the other inductors by a large distance in order to prevent the effects of mutual inductance.

Therefore, it is necessary to provide a new circuit to solve the above problems.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a high-speed buffer circuit of an active inductive load, which can reduce the area of the circuit, ensure the reliable work, fix the common-mode output voltage and obtain better output signal quality.

In order to achieve the above purposes, the invention adopts the technical scheme that: a cache circuit for an active inductive load, comprising: the circuit comprises transistors Mn0 and Mn1, resistors R0 and R1, a first active inductor, a second active inductor and an operational amplifier Mopa;

the gate of Mn0 is connected with an input signal Vinp; a drain of Mn0, a first terminal of a resistor R0 and an output terminal of the first active inductor are connected to an output node Outn; the source of Mn0, Mn1 and the first terminal of the current source are connected to node Vs; the second end of the current source is grounded;

the gate of Mn1 is connected with an input signal Vinn; the drain of Mn1, the first end of the resistor R1 and the output end of the second active inductor are connected to an output node Outp;

the second ends of the resistors R0 and R1 and the first input end of the operational amplifier Mopa are connected to a node Vcm; a second input end of the operational amplifier Mopa is connected with a reference voltage Vref, and an output node and first input nodes of the first active inductor and the second active inductor are connected to a Vcmfb node; the second input nodes of the first active inductor and the second active inductor are both connected with a power supply.

Further, the first active inductor and the second active inductor have the same structure, and specifically include transistors Mp0 and Mn3, a resistor R2, and a capacitor C1:

the gate of Mp0, the first terminal of capacitor C1, the first terminal of resistor R2, and the drain of transistor Mn3 are connected to node V1; the drain of Mp0 and the second terminal of resistor R2 are connected to the output node Out; the source of Mp0 and the second end of capacitor C1 are connected to the power supply; the gate of Mn3 is connected to input node In and the source is connected to ground.

Further, the value of the output common mode voltage Vcm is equal to the value of the reference voltage Vref.

Further, the transistors Mn0, Mn1 are NMOS transistors.

Further, the transistor Mp0 is a PMOS transistor, and Mn3 is an NMOS transistor.

The low dropout linear voltage stabilizing circuit provided by the invention has the advantages that an active device is adopted to realize a high-speed buffer circuit of an active inductive load, the circuit has small area and reliable work, the common-mode output voltage can be fixed, and better output signal quality can be obtained.

Drawings

FIG. 1 is a schematic diagram of a cache circuit for an active inductive load according to the present invention;

fig. 2 is a schematic diagram of a circuit structure of the active inductor according to the present invention.

Detailed Description

In order to make the technical problems solved, the technical solutions adopted, and the technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be further described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a cache circuit of an active inductive load according to the present invention. The invention provides a high-speed buffer circuit of an active inductive load, which comprises: the circuit comprises transistors Mn0 and Mn1, resistors R0 and R1, a first active inductor, a second active inductor and an operational amplifier Mopa.

The invention provides a current mode logic structure of a high-speed buffer circuit of an active inductive load. As shown in fig. 1, the transistors Mn0 and Mn1 are a pair of differential pair transistors, which amplify and output the input signals Vinp and Vinn to obtain differential outputs Outn and Outp. The high-resistance resistors R0 and R1 extract the common-mode voltage outputted by the difference to obtain Vcm, and the voltage is compared with the reference voltage Vref by the operational amplifier Mopa to output the voltage Vcmfb, which is used for adjusting the current of the active inductor until Vref and Vcm are equal.

It should be noted that the value of the output common mode voltage Vcm is equal to the value of the reference voltage Vref. In addition, the whole loop is a negative feedback, and the stability of the loop needs to be ensured in the design.

Due to the characteristics of the differential circuit, the first active inductor and the second active inductor are identical in circuit structure. The first active inductor or the second active inductor comprises transistors Mp0, Mn3, a resistor R2 and a capacitor C1. Specific connections are shown in fig. 2:

The transistor Mp0, the resistor R2 and the capacitor C1 can realize an impedance with inductive characteristics, and the transistor Mn3 provides a suitable operating point for the Mp 0. From the point of view of frequency, the impedance looking into the output node Out is low at low frequency, and is high at high frequency, the position of high frequency is determined by the values of the resistor R2 and the capacitor C1, and the difference between the high frequency and low frequency is determined by the size of the transistor Mp0 and the dc operating point.

It should also be noted that the transistors Mn0, Mn1 are NMOS transistors. The transistor Mp0 is a PMOS transistor, and Mn3 is an NMOS transistor.

Compared with the prior art, the high-speed buffer circuit of the active inductive load provided by the invention adopts the active device to realize the high-speed buffer circuit of the active inductive load, the circuit has small area and reliable work, can fix the common-mode output voltage, and can obtain better output signal quality.

It will be appreciated by persons skilled in the art that the circuit of the present invention is not limited to the embodiments described in the detailed description, and the above detailed description is for the purpose of illustrating the invention and is not intended to limit the invention. Other embodiments will be apparent to those skilled in the art from the following detailed description, which is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims

1. A cache circuit for an active inductive load, the circuit comprising: the circuit comprises transistors Mn0 and Mn1, resistors R0 and R1, a first active inductor, a second active inductor and an operational amplifier Mopa;

2. The active inductive load cache circuit of claim 1, wherein the first and second active inductors are identical in structure, and in particular comprise transistors Mp0, Mn3, resistor R2 and capacitor C1:

3. The active inductive load cache circuit of claim 1, wherein the value of the output common-mode voltage Vcm equals the value of the reference voltage Vref.

4. The active inductive load cache circuit of claim 1 wherein the transistors Mn0, Mn1 are NMOS transistors.

5. The active inductive load cache circuit of claim 2 wherein said transistor Mp0 is a PMOS transistor and Mn3 is an NMOS transistor.