CN101820257B - Switched capacitor circuit and analog-to-digital converter - Google Patents
Switched capacitor circuit and analog-to-digital converter Download PDFInfo
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- CN101820257B CN101820257B CN2010101676174A CN201010167617A CN101820257B CN 101820257 B CN101820257 B CN 101820257B CN 2010101676174 A CN2010101676174 A CN 2010101676174A CN 201010167617 A CN201010167617 A CN 201010167617A CN 101820257 B CN101820257 B CN 101820257B
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Abstract
The invention is suitable for the technical field of signal sampling and provides a switched capacitor circuit and an analog-to-digital converter. The switched capacitor circuit comprises a first driving unit, a first sampling unit, a first sampling and integrating unit and a first operational amplification unit, wherein the first driving unit uses a single-ended input signal as an input signal; the first sampling unit is used for sampling the single-ended input signal during the high level period of a first clock signal; the first sampling and integrating unit is used for sampling a signal of the single-ended input signal output from the first driving unit during the high level period of a third clock signal and integrating a sampling capacitor which is pre-sampled by the first sampling and integrating unit and sampled by the first sampling unit during the high level period of the second clock signal; and the third clock signal, the second clock signal and the first clock signal have the same period, and high levels of the third clock signal, the second clock signal and the first clock signal appear alternatively in turn in a clock period. Therefore, noise on the sampling capacitor caused by the driving unit is reduced and the effective accuracy is improved.
Description
Technical field
The invention belongs to technical field of signal sampling, relate in particular to a kind of switched-capacitor circuit and analog to digital converter.
Background technology
Switched-capacitor circuit is meant the circuit of being made up of the switch of subject clock signal control and capacitor, and it utilizes the storage of electric charge and shifts and realize the various processing capacities to signal.
The present switched-capacitor circuit that is applied to the signal sampling field is in order to improve input impedance; Generally be between input signal and integrated transporting discharging, to insert one drive circuit (BUF); Yet because the introducing meeting of drive circuit is introduced noise to switched-capacitor circuit simultaneously, thereby reduced the effective accuracy of switched-capacitor circuit to signal sampling.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of switched-capacitor circuit, is intended to solve the switched-capacitor circuit that is applied to the signal sampling field that prior art provides because the introducing of drive circuit has reduced the problem to the effective accuracy of signal sampling.
The embodiment of the invention is achieved in that a kind of switched-capacitor circuit, and said circuit comprises:
The first computing amplifying unit comprises an operational amplifier and integrating capacitor C2, and the in-phase input end of said operational amplifier connects common-mode voltage, and the output of said operational amplifier connects the inverting input of said operational amplifier through integrating capacitor C2;
First driver element, the input impedance that is used to improve said switched-capacitor circuit, single-ended input signal is as the signal of said first driver element of input;
First sampling unit is used between the high period of first clock signal, the said single-ended input signal of sampling;
The first sampling integral unit that connects the inverting input of said operational amplifier; Be used between the high period of the 3rd clock signal; The signal that said first driver element of sampling is in advance exported; And between the high period of second clock signal, jointly the signal through said first preparatory sampling of sampling integral unit and the sampling of said first sampling unit is carried out integration with the said first computing amplifying unit;
Said the 3rd clock signal, second clock signal are identical with the cycle of first clock signal, and between the high period of said first clock signal, in a clock cycle, alternately occur in order between the high period of said second clock signal and between the high period of said the 3rd clock signal.
Another purpose of the embodiment of the invention is to provide a kind of analog to digital converter, comprises as stated a switched-capacitor circuit.
Another purpose of the embodiment of the invention is to provide a kind of switched-capacitor circuit, and said circuit comprises:
The first computing amplifying unit comprises an operational amplifier and integrating capacitor C2, and the in-phase input end of said operational amplifier connects common-mode voltage, and the output of said operational amplifier connects the inverting input of said operational amplifier through integrating capacitor C2;
First driver element, the input impedance that is used to improve said switched-capacitor circuit, single-ended input signal is as the signal of said first driver element of input;
First sampling unit is used between the high period of first clock signal, the said single-ended input signal of sampling;
The first sampling integral unit that connects the inverting input of said operational amplifier; Be used between the high period of the 4th clock signal; The signal that said first driver element of sampling is in advance exported; And between the high period of second clock signal, jointly the signal through preparatory sampling of the said first sampling integral unit and the sampling of first sampling unit is carried out integration with the said first computing amplifying unit;
Second sampling unit is used between the high period of the 3rd clock signal, the said single-ended input signal of sampling;
The second sampling integral unit that connects the inverting input of said operational amplifier; Be used between the high period of said second clock signal; The signal that said first driver element of sampling is in advance exported; And between the high period of the 4th clock signal, jointly the sampling capacitance through preparatory sampling of the said second sampling integral unit and the sampling of second sampling unit is carried out integration with the said first computing amplifying unit;
Said the 4th clock signal, the 3rd clock signal, second clock signal are all identical with the cycle of first clock signal, and between the high period of said first clock signal, between the high period of said second clock signal, in a clock cycle, alternately occur in order between the high period of said the 3rd clock signal and between the high period of said the 4th clock signal.
Another purpose of the embodiment of the invention is to provide a kind of analog to digital converter, comprises as stated a switched-capacitor circuit.
Another purpose of the embodiment of the invention is to provide a kind of switched-capacitor circuit, and said circuit comprises:
The second computing amplifying unit; Comprise an operational amplifier, integrating capacitor C5 and integrating capacitor C6; The positive output end of said operational amplifier connects the inverting input of said operational amplifier through integrating capacitor C6, and the negative output terminal of said operational amplifier connects the in-phase output end of said operational amplifier through integrating capacitor C5;
First driver element is used to improve this switched-capacitor circuit input impedance, and the negative terminal signal of fully differential signal is as the signal of said first driver element of input;
First sampling unit is used between the high period of first clock signal, the negative terminal signal of the said fully differential signal of sampling;
The first sampling integral unit that connects the inverting input of said operational amplifier; Be used between the high period of the 3rd clock signal; The signal that said first driver element of sampling is in advance exported; And between the high period of second clock signal, jointly the signal through preparatory sampling of the said first sampling integral unit and the sampling of first sampling unit is carried out integration with the said second computing amplifying unit;
Second driver element is used to improve this switched-capacitor circuit input impedance, and the positive end signal of fully differential signal is as the signal of said second driver element of input;
The 3rd sampling unit is used between the high period of first clock signal, the positive end signal of the said fully differential signal of sampling
The 3rd sampling integral unit that connects the in-phase input end of said operational amplifier; Be used between the high period of said the 3rd clock signal; The signal that said second driver element of sampling is in advance exported; And between the high period of said second clock signal, jointly the signal through preparatory sampling of said the 3rd sampling integral unit and the sampling of the 3rd sampling unit is carried out integration with the said second computing amplifying unit;
Said the 3rd clock signal, second clock signal are identical with the cycle of first clock signal, and between the high period of said first clock signal, in a clock cycle, alternately occur in order between the high period of said second clock signal and between the high period of said the 3rd clock signal.
Another purpose of the embodiment of the invention is to provide a kind of analog to digital converter, comprises as stated a switched-capacitor circuit.
Another purpose of the embodiment of the invention is to provide a kind of switched-capacitor circuit, and said circuit comprises:
The second computing amplifying unit; Comprise an operational amplifier, integrating capacitor C5 and integrating capacitor C6; The positive output end of said operational amplifier connects the inverting input of said operational amplifier through integrating capacitor C6, and the negative output terminal of said operational amplifier connects the in-phase output end of said operational amplifier through integrating capacitor C5;
First driver element is used to improve said switched-capacitor circuit input impedance, and the negative terminal signal of fully differential signal is as the signal of said first driver element of input;
First sampling unit is used between the high period of first clock signal, the negative terminal signal of full-difference sampling signal;
The first sampling integral unit that connects the inverting input of said operational amplifier; Be used between the high period of the 4th clock signal; The signal that said first driver element of sampling is in advance exported; And between the high period of second clock signal, jointly the signal through preparatory sampling of the said first sampling integral unit and the sampling of first sampling unit is carried out integration with the said second computing amplifying unit;
Second sampling unit is used between the high period of the 3rd clock signal, the negative terminal signal of the said fully differential signal of sampling;
The second sampling integral unit; Be used between the high period of said second clock signal; The signal that said first driver element of sampling is in advance exported; And between the high period of said the 4th clock signal, jointly the signal through preparatory sampling of the said second sampling integral unit and the sampling of second sampling unit is carried out integration with the said second computing amplifying unit;
The 3rd sampling unit is used between the high period of said first clock signal, the positive end signal of the said fully differential signal of sampling;
The 3rd sampling integral unit; Be used between the high period of said the 4th clock signal; The signal that said second driver element of sampling is in advance exported; And between the high period of said second clock signal, jointly the signal through preparatory sampling of said the 3rd sampling integral unit and the sampling of the 3rd sampling unit is carried out integration with the said second computing amplifying unit;
The 4th sampling unit is used between the high period of said the 3rd clock signal, the positive end signal of the said fully differential signal of sampling;
The 4th sampling integral unit; Be used between the high period of said second clock signal; The signal that said second driver element of sampling is in advance exported; And between the high period of said the 4th clock signal, jointly the signal through said the 4th preparatory sampling of sampling integral unit and the sampling of said the 4th sampling unit is carried out integration with the said second computing amplifying unit;
Said the 4th clock signal, the 3rd clock signal, second clock signal are identical with the cycle of first clock signal; Duty ratio can be adjusted according to the requirement that signal is set up, and between the high period of said first clock signal, between the high period of said second clock signal, in a clock cycle, alternately occur in order between the high period of said the 3rd clock signal and between the high period of said the 4th clock signal.
Another purpose of the embodiment of the invention is to provide a kind of analog to digital converter, comprises as stated a switched-capacitor circuit.
The switched-capacitor circuit that the embodiment of the invention provides is applicable to the sampling to fully differential signal and single-ended input signal; Adopted the two-stage sample circuit; Elder generation, input signal is sampled, and the signal that will pass through on the sampling capacitance behind the double sampling carries out integration after the signal of over-drive unit output is sampled input signal again; Thereby the level and smooth noise of being introduced by driver element on the sampling capacitance has improved effective accuracy.
Description of drawings
Fig. 1 is the theory diagram of the switched-capacitor circuit that provides of first embodiment of the invention;
Fig. 2 is the sequential chart of first clock signal in the first embodiment of the invention, second clock signal and the 3rd clock signal;
Fig. 3 is the circuit diagram of Fig. 1;
Fig. 4 is the theory diagram of the switched-capacitor circuit that provides of second embodiment of the invention;
Fig. 5 is the sequential chart of first clock signal in the second embodiment of the invention, second clock signal, the 3rd clock signal and the 4th clock signal;
Fig. 6 is the circuit diagram of Fig. 4;
Fig. 7 is the theory diagram of the switched-capacitor circuit that provides of third embodiment of the invention;
Fig. 8 is the circuit diagram of Fig. 7;
Fig. 9 is the principle assumption diagram of the switched-capacitor circuit that provides of fourth embodiment of the invention;
Figure 10 is the circuit diagram of Fig. 9.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only is used to explain the present invention, and be not used in qualification the present invention.
The switched-capacitor circuit that the embodiment of the invention provides has adopted the two-stage sample circuit; Earlier at input signal after the signal of over-drive unit output is sampled in advance; Again input signal is sampled, and the sampling capacitance that will pass through behind preparatory sampling, the sampling double sampling carries out integration output.
Fig. 1 is the theory diagram of the switched-capacitor circuit that provides of first embodiment of the invention, for the ease of explanation, only shows the part relevant with first embodiment of the invention.
This switched-capacitor circuit is applicable to the collection to single-ended input signal, comprising: the first computing amplifying unit 14; Single-ended input signal is used to improve this switched-capacitor circuit input impedance as first driver element, 11, the first driver elements 11 of input signal; The first sampling integral unit 12; Be used between the high period of the 3rd clock signal; The signal that first driver element 11 of sampling is in advance exported; And between the high period of second clock signal, jointly the signal through preparatory 12 samplings of the first sampling integral unit is carried out integration with the first computing amplifying unit 14.
In order to overcome in the prior art; Because the problem that the sampling effective accuracy that introducing caused of first driver element 11 reduces; In the first embodiment of the invention, this switched-capacitor circuit also comprises: first sampling unit 13 is used between the high period of first clock signal; The single-ended input signal of sampling; At this moment, the first sampling integral unit 12 and the first computing amplifying unit 14 specifically are between the high period of second clock signal, to carrying out integration through the signal that the first sampling integral unit 12 is sampled in advance and first sampling unit 13 is sampled.
This switched-capacitor circuit that first embodiment of the invention provides can carry out the double sampling process to single-ended input signal; For the first time for existing used to the signals sampling of single-ended input signal through 11 outputs of first driver element; This sampling process has improved the input impedance of signals collecting path; Having reduced the requirement of external signal input impedance, for the second time be that this sampling process is being carried out on for the first time preparatory sampling process basis to the sampling as the single-ended input signal of the input signal of first driver element 11; Play the effect that level and smooth sampling capacitance C1 goes up the noise of being introduced by first driver element 11, thereby improved effective accuracy.
Wherein, the 3rd clock signal, second clock signal are identical with the cycle of first clock signal, and duty ratio all can be adjusted according to the requirement that signal is set up; In this embodiment of the invention; The duty ratio of the 3rd clock signal, second clock signal and first clock signal is 1: 3, and between the high period of the 3rd clock signal, in a clock cycle, alternately occur in order between the high period of second clock signal and between the high period of first clock signal, its sequential chart is as shown in Figure 2; Wherein, Φ 1 is first clock signal, and Φ 2 is the second clock signal, and Φ 3 is the 3rd clock signal.
Fig. 3 shows the circuit of Fig. 1.
The first sampling integral unit 12 comprises: K switch 2, K switch 3, K switch 4, K switch 5 and sampling capacitance C1.Wherein, an end of K switch 2 connects the output of first driver element 11, and the other end of K switch 2 is through an end of sampling capacitance C1 connection K switch 3, and the other end of K switch 3 connects the inverting input of the first computing amplifying unit 14; The other end of K switch 2 connects common-mode voltage VCM through K switch 4 simultaneously, and an end of K switch 3 connects common-mode voltage VCM through K switch 5 simultaneously.K switch 2 is by the control of the 3rd clock signal, and K switch 5 is by the 3rd clock signal and the control of first clock signal; K switch 3 and K switch 4 are by the second clock signal controlling.
The first computing amplifying unit 14 comprises: operational amplifier OPA1 and integrating capacitor C2; Wherein, The inverting input of operational amplifier OPA1 connects the first sampling integral unit 12 as the inverting input of the first computing amplifying unit 14; The in-phase input end of operational amplifier OPA1 connects common-mode voltage VCM, and the output of operational amplifier OPA1 is through the inverting input of integrating capacitor C2 concatenation operation amplifier OPA1.
This switched-capacitor circuit is when work, and with reference to sequential chart as shown in Figure 2, between the high period of Φ 3, K switch 2 and K switch 5 closures, capacitor C 1 begin the signal of first driver element, 11 outputs is sampled; Between the high period of Φ 1, K switch 1 closure, capacitor C 1 begin single-ended input signal is sampled; Between the high period of Φ 2, the single-ended input signal after K switch 3 and K switch 4 closures, capacitor C 1 are sampled to it carries out integration output.
Fig. 4 is the theory diagram of the switched-capacitor circuit that provides of second embodiment of the invention, for the ease of explanation, only shows the part relevant with the embodiment of the invention.
This switched-capacitor circuit that second embodiment of the invention provides still is applicable to the collection to single-ended input signal; Specifically be on circuit structure; On the basis of first embodiment of the invention, increased by the second sampling integral unit 15 and second sampling unit 16, at this moment; Aforementioned the 3rd clock signal that is used to control the first sampling integral unit 12 is used to control second sampling unit 16, and introduce one be used to control the first sampling integral unit 12 the 4th clock signal.Particularly, first sampling unit 11 is used between the high period of first clock signal, the single-ended input signal of sampling; The first sampling integral unit 12 is used between the high period of the 4th clock signal; The signal that first driver element 11 of sampling is in advance exported; And between the high period of second clock signal, jointly the signal through 12 preparatory samplings of the first sampling integral unit and 13 samplings of first sampling unit is carried out integration with the first computing amplifying unit 14; Second sampling unit 16 is used between the high period of the 3rd clock signal, the single-ended input signal of first driver element 11 of sampling; The second sampling integral unit 15 is used between the high period of second clock signal; The signal that first driver element 11 of sampling is in advance exported; And between the high period of the 4th clock signal; Jointly the sampling capacitance through 15 preparatory samplings of the second sampling integral unit and 16 samplings of second sampling unit is carried out integration with the first computing amplifying unit 14, thereby improved sample rate further single-ended input signal.
Wherein, The 4th clock signal, the 3rd clock signal, second clock signal are identical with the cycle of first clock signal; Duty ratio can be adjusted according to the requirement that signal is set up, and in this embodiment of the invention, the duty ratio of the 4th clock signal, the 3rd clock signal, second clock signal and first clock signal is 1: 4; And between the high period of the 4th clock signal, between the high period of the 3rd clock signal, in a clock cycle, alternately occur in order between the high period of second clock signal and between the high period of first clock signal; Its sequential chart is as shown in Figure 5, and wherein, Φ 1 is first clock signal; Φ 2 is the second clock signal, and Φ 3 is that the 3rd clock signal, Φ 4 are the 4th clock signal.
Fig. 6 shows the circuit of Fig. 4.
The second sampling integral unit 15 comprises: K switch 7, K switch 8, K switch 9, K switch 10 and sampling capacitance C3.Wherein, an end of K switch 7 connects the output of first driver element 11, and the other end of K switch 7 is through an end of sampling capacitance C3 connection K switch 8, and the other end of K switch 8 connects the inverting input of the first computing amplifying unit 14; The other end of K switch 7 connects common-mode voltage VCM through K switch 9 simultaneously, and an end of K switch 8 connects common-mode voltage VCM through K switch 10 simultaneously.K switch 7 is by the second clock signal controlling, and K switch 10 is by second clock signal and the control of the 3rd clock signal; K switch 9 is controlled by the 4th clock signal with K switch 8.
This switched-capacitor circuit is in when work, and with reference to sequential chart as shown in Figure 5, between the high period of Φ 4, K switch 8, K9 are closed, and capacitor C 3 is carried out integration, and K switch 5, K2 are closed in addition, and capacitor C 1 is the signal of sampling first driver element 11 outputs in advance; Between the high period of Φ 1, K switch 1 and K switch 5 closures, 1 pair of single-ended input signal of capacitor C is sampled; Between the high period of Φ 2, K switch 7, K10 are closed, and capacitor C 3 is the signal of sampling first driver elements 11 outputs in advance, and K switch 3, K4 are closed in addition, and capacitor C 1 is carried out integration; Between the high period of Φ 3, K switch 6 and K switch 10 closures, 3 pairs of single-ended input signals of capacitor C are sampled.
Through the description of the course of work of Fig. 3 and Fig. 6 can be found out; The switched-capacitor circuit that first embodiment of the invention provides needs three high level lasting times; The high level lasting time that is Φ 3, Φ 1, Φ 2 can be accomplished a signal sampling integration to fortune; And the switched-capacitor circuit that second embodiment of the invention provides needs two high level lasting times, thereby has improved the sample rate to single-ended input signal.
Fig. 7 is the theory diagram of the switched-capacitor circuit that provides of third embodiment of the invention, for the ease of explanation, only shows the part relevant with the embodiment of the invention.
This switched-capacitor circuit that third embodiment of the invention provides is applicable to the collection to the fully differential signal; Specifically be on the basis of first embodiment of the invention; The first computing amplifying unit 14 is replaced with the second computing amplifying unit 20 with differential signal enlarging function; Increased the positive end signal of fully differential signal second driver element 17 and the 3rd sampling integral unit 18, in addition, can also increase by the 3rd sampling unit 19 as input signal.The input impedance that second driver element 17 wherein is used to improve this switched-capacitor circuit.
At this moment, the signal that first driver element 11 receives is not single-ended input signal, but the negative terminal signal of fully differential signal.The 3rd sampling unit 19 is used between the high period of first clock signal; The positive end signal of the fully differential signal of sampling input second driver element 17; The 3rd sampling integral unit 18 is used between the high period of the 3rd clock signal; The sample positive end signal of fully differential signal of second driver element 11 output, and between the high period of second clock signal, the positive end signal that the 3rd sampling integral unit 18 and the 3rd sampling unit 19 are sampled carries out exporting behind the integration; The function such as the first embodiment of the invention of the first sampling integral unit 12 and first sampling unit 13 are said; Different is; The first sampling integral unit 12 and first sampling unit 13 is sampled and the signal of Integral Processing is not single-ended input signal, but the negative terminal signal of fully differential signal.The second computing amplifying unit 20 is used for the positive end signal of the differential signal of the negative terminal signal of the differential signal of the first sampling integral unit, 12 outputs and 18 outputs of the 3rd sampling integral unit is amplified back output.
The switched-capacitor circuit that third embodiment of the invention provides can carry out the double sampling process to the negative terminal signal of fully differential input signal; Be the existing negative terminal signals sampling of having used for the first time to 11 outputs of first driver element; This sampling process has improved the input impedance of signals collecting path; Having reduced the requirement of external signal input impedance, is that this sampling process was carried out on the sampling process basis in the first time to the negative terminal signals sampling of the fully differential signal of importing first driver element 11 for the second time; Play the effect of the noise of introducing by first driver element 11 on the level and smooth sampling capacitance, thereby improved effective accuracy the fully differential signal sampling.When this switched-capacitor circuit also further includes the 3rd sampling unit 19, similar with negative terminal signals sampling principle to the fully differential signal, can further improve effective accuracy to the fully differential signal sampling.
Wherein, The 3rd clock signal, second clock signal are identical with the cycle of first clock signal; Duty ratio all can be adjusted according to the requirement that signal is set up, and in this embodiment of the invention, the duty ratio of the 3rd clock signal, second clock signal and first clock signal is 1: 3; And between the high period of the 3rd clock signal, in a clock cycle, alternately occur in order between the high period of second clock signal and between the high period of first clock signal, its sequential chart is as shown in Figure 2.
Fig. 8 shows the circuit of Fig. 7.
The 3rd sampling integral unit 18 comprises: K switch 12, K switch 13, K switch 14, K switch 15 and sampling capacitance C4.Wherein, an end of K switch 12 connects the output of second driver element 17, and the other end of K switch 12 is through an end of sampling capacitance C4 connection K switch 15, and the other end of K switch 15 connects the in-phase input end of the second computing amplifying unit 20; The other end of K switch 12 connects common-mode voltage VCM through K switch 13 simultaneously, and an end of K switch 15 connects common-mode voltage VCM through K switch 14 simultaneously.K switch 12 is by the control of the 3rd clock signal, and K switch 14 is by the 3rd clock signal and the control of first clock signal; K switch 13 and K switch 15 are by the second clock signal controlling.
The 3rd sampling unit 19 comprises: by the K switch 11 of first clock signal control.One end of K switch 11 connects the input of second driver element 17, and the other end of K switch 11 connects the other end of K switch 12.
The second computing amplifying unit 20 comprises: operational amplifier OPA2, integrating capacitor C5 and integrating capacitor C6.Wherein, The inverting input of operational amplifier OPA2 connects the first sampling integral unit 12 as the inverting input of the second computing amplifying unit 20; It specifically is the other end that connects K switch 3; The in-phase input end of operational amplifier OPA2 connects the 3rd sampling integral unit 18 as the in-phase input end of the second computing amplifying unit 20; The positive output end of operational amplifier OPA2 is through the inverting input of integrating capacitor C6 concatenation operation amplifier OPA2, and the negative output terminal of operational amplifier OPA2 is through the in-phase output end of integrating capacitor C5 concatenation operation amplifier OPA2.
This switched-capacitor circuit is when work; With reference to sequential chart as shown in Figure 2; Between the high period of Φ 3, K switch 2 and K switch 5 closures, capacitor C 1 begin the negative terminal signal of the fully differential signal of first driver element, 11 outputs is sampled; K switch 13 and K switch 14 closures, capacitor C 4 begin the positive end signal of the fully differential signal of second driver element, 17 outputs is sampled; Between the high period of Φ 1; K switch 1 closure; Capacitor C 1 begins the negative terminal signal of the fully differential signal of importing first driver element 11 is sampled, and K switch 11 closures, capacitor C 4 begin the positive end signal of the fully differential signal of importing second driver element 17 is sampled; Between the high period of Φ 2; K switch 3 and K switch 4 closures; The negative terminal signal of fully differential signal of capacitor C 1 after to its sampling carries out exporting to behind the integration inverting input of operational amplifier OPA2; The positive end signal of K switch 15 and K switch 13 closures, the capacitor C 4 fully differential signal after to its sampling carries out exporting to behind the integration in-phase input end of operational amplifier OPA2, is undertaken exporting after the processing and amplifying by the fully differential signal of operational amplifier OPA2 after to integration.
Fig. 9 is the principle assumption diagram of the switched-capacitor circuit that provides of fourth embodiment of the invention, for the ease of explanation, only shows the part relevant with the embodiment of the invention.
The switched-capacitor circuit that fourth embodiment of the invention provides still is applicable to the fully differential signals sampling.Specifically be on the basis of second embodiment of the invention; The first computing amplifying unit 14 is replaced with the second computing amplifying unit 20 with differential signal enlarging function; Increase the 4th clock signal of the first sampling integral unit 12, the 3rd sampling integral unit 18 and the 4th sampling integral unit 21; Compared to the switched-capacitor circuit that third embodiment of the invention provides, the switched-capacitor circuit that fourth embodiment of the invention provides is faster to fully differential signals sampling speed.
At this moment, first driver element 11 be not with single-ended input signal as input signal, but with the negative terminal signal of fully differential signal as input signal.Particularly, first sampling unit 12 is used between the high period of first clock signal, the negative terminal signal of full-difference sampling signal; The first sampling integral unit 12 is used between the high period of the 4th clock signal; The signal that first driver element 11 of sampling is in advance exported; And between the high period of second clock signal, jointly the signal through 12 preparatory samplings of the first sampling integral unit and 13 samplings of first sampling unit is carried out integration with the second computing amplifying unit 20; Second sampling unit 16 is used between the high period of the 3rd clock signal, the negative terminal signal of full-difference sampling signal; The second sampling integral unit 15 is used between the high period of second clock signal; The signal that first driver element 11 of sampling is in advance exported; And between the high period of the 4th clock signal, jointly the signal through 15 preparatory samplings of the second sampling integral unit and 16 samplings of second sampling unit is carried out integration with the second computing amplifying unit 20; The 3rd sampling unit 19 is used between the high period of first clock signal, the positive end signal of full-difference sampling signal; The 3rd sampling integral unit 18 is used between the high period of the 4th clock signal; The signal that second driver element 17 of sampling is in advance exported; And between the high period of second clock signal, jointly the signal through 18 preparatory samplings of the 3rd sampling integral unit and 19 samplings of the 3rd sampling unit is carried out integration with the second computing amplifying unit 20; The 4th sampling unit 22 is used between the high period of the 3rd clock signal, the positive end signal of full-difference sampling signal; The 4th sampling integral unit 21 is used between the high period of second clock signal; The signal that second driver element 17 of sampling is in advance exported; And between the high period of the 4th clock signal, jointly the signal through 21 preparatory samplings of the 4th sampling integral unit and 22 samplings of the 4th sampling unit is carried out integration with the second computing amplifying unit 20.
The function such as the second embodiment of the invention of the first sampling integral unit 12, first sampling unit 13, the second sampling integral unit 15 and second sampling unit 16 are said; The structure such as the third embodiment of the invention of the second computing amplifying unit 20 are said; Different is; The first sampling integral unit 12, first sampling unit 13, the second sampling integral unit 15 and second sampling unit 16 is sampled and the signal of Integral Processing is not single-ended input signal, but the negative terminal signal of fully differential signal.
Wherein, The 4th clock signal, the 3rd clock signal, second clock signal are identical with the cycle of first clock signal; Duty ratio is 1: 4; And between the high period of the 4th clock signal, between the high period of the 3rd clock signal, in a clock cycle, alternately occur in order between the high period of second clock signal and between the high period of first clock signal, its sequential chart is as shown in Figure 5.
Figure 10 shows the circuit of Fig. 9.
The 4th sampling integral unit 21 comprises: K switch 17, K switch 18, K switch 19, K switch 20 and sampling capacitance C7.Wherein, an end of K switch 17 connects the output of second driver element 17, and the other end of K switch 17 is through an end of sampling capacitance C7 connection K switch 18, and the other end of K switch 18 connects the in-phase input end of the second computing amplifying unit 20; The other end of K switch 17 connects common-mode voltage VCM through K switch 19 simultaneously, and an end of K switch 18 connects common-mode voltage VCM through K switch 20 simultaneously.K switch 17 is by the second clock signal controlling, and K switch 20 is by the 4th clock signal and second clock signal controlling; K switch 19 is controlled by the 3rd clock signal with K switch 18.
The 4th sampling unit 22 comprises: by the K switch 16 of the 4th clock signal control.One end of K switch 16 connects the input of second driver element 17, and the other end of K switch 16 connects the other end of K switch 17.
This switched-capacitor circuit is when work, with reference to sequential chart as shown in Figure 5.Between the high period of Φ 3; K switch 6 closures; Capacitor C 3 begins the negative terminal signal of the fully differential signal of importing first driver element 11 is sampled, and K switch 16 closures, capacitor C 7 begin the positive end signal of the fully differential signal of importing second driver element 11 is sampled; Between the high period of Φ 4; K switch 2 and K switch 5 closures; Capacitor C 1 begins the negative terminal signal of first driver element, 11 outputs is sampled, and while K switch 8 and K switch 9 closures, capacitor C 3 begin the negative terminal signal after its sampling is carried out exporting to operational amplifier OPA2 behind the integration; K switch 12 and K switch 14 closures; Capacitor C 4 begins the positive end signal of second driver element, 17 outputs is sampled, and K switch 19 and K switch 18 closures, capacitor C 7 begin the positive end signal after its sampling is carried out exporting to operational amplifier OPA2 behind the integration; Between the high period of Φ 1, K switch 1 closure, capacitor C 1 begin the negative terminal signal of importing first driver element 11 is sampled, and K switch 11 closures, capacitor C 4 begin the positive end signal of importing second driver element 11 is sampled; Between the high period of Φ 2; K switch 3 and K switch 4 closures, the capacitor C 1 negative terminal signal after to its sampling carries out exporting to behind the integration inverting input of operational amplifier OPA2, K switch 7 and K switch 10 closures; Capacitor C 3 begins the negative terminal signal of first driver element, 11 outputs is sampled; K switch 13 and K switch 15 closures, the capacitor C 4 positive end signal after to its sampling carries out exporting to behind the integration in-phase input end of operational amplifier OPA2, K switch 17 and K switch 20 closures; Capacitor C 7 begins the positive end signal of second driver element 17 output is sampled, and the differential signal of operational amplifier OPA2 after to integration carries out exporting after the processing and amplifying.
Through the description of the course of work of Fig. 3 and Fig. 6 can be found out; The switched-capacitor circuit that third embodiment of the invention provides needs three high level lasting times; The high level lasting time that is Φ 3, Φ 1, Φ 2 can be to sampled signal of operational amplifier OPA 2 outputs; And the switched-capacitor circuit that fourth embodiment of the invention provides needs two high level lasting times; High level lasting time like Φ 4, Φ 3 promptly can be exported a sampled signal to operational amplifier OPA2, thereby has improved the sample rate to single-ended input signal.
Those skilled in the art should understand; One or more in K switch 1, K switch 2, K switch 3, K switch 4, K switch 5, K switch 6, K switch 7, K switch 8, K switch 9, K switch 10, K switch 11, K switch 12, K switch 13, K switch 14, K switch 15, K switch 16, K switch 17, K switch 18, K switch 19 and the switch 20 are not limited to adopt the switching circuit shown in the diagram, can also be the existing circuit with switching function that is made up of one or more PMOS pipes, NMOS pipe, CMOS pipe etc.
The embodiment of the invention also provides a kind of analog to digital converter, comprises as stated a switched-capacitor circuit.
The switched-capacitor circuit that the embodiment of the invention provides is applicable to the sampling to fully differential signal and single-ended input signal; Adopted the two-stage sample circuit; After the signal of driver element output is sampled, the signal of input driver element is sampled, and the signal behind the double sampling is carried out integration output; Thereby the level and smooth noise of being introduced by driver element on the sampling capacitance has improved the effective accuracy to signal sampling.In addition; Increase another identical road sampling channel on the circuit structure; And the 4th clock signal of this passage of introducing control; Through controlling the conducting sequential of first clock signal, second clock signal, the 3rd clock signal and the 4th clock signal, can improve switched-capacitor circuit to signals sampling speed.
The above is merely preferred embodiment of the present invention, is not limited to the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1. a switched-capacitor circuit is characterized in that, said circuit comprises:
The first computing amplifying unit comprises an operational amplifier and integrating capacitor C2, and the in-phase input end of said operational amplifier connects common-mode voltage, and the output of said operational amplifier connects the inverting input of said operational amplifier through integrating capacitor C2;
First driver element, the input impedance that is used to improve said switched-capacitor circuit, single-ended input signal is as the signal of said first driver element of input;
First sampling unit is used between the high period of first clock signal, the said single-ended input signal of sampling;
The first sampling integral unit that connects the inverting input of said operational amplifier; Be used between the high period of the 3rd clock signal; The signal that said first driver element of sampling is in advance exported; And between the high period of second clock signal, jointly the signal through said first preparatory sampling of sampling integral unit and the sampling of said first sampling unit is carried out integration with the said first computing amplifying unit;
Said the 3rd clock signal, second clock signal are identical with the cycle of first clock signal, and between the high period of said first clock signal, in a clock cycle, alternately occur in order between the high period of said second clock signal and between the high period of said the 3rd clock signal.
2. switched-capacitor circuit as claimed in claim 1 is characterized in that, the said first sampling integral unit comprises: K switch 2, K switch 2, K switch 4, K switch 5 and sampling capacitance C1; One end of K switch 2 connects the output of said first driver element, and the other end of K switch 2 is through an end of sampling capacitance C1 connection K switch 3, and the other end of K switch 3 connects the said first computing amplifying unit; The other end of K switch 2 connects common-mode voltage through K switch 4 simultaneously, and an end of K switch 3 connects common-mode voltage through K switch 5 simultaneously; K switch 2 is controlled by said the 3rd clock signal, and K switch 5 is by said the 3rd clock signal and the control of said first clock signal; K switch 3 and K switch 4 are by said second clock signal controlling;
Said first sampling unit comprises: by the K switch 1 of said first clock signal control; One end of K switch 1 connects the input of said first driver element, and the other end of K switch 1 connects the other end of K switch 2.
3. an analog to digital converter comprises a switched-capacitor circuit, it is characterized in that, said switched-capacitor circuit adopts switched-capacitor circuit according to claim 1 or claim 2.
4. a switched-capacitor circuit is characterized in that, said circuit comprises:
The first computing amplifying unit comprises an operational amplifier and integrating capacitor C2, and the in-phase input end of said operational amplifier connects common-mode voltage, and the output of said operational amplifier connects the inverting input of said operational amplifier through integrating capacitor C2;
First driver element, the input impedance that is used to improve said switched-capacitor circuit, single-ended input signal is as the signal of said first driver element of input;
First sampling unit is used between the high period of first clock signal, the said single-ended input signal of sampling;
The first sampling integral unit that connects the inverting input of said operational amplifier; Be used between the high period of the 4th clock signal; The signal that said first driver element of sampling is in advance exported; And between the high period of second clock signal, jointly the signal through preparatory sampling of the said first sampling integral unit and the sampling of first sampling unit is carried out integration with the said first computing amplifying unit;
Second sampling unit is used between the high period of the 3rd clock signal, the said single-ended input signal of sampling;
The second sampling integral unit that connects the inverting input of said operational amplifier; Be used between the high period of said second clock signal; The signal that said first driver element of sampling is in advance exported; And between the high period of the 4th clock signal, jointly the sampling capacitance through preparatory sampling of the said second sampling integral unit and the sampling of second sampling unit is carried out integration with the said first computing amplifying unit;
Said the 4th clock signal, the 3rd clock signal, second clock signal are all identical with the cycle of first clock signal, and between the high period of said first clock signal, between the high period of said second clock signal, in a clock cycle, alternately occur in order between the high period of said the 3rd clock signal and between the high period of said the 4th clock signal.
5. switched-capacitor circuit as claimed in claim 4 is characterized in that: the said second sampling integral unit comprises: K switch 7, K switch 8, K switch 9, K switch 10 and sampling capacitance C3; One end of K switch 7 connects the output of said first driver element, and the other end of K switch 7 is through an end of sampling capacitance C3 connection K switch 8, and the other end of K switch 8 connects the inverting input of the said first computing amplifying unit; The other end of K switch 7 connects common-mode voltage through K switch 9 simultaneously, and an end of K switch 8 connects common-mode voltage through K switch 10 simultaneously; K switch 7 is by said second clock signal controlling, and K switch 10 is by said second clock signal and the control of said the 4th clock signal; K switch 9 is controlled by said the 3rd clock signal with K switch 8;
Said second sampling unit comprises: by the K switch 6 of said the 4th clock signal control; One end of K switch 6 connects the input of said first driver element, and the other end of K switch 1 connects the other end of K switch 7.
6. an analog to digital converter comprises a switched-capacitor circuit, it is characterized in that, said switched-capacitor circuit adopts like claim 4 or 5 described switched-capacitor circuits.
7. a switched-capacitor circuit is characterized in that, said circuit comprises:
The second computing amplifying unit; Comprise an operational amplifier, integrating capacitor C5 and integrating capacitor C6; The positive output end of said operational amplifier connects the inverting input of said operational amplifier through integrating capacitor C6, and the negative output terminal of said operational amplifier connects the in-phase output end of said operational amplifier through integrating capacitor C5;
First driver element is used to improve this switched-capacitor circuit input impedance, and the negative terminal signal of fully differential signal is as the signal of said first driver element of input;
First sampling unit is used between the high period of first clock signal, the negative terminal signal of the said fully differential signal of sampling;
The first sampling integral unit that connects the inverting input of said operational amplifier; Be used between the high period of the 3rd clock signal; The signal that said first driver element of sampling is in advance exported; And between the high period of second clock signal, jointly the signal through preparatory sampling of the said first sampling integral unit and the sampling of first sampling unit is carried out integration with the said second computing amplifying unit;
Second driver element is used to improve this switched-capacitor circuit input impedance, and the positive end signal of fully differential signal is as the signal of said second driver element of input;
The 3rd sampling unit is used between the high period of first clock signal, the positive end signal of the said fully differential signal of sampling
The 3rd sampling integral unit that connects the in-phase input end of said operational amplifier; Be used between the high period of said the 3rd clock signal; The signal that said second driver element of sampling is in advance exported; And between the high period of said second clock signal, jointly the signal through preparatory sampling of said the 3rd sampling integral unit and the sampling of the 3rd sampling unit is carried out integration with the said second computing amplifying unit;
Said the 3rd clock signal, second clock signal are identical with the cycle of first clock signal, and between the high period of said first clock signal, in a clock cycle, alternately occur in order between the high period of said second clock signal and between the high period of said the 3rd clock signal.
8. switched-capacitor circuit as claimed in claim 7 is characterized in that, said the 3rd sampling integral unit comprises: K switch 12, K switch 13, K switch 14, K switch 15 and sampling capacitance C4; One end of K switch 12 connects the output of said second driver element, and the other end of K switch 12 is through an end of sampling capacitance C4 connection K switch 15, and the other end of K switch 15 connects the in-phase input end of the said second computing amplifying unit; The other end of K switch 12 connects common-mode voltage through K switch 13 simultaneously, and an end of K switch 15 connects common-mode voltage through K switch 14 simultaneously; K switch 12 is controlled by said the 3rd clock signal, and K switch 14 is by said the 3rd clock signal and the control of first clock signal; K switch 13 and K switch 15 are by said second clock signal controlling;
Said the 3rd sampling unit comprises: by the K switch 11 of said first clock signal control; One end of K switch 11 connects the input of said second driver element, and the other end of K switch 11 connects the other end of K switch 12.
9. an analog to digital converter comprises a switched-capacitor circuit, it is characterized in that, said switched-capacitor circuit adopts like claim 7 or 8 described switched-capacitor circuits.
10. a switched-capacitor circuit is characterized in that, said circuit comprises:
The second computing amplifying unit; Comprise an operational amplifier, integrating capacitor C5 and integrating capacitor C6; The positive output end of said operational amplifier connects the inverting input of said operational amplifier through integrating capacitor C6, and the negative output terminal of said operational amplifier connects the in-phase output end of said operational amplifier through integrating capacitor C5;
First driver element is used to improve said switched-capacitor circuit input impedance, and the negative terminal signal of fully differential signal is as the signal of said first driver element of input;
First sampling unit is used between the high period of first clock signal, the negative terminal signal of full-difference sampling signal;
The first sampling integral unit that connects the inverting input of said operational amplifier; Be used between the high period of the 4th clock signal; The signal that said first driver element of sampling is in advance exported; And between the high period of second clock signal, jointly the signal through preparatory sampling of the said first sampling integral unit and the sampling of first sampling unit is carried out integration with the said second computing amplifying unit;
Second sampling unit is used between the high period of the 3rd clock signal, the negative terminal signal of the said fully differential signal of sampling;
The second sampling integral unit; Be used between the high period of said second clock signal; The signal that said first driver element of sampling is in advance exported; And between the high period of said the 4th clock signal, jointly the signal through preparatory sampling of the said second sampling integral unit and the sampling of second sampling unit is carried out integration with the said second computing amplifying unit;
The 3rd sampling unit is used between the high period of said first clock signal, the positive end signal of the said fully differential signal of sampling;
The 3rd sampling integral unit; Be used between the high period of said the 4th clock signal; The signal that said second driver element of sampling is in advance exported; And between the high period of said second clock signal, jointly the signal through preparatory sampling of said the 3rd sampling integral unit and the sampling of the 3rd sampling unit is carried out integration with the said second computing amplifying unit;
The 4th sampling unit is used between the high period of said the 3rd clock signal, the positive end signal of the said fully differential signal of sampling;
The 4th sampling integral unit; Be used between the high period of said second clock signal; The signal that said second driver element of sampling is in advance exported; And between the high period of said the 4th clock signal, jointly the signal through said the 4th preparatory sampling of sampling integral unit and the sampling of said the 4th sampling unit is carried out integration with the said second computing amplifying unit;
Said the 4th clock signal, the 3rd clock signal, second clock signal are identical with the cycle of first clock signal; Duty ratio can be adjusted according to the requirement that signal is set up, and between the high period of said first clock signal, between the high period of said second clock signal, in a clock cycle, alternately occur in order between the high period of said the 3rd clock signal and between the high period of said the 4th clock signal.
11. switched-capacitor circuit as claimed in claim 10 is characterized in that: said the 4th sampling integral unit comprises: K switch 17, K switch 18, K switch 19, K switch 20 and sampling capacitance C7; One end of K switch 17 connects the output of said second driver element, and the other end of K switch 17 is through an end of sampling capacitance C7 connection K switch 18, and the other end of K switch 18 connects the in-phase input end of the said second computing amplifying unit; The other end of K switch 17 connects common-mode voltage through K switch 19 simultaneously, and an end of K switch 18 connects common-mode voltage through K switch 20 simultaneously; K switch 17 is by said second clock signal controlling, and K switch 20 is by said the 4th clock signal and second clock signal controlling; K switch 19 is controlled by said the 3rd clock signal with K switch 18;
Said the 4th sampling unit comprises: by the K switch 16 of said the 4th clock signal control; One end of K switch 16 connects the input of said second driver element, and the other end of K switch 16 connects the other end of K switch 17.
12. an analog to digital converter comprises a switched-capacitor circuit, it is characterized in that, said switched-capacitor circuit adopts like claim 10 or 11 described switched-capacitor circuits.
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| CN102868408B (en) * | 2011-07-05 | 2015-05-20 | 北京立博信荣科技有限公司 | Integral analog-to-digital converter |
| CN102355250B (en) * | 2011-07-12 | 2013-04-10 | 深圳市芯海科技有限公司 | Integrator and switched-capacitor integrator circuit thereof |
| CN107332563A (en) * | 2017-05-31 | 2017-11-07 | 苏州真感微电子科技有限公司 | Reduce the circuit of switching capacity input current and the method for sampling of switching capacity |
| CN110113052B (en) | 2019-05-10 | 2022-03-22 | 深圳锐越微技术有限公司 | Preceding stage driving module of analog-to-digital converter and analog-to-digital conversion device |
| CN111169184B (en) * | 2020-02-19 | 2024-08-20 | 上海商米科技集团股份有限公司 | Sampling method and sampling device |
| CN111953323B (en) * | 2020-07-28 | 2022-05-31 | 北京中星微电子有限公司 | Circuit for signal acquisition |
| CN113794361B (en) * | 2021-08-31 | 2023-08-18 | 上海威固信息技术股份有限公司 | Input driving circuit with self-adaptive input high level |
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| JPH01205609A (en) * | 1988-02-10 | 1989-08-18 | Nec Corp | Balanced modulator |
| GB2256551B (en) * | 1991-06-06 | 1996-01-24 | Crystal Semiconductor Corp | Switched capacitor integrator with chopper stabilisation performed at the sampling rate |
| EP0862270A1 (en) * | 1997-02-28 | 1998-09-02 | STMicroelectronics S.r.l. | Staircase adaptive voltage generator circuit |
| JP3216604B2 (en) * | 1998-06-25 | 2001-10-09 | 日本電気株式会社 | Switched capacitor type D / A converter and display drive circuit |
| US6344767B1 (en) * | 2000-01-28 | 2002-02-05 | The Hong Kong University Of Science And Technology | Switched-opamp technique for low-voltage switched capacitor circuits |
| US7315200B2 (en) * | 2004-03-31 | 2008-01-01 | Silicon Labs Cp, Inc. | Gain control for delta sigma analog-to-digital converter |
| US7009373B1 (en) * | 2004-04-13 | 2006-03-07 | Analog Devices, Inc. | Switched capacitor bandgap reference circuit |
| EP1999758B1 (en) * | 2006-03-21 | 2012-01-04 | Cambridge Analog Technologies, Inc. | Offset cancellation for sampled-data circuits |
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Address after: 518000 Nanhai Avenue, Nanshan District, Shenzhen City, Guangdong Province, 1079 Garden City Digital Building, Block A, 901A Patentee after: Xinhai Science and Technology (Shenzhen) Co., Ltd. Address before: 508, room 4, 518057 Shenzhen Software Park, three road, Nanshan District hi tech, Guangdong, Shenzhen, China Patentee before: Xinhai Science and Technology Co., Ltd., Shenzhen City |