CN202168276U - Interconnectable inner-layer multilayer printed wiring board - Google Patents

Interconnectable inner-layer multilayer printed wiring board Download PDF

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Publication number
CN202168276U
CN202168276U CN2011202424645U CN201120242464U CN202168276U CN 202168276 U CN202168276 U CN 202168276U CN 2011202424645 U CN2011202424645 U CN 2011202424645U CN 201120242464 U CN201120242464 U CN 201120242464U CN 202168276 U CN202168276 U CN 202168276U
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CN
China
Prior art keywords
layer
circuit board
interconnection
multilayer circuit
millimeter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2011202424645U
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Chinese (zh)
Inventor
刘�东
姜雪飞
彭卫红
叶应才
高团芬
刘克敢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Suntak Multilayer PCB Co Ltd
Original Assignee
Shenzhen Suntak Multilayer PCB Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Suntak Multilayer PCB Co Ltd filed Critical Shenzhen Suntak Multilayer PCB Co Ltd
Priority to CN2011202424645U priority Critical patent/CN202168276U/en
Application granted granted Critical
Publication of CN202168276U publication Critical patent/CN202168276U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

The utility model relates to a multilayer printed wiring board, specifically relating to an interconnectable inner-layer multilayer printed wiring board. The utility model provides an interconnectable inner-layer multilayer printed wiring board comprising at least 24 layers of signal layers which are separated from each other and are laminatingly arranged, wherein the fourth signal layer to the ninth signal layer and the sixteenth signal layer to the seventeenth signal layer are interconnected with each other through buried holes. The interconnectable inner-layer multilayer printed wiring board provided by the utility model has the advantages of improving the signal transmission performance of the multilayer printed wiring board and having less distortion.

Description

But the multilayer circuit board of internal layer interconnection
Technical field
The utility model relates to multilayer circuit board, but relates in particular to a kind of multilayer circuit board of internal layer interconnection.
Background technology
PCB (Printed Circuit Board), Chinese is a printed circuit board, claims printed circuit board (PCB), printed substrate again, is the important electron parts, is the supporter of electronic devices and components, is the supplier that electronic devices and components are electrically connected.At present, the signal transmission characteristics of multilayer circuit board is poor now, and distortion is bigger.
Summary of the invention
In order to solve the problems of the prior art, but the utility model provides a kind of multilayer circuit board of internal layer interconnection.
But the utility model provides a kind of multilayer circuit board of internal layer interconnection, comprises at least 24 layers each other across the signals layer of insulating barrier and range upon range of setting, wherein, passes through the buried via hole interconnection between the 4th~9 layer signal layer and between the 16th~17 layer signal layer respectively.
As the further improvement of the utility model, the aperture of said buried via hole is 0.2~0.5 millimeter.
As the further improvement of the utility model, the gross thickness of said buried via hole is 0.4~0.6 millimeter.
As the further improvement of the utility model, interconnect through blind hole between the 1st~12 layer signal layer.
As the further improvement of the utility model, the aperture of said blind hole is 0.2~0.5 millimeter.
As the further improvement of the utility model, the gross thickness of said blind hole is 0.8~1.2 millimeter.
As the further improvement of the utility model, interconnect through blind hole between the 13rd~24 layer signal layer.
As the further improvement of the utility model, the aperture of said blind hole is 0.2~0.5 millimeter.
As the further improvement of the utility model, the gross thickness of said blind hole is 0.8~1.2 millimeter.
As the further improvement of the utility model, through the clear opening interconnection, the aperture of said clear opening is 0.2~0.5 millimeter between the 1st~24 layer signal layer, and the gross thickness of said clear opening is 1.8~2.5 millimeters.
The beneficial effect of the utility model is: through such scheme, improved the signal transmission characteristics of multilayer circuit board, distortion is less.
Description of drawings
But the decomposition texture sketch map of the multilayer circuit board of Fig. 1 to be the utility model a kind of internal layer interconnection.
Embodiment
Below in conjunction with description of drawings and embodiment the utility model is further specified.
Drawing reference numeral among Fig. 1 is: the 1st layer signal layer 1; The 2nd layer signal layer 2; The 3rd layer signal layer 3; The 4th layer signal layer 4; The 5th layer signal layer 5; The 6th layer signal layer 6; The 7th layer signal layer 7; The 8th layer signal layer 8; The 9th layer signal layer 9; The 10th layer signal layer 10; 11th layer signals layer 11; The 12nd layer signal layer 12; The 13rd layer signal layer 13; The 14th layer signal layer 14; The 15th layer signal layer 15; The 16th layer signal layer 16; The 17th layer signal layer 17; The 18th layer signal layer 18; The 19th layer signal layer 19; The 20th layer signal layer 20; The 21st layer signal layer 21; The 22nd layer signal layer 22; The 23rd layer signal layer 23; The 24th layer signal layer 24.
As shown in Figure 1, but the multilayer circuit board of a kind of internal layer interconnection comprises 24 layers each other across the signals layer of insulating barrier and range upon range of setting, is respectively the 1st layer signal layer 1 from top to bottom; The 2nd layer signal layer 2; The 3rd layer signal layer 3; The 4th layer signal layer 4; The 5th layer signal layer 5; The 6th layer signal layer 6; The 7th layer signal layer 7; The 8th layer signal layer 8; The 9th layer signal layer 9; The 10th layer signal layer 10; 11th layer signals layer 11; The 12nd layer signal layer 12; The 13rd layer signal layer 13; The 14th layer signal layer 14; The 15th layer signal layer 15; The 16th layer signal layer 16; The 17th layer signal layer 17; The 18th layer signal layer 18; The 19th layer signal layer 19; The 20th layer signal layer 20; The 21st layer signal layer 21; The 22nd layer signal layer 22; The 23rd layer signal layer 23; The 24th layer signal layer 24, wherein, the 4th~9 layer signal layer 4,5,6,7,8, between 9 and the 16th~17 layer signal layer 16, between 17 respectively through the buried via hole interconnection.
As shown in Figure 1, the aperture of said buried via hole is 0.2~0.5 millimeter.
As shown in Figure 1, the gross thickness of said buried via hole is 0.4~0.6 millimeter.
As shown in Figure 1, the 1st~12 layer signal layer 1,2,3,4,5,6,7,8,9,10,11, between 12 through the blind hole interconnection.
As shown in Figure 1, the aperture of said blind hole is 0.2~0.5 millimeter.
As shown in Figure 1, the gross thickness of said blind hole is 0.8~1.2 millimeter.
As shown in Figure 1, the 13rd~24 layer signal layer 13,14,15,16,17,18,19,20,21,22,23, between 24 through the blind hole interconnection.
As shown in Figure 1, the aperture of said blind hole is 0.2~0.5 millimeter.
As shown in Figure 1, the gross thickness of said blind hole is 0.8~1.2 millimeter.
As shown in Figure 1; The 1st~24 layer signal layer 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23, between 24 through the clear opening interconnection; The aperture of said clear opening is 0.2~0.5 millimeter, and the gross thickness of said clear opening is 1.8~2.5 millimeters.
But the multilayer circuit board of a kind of internal layer that the utility model provides interconnection has improved the signal transmission characteristics of multilayer circuit board, and distortion is less.
Above content is the further explain that combines concrete preferred implementation that the utility model is done, and can not assert that the practical implementation of the utility model is confined to these explanations.For the those of ordinary skill of technical field under the utility model, under the prerequisite that does not break away from the utility model design, can also make some simple deduction or replace, all should be regarded as belonging to the protection range of the utility model.

Claims (10)

1. but the multilayer circuit board of an internal layer interconnection is characterized in that: comprise 24 layers each other across the signals layer of insulating barrier and range upon range of setting, wherein, pass through the buried via hole interconnection between the 4th~9 layer signal layer and between the 16th~17 layer signal layer respectively at least.
2. but according to the multilayer circuit board of the said internal layer interconnection of claim 1, it is characterized in that: the aperture of said buried via hole is 0.2~0.5 millimeter.
3. but according to the multilayer circuit board of the said internal layer interconnection of claim 1, it is characterized in that: the gross thickness of said buried via hole is 0.4~0.6 millimeter.
4. but according to the multilayer circuit board of the said internal layer interconnection of claim 1, it is characterized in that: interconnect through blind hole between the 1st~12 layer signal layer.
5. but according to the multilayer circuit board of the said internal layer interconnection of claim 4, it is characterized in that: the aperture of said blind hole is 0.2~0.5 millimeter.
6. but according to the multilayer circuit board of the said internal layer interconnection of claim 4, it is characterized in that: the gross thickness of said blind hole is 0.8~1.2 millimeter.
7. but according to the multilayer circuit board of the said internal layer interconnection of claim 1, it is characterized in that: interconnect through blind hole between the 13rd~24 layer signal layer.
8. but according to the multilayer circuit board of the said internal layer interconnection of claim 7, it is characterized in that: the aperture of said blind hole is 0.2~0.5 millimeter.
9. but according to the multilayer circuit board of the said internal layer interconnection of claim 7, it is characterized in that: the gross thickness of said blind hole is 0.8~1.2 millimeter.
10. but according to the multilayer circuit board of the said internal layer interconnection of claim 1, it is characterized in that: through the clear opening interconnection, the aperture of said clear opening is 0.2~0.5 millimeter between the 1st~24 layer signal layer, and the gross thickness of said clear opening is 1.8~2.5 millimeters.
CN2011202424645U 2011-07-11 2011-07-11 Interconnectable inner-layer multilayer printed wiring board Expired - Fee Related CN202168276U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011202424645U CN202168276U (en) 2011-07-11 2011-07-11 Interconnectable inner-layer multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011202424645U CN202168276U (en) 2011-07-11 2011-07-11 Interconnectable inner-layer multilayer printed wiring board

Publications (1)

Publication Number Publication Date
CN202168276U true CN202168276U (en) 2012-03-14

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011202424645U Expired - Fee Related CN202168276U (en) 2011-07-11 2011-07-11 Interconnectable inner-layer multilayer printed wiring board

Country Status (1)

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CN (1) CN202168276U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9635794B2 (en) 2012-02-20 2017-04-25 Trw Automotive U.S. Llc Method and apparatus for attachment of integrated circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9635794B2 (en) 2012-02-20 2017-04-25 Trw Automotive U.S. Llc Method and apparatus for attachment of integrated circuits

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C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120314

Termination date: 20170711