CN202103042U - 带有整体隔离层的堆叠式数字和射频片上系统 - Google Patents

带有整体隔离层的堆叠式数字和射频片上系统 Download PDF

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CN202103042U
CN202103042U CN2011200608428U CN201120060842U CN202103042U CN 202103042 U CN202103042 U CN 202103042U CN 2011200608428 U CN2011200608428 U CN 2011200608428U CN 201120060842 U CN201120060842 U CN 201120060842U CN 202103042 U CN202103042 U CN 202103042U
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N·D·菲尔德曼
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Kai Yin Polytron Technologies Inc
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Abstract

一种带有整体隔离层的堆叠式数字和射频片上系统，包括：器件封装；第一集成电路(IC)，其被封装在所述器件封装中；和第二IC，其被封装在所述器件封装中并且被制造在多层互连电路上，所述多层互连电路包括用于互连所述第二IC的部件的多个互连层，其特征在于，所述多个互连层中的一个选定层被配置为用作用于减少所述第一IC和所述第二IC之间干扰的传导屏蔽。

Description

带有整体隔离层的堆叠式数字和射频片上系统
技术领域
本实用新型总体上涉及集成电路，具体地涉及用于减少多芯片器件封装中干扰的方法和器件。 
背景技术
射频(RF)通信器件(例如接收器和发送器)有时使用多裸片封装(multi-die packages)来实现，该多裸片封装又被称作多芯片封装(MCP)、多芯片模块(MCM)、封装内系统(SiP)或片上系统(SoC)。当多个裸片被封装在单个封装中时，从一个裸片发出的信号可以干扰另一个裸片的运行。 
已经提出了多种用于减少裸片间干扰的技术。例如，美国专利申请公开文本2008/0237825(其公开内容以参引方式纳入本文)描述了一种包括第一器件和第二器件的堆叠式集成电路封装。该第一器件上方形成有传导间隔结构，该传导间隔结构具有围绕传导元件的间隔填充物。该第二器件安装在该传导间隔结构上方。该第一器件、该第二器件和该传导间隔结构被封装起来。 
实用新型内容
本文中描述的本实用新型的一个实施方案提供了一种装置，包括： 
器件封装； 
第一集成电路(IC)，其被封装在所述器件封装中；以及 
第二IC，其被封装在所述器件封装中并且被制造在多层互连电路上，所述多层互连电路包括用于互连所述第二IC的部件的多个互连层，其特征在于，所述多个互连层中的一个选定层被配置为用作用于减少所述第一IC和所述第二IC之间干扰的传导屏蔽(conductive shield)。 
在一些实施方案中，所述选定层不被用于互连任何所述部件。在一个实施方案中，所述第一IC和所述第二IC中的一个包括数字IC， 并且所述第一IC和所述第二IC中的另一个包括射频IC(RFIC)。在这里所公开的一个实施方案中，所述第一IC和所述第二IC在所述器件封装中被堆叠成一个在另一个顶部。在另一个实施方案中，所述互连层--包括所述选定层--在所述多层互连电路的单个制造工艺(process)中联合形成。在一些实施方案中，所述单个制造工艺包括铜互连工艺。 
根据本实用新型的一个实施方案，还提供了一种用于制造片上系统(SoC)的方法，该方法包括： 
将第一集成电路(IC)封装在器件封装中；以及 
在所述器件封装中封装第二IC，所述第二IC被制造在多层互连电路上，所述多层互连电路包括用于互连所述第二IC的部件的多个互连层，其特征在于，所述多个互连层中的一个选定层被配置为用作用于减少所述第一IC和所述第二IC之间干扰的传导屏蔽。 
根据本实用新型的一个实施方案，还提供了一种用于接收的方法，包括： 
使用封装在器件封装中的射频集成电路(RFIC)接收射频(RF)信号； 
使用与所述RFIC一起封装在所述器件封装中的数字IC来处理所接收的信号， 
其中，所述RFIC和所述数字IC中的一个被制造在多层互连电路上，所述多层互连电路包括用于互连所述RFIC和所述数字IC中的一个的部件的多个互连层，并且其中，所述多个互连层中的一个选定层被配置为用作用于减少所述RFIC和所述数字IC之间干扰的传导屏蔽。 
在一些实施方案中，接收和处理所述信号包括接收和处理移动数字电视(MDTV)信号。在一些实施方案中，所述干扰包括在所述数字IC中产生的时钟信号泄漏到所述RFIC中。 
从本实用新型的实施方案的以下详细描述中，结合附图，将更充分地理解本实用新型。 
附图说明
图1是根据本实用新型的一个实施方案的片上系统(SoC)的示意性截面图； 
图2是根据本实用新型的一个实施方案的带有整体隔离层的数字芯片的示意性截面图； 
图3是根据本实用新型的一个实施方案的流程图，该流程图示意性地例示了制造SoC的方法。 
具体实施方式
综述 
当两个或更多个集成电路(IC)彼此紧密靠近地被封装在同一器件封装中时，在一个IC中产生的信号可以辐射并在另一个IC中导致干扰。例如，当接收器或发送器包括被封装在单个器件封装中的数字IC和射频IC(RFIC)时，在该数字IC中产生的信号可以在该RFIC中导致干扰，反之亦然。 
本文中描述的本实用新型的实施方案提供了用于减少被封装在同一封装中的多个IC之间的干扰的改进的方法和器件。在一些实施方案中，该封装中的多个IC中的至少一个被制造在一个多层衬底上，所述多层衬底包括用于互连IC部件的多个互连层。不过，该多层结构中的一层不被用于互连，而是作为减少进出该IC的信号辐射的导电屏蔽。该层(其通常接地)减少或消除了该IC和该封装中其他IC之间的干扰。 
尽管在原理上有可能通过在该封装中的多个IC之间插入各种金属隔离器(separator)来减少芯片间干扰，但是这种解决方案通常昂贵、制作复杂，并且可观地增大了封装尺寸。另一方面，这里所公开的技术使用金属化层来减少干扰，所述金属化层固有地作为所述多个IC中的一个IC的制作工艺的一部分而被制造。因此，使用这里所公开的技术的器件(例如接收器或发送器)尺寸小、成本低，并且容易制作和装配。 
由于这里所公开的屏蔽层是所述多个IC中的一个IC的整体部分，所以干扰抑制是可预测的、在变化的运行条件下稳定的、可重复的和 容易测试的。再者，由于这里所公开的屏蔽层更接近干扰信号的源头，所以可获得的干扰抑制高于外部隔离器的干扰抑制。 
系统描述 
图1是根据本实用新型的一个实施方案的多裸片片上系统(SoC)20的示意性截面图。SoC 20包括数字IC 24和RFIC 28，它们一个堆叠在另一个之上并封装在器件封装32中。该SoC还包括该数字IC和该RFIC之间的内部互连，以及到器件板(device pad)36的互连。在本实施例中，SoC 20包括移动数字电视(MDTV)接收器。在该实施方案中，RFIC 28接收RF MDTV信号，而数字IC 24处理所接收的信号。不过，在替代实施方案中，这里所公开的技术可以与各种其他类型的IC一同使用，并用在各种其他的SoC应用中。 
图1中示出的SoC构造是仅仅为了概念清晰的目的而选择的示例性构造。在替代实施方案中，可以使用任何其他合适的SoC构造。例如，该SoC可以仅包括数字IC、仅包括RFIC、包括多于两个的任何期望类型的IC，或者包括任何其他合适的一组IC。所述IC可以使用任何合适的结构和/或技术，而不必定以堆叠式构造，封装在封装32中。 
SoC 20中的IC 24和IC 28产生及使用各种信号，例如时钟信号、本地振荡(LO)信号或任何其他类型的信号。由于封装32中的IC彼此紧密靠近，所以在一个IC中产生的信号可以从该IC辐射并在另一个IC中导致干扰。例如，在数字IC 24中产生的时钟信号可以辐射并作为寄生信号(spurious signal)出现在RFIC 28中，从而降低接收器性能。这类干扰在处理弱RF信号的接收器中尤其有害，但在任何SoC中可能普遍成问题。 
使用整体隔离层减少芯片间信号干扰 
在一些实施方案中，SoC 20中的一个IC包括减少进出该IC的信号辐射的整体隔离层。在本文描述的实施方案中，该隔离层是数字IC24的一部分。不过，替代地，这类隔离层可以作为任何其他合适IC(例如RFIC 28)的一部分而被制造。 
图2是根据本实用新型的一个实施方案的数字IC 24的示意性截 面图。IC 24包括半导体衬底40，半导体衬底40包括该IC的各种电子部件(例如晶体管、二极管、电阻器、电容器和电感器)。IC 24包括用于互连所述各种IC部件的多层互连电路44。该多层互连电路包括多个印刷传导层48。所述互连层由介电层52彼此分开，以形成堆叠式多层结构，该结构使得期望的信号能够在所述IC部件之间通行。每个层48包括用于信号通行的合适的电路迹线(circuit trace)。使用传导通孔54来执行层之间的互连。 
在一些实施方案中，一个或多个钝化层60被应用到电路44。层60通常是玻璃基的(glass-based)。在一些实施方案中，电路44和层60之间保留了特定的气隙。 
可以使用各种材料和工艺来制造数字IC 24。在本实施例中，衬底40包括硅，但是可以替代地包括砷化镓(GaAs)。互连层48通常包括铜，但是可以替代地包括铝或任何其他导电金属层。介电层52通常包括二氧化硅(SiO2)，但是可以替代地包括任何其他合适材料。 
层48的层厚度通常为大约 
Figure BSA00000447372000051
层52的厚度通常为大约 
Figure BSA00000447372000052
并且衬底40的厚度通常为大约 
Figure BSA00000447372000053
典型的数字IC包括5到8个层48。在一个示例性实施方案中，数字IC 24的总厚度为大约12mil，尽管在替代实施方案中该总厚度可以有可观的不同。当这里所公开的技术被应用在RFIC中时，该半导体衬底可以包括硅，该互连层可以包括铜，并且该介电层可以包括SiO2。上文列出的材料和尺寸仅通过示例给出。在替代实施方案中，可以使用任何其他合适的材料和尺寸。 
在一些实施方案中，互连电路44的多层结构中的一层不被用于互连，并且不携带信号，而是被用于为IC 24屏蔽信号辐射。该整体屏蔽层和互连层48一起在电路44的同一制造工艺中被制造。在图2的实施例中，该内部屏蔽层被标记为56，并且位于电路44与层60的分界处。 
可以使用各种工艺来制造互连电路44的多层结构。在一些实施方案中，使用铜互连工艺(例如90nm铜工艺)联合制造互连层48和屏蔽层56。铜互连工艺例如在Jackson等人的“Processing andIntegration of Copper Interconnects，”Solid State Technology， Volume 41，No.3，1998，pages 49-59中描述，该文献以参引方式被纳入本文。替代地，可使用任何其他适合的制造工艺联合制造互连层48和屏蔽层56。 
在一些实施方案中，屏蔽层56包括基本覆盖电路44整个表面的导电材料，并且通常被连接到地。这样，层56减少或消除了进出IC 24的信号辐射。在替代实施方案中，层56中的导电材料没有覆盖整个表面，但是以有效减少信号辐射的足够密集的图案被布置。层56的特性(例如厚度和图案密度)，例如，可以取决于硅供应商的生产能力。层56的材料成分通常取决于电路44的总体制造工艺，这是因为层56与层48在同一工艺中被制造。 
图2中示出的IC 24的机械构造和电构造是示例性构造，其仅仅以示例的方式被选择。在替代实施方案中，可以使用任何其他合适的构造。 
图3是根据本实用新型的一个实施方案的流程图，该流程图示意性地例示了用于制造SoC 20的方法。该方法开始自在第一IC提供步骤70提供数字IC 24，数字IC 24的顶部互连层被用作整体屏蔽层。在第二IC提供步骤74提供RFIC 28。在封装步骤78，IC 24和IC 28被封装在器件封装32中。由于IC 24的层56提供的屏蔽，由IC 24和IC 28之间的信号辐射导致的干扰被有效地抑制。 
尽管本文描述的实施方案主要针对MDTV接收器，但是这里所公开的技术绝非限于MDTV，而是可以被用在任何其他合适的接收器中，例如用在蓝牙(BT)、无线局域网(WLAN，也被称作Wi-Fi)或WiMAX接收器中。再者，尽管本文描述的实施方案主要考虑在集成的接收器和发送器中减少干扰，但是本文描述的方法和系统也可以用于其它应用，例如，包括有噪声的数字裸片和灵敏的模拟裸片的其他器件。 
因此应理解，上述实施方案通过示例的形式被引用，并且本实用新型不限于上文中已经特别示出和描述的内容。相反，本实用新型的范围包括上文描述的各种特征的组合和子组合，以及本领域技术人员在阅读前述内容后会想到的、并且没有在现有技术中公开的变化和修改。 

Claims (6)

1.带有整体隔离层的堆叠式数字和射频片上系统，包括：
器件封装；
第一IC，其被封装在所述器件封装中；以及
第二IC，其被封装在所述器件封装中并且被制造在多层互连电路上，所述多层互连电路包括用于互连所述第二IC的部件的多个互连层，其特征在于，所述多个互连层中的一个选定层被配置为用作用于减少所述第一IC和所述第二IC之间干扰的传导屏蔽。
2.根据权利要求1所述的带有整体隔离层的堆叠式数字和射频片上系统，其特征在于，所述选定层不被用于互连任何所述部件。
3.根据权利要求1所述的带有整体隔离层的堆叠式数字和射频片上系统，其特征在于，所述第一IC和所述第二IC中的一个包括数字IC，并且所述第一IC和所述第二IC中的另一个包括RFIC。
4.根据权利要求1所述的带有整体隔离层的堆叠式数字和射频片上系统，其特征在于，所述第一IC和所述第二IC在所述器件封装中被堆叠成一个在另一个顶部。
5.根据权利要求1所述的带有整体隔离层的堆叠式数字和射频片上系统，其特征在于，所述互连层——包括所述选定层——在所述多层互连电路的单个制造工艺中联合形成。
6.根据权利要求5所述的带有整体隔离层的堆叠式数字和射频片上系统，其特征在于，所述单个制造工艺包括铜互连工艺。 
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US8134227B2 (en) 2007-03-30 2012-03-13 Stats Chippac Ltd. Stacked integrated circuit package system with conductive spacer
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