CN202041874U - No-resistance complementary metal oxide semiconductor (CMOS) voltage reference source - Google Patents

Abstract

The utility model discloses a no-resistance complementary metal oxide semiconductor (CMOS) voltage reference source, which specifically comprises a starting circuit, a biasing circuit, a no-resistance proportional to absolute temperature (PTAT) voltage generated circuit, a complementary to absolute temperature (CTAT) voltage generated circuit and a superposed output voltage circuit. The voltage reference source sums a first order positive temperature compensation voltage generated by the no-resistance PTAT voltage generated circuit and a first order negative temperature compensation voltage generated by the CTAT voltage generated circuit by proportion and outputs compensated zero-temperature voltage, thereby having good temperature stability and relatively high power supply rejection ratio, and being capable of being applied to various analog and digital and analog hybrid integrated circuits of various oscillators, phaselocked loops, data converters and the like.

Description

A kind of non-resistance cmos voltage reference source

Technical field

The utility model belongs to power technique fields, is specifically related to the design of a kind of voltage-reference (Voltage Reference).

Background technology

All need high-precision voltage-reference at simulation, digital-to-analogue mixing even totally digital circuit, as oscillator, phaselocked loop, data converter, flash memory control circuit etc.The stability of voltage-reference has directly determined the quality of circuit performance.The index of describing the voltage reference source stability mainly contains: Power Supply Rejection Ratio, temperature coefficient.In order to satisfy the requirement of circuit operate as normal under abominable external temperature environment, voltage reference must have very little temperature coefficient, promptly very high temperature stability.

The principle of work of tradition band-gap reference is to utilize thermal voltage VT with positive temperature coefficient (PTC) and the bipolar transistor base-emitter voltage V with negative temperature coefficient _BECancel out each other, i.e. V _REF=V _BE+ α V _T, realize reference voltage, wherein penalty coefficient α transfers resistance to obtain by repairing.But in the digital CMOS process of standard, silicide generally can be used for reducing the drift resistance of Si-gate and diffusion layer, so low resistance resistance can take very big area, and influenced by process deviation very big for resistance in addition.Non-resistance bandgap reference voltage source in the document " Buck A E; McDonald C L; Lewis H.et al.A CMOS bandgap reference withoutresistors.IEEE JOURNAL of Solid-State Circuits, 2002.37 (1): 81-83 " has well solved the problem of resistance.But, because VBE's is non-linear, only carrying out first compensation phase, the temperature coefficient of bandgap voltage reference is bigger, and the Power Supply Rejection Ratio of output reference voltage (PSRR, Power Supply RejectionRatio) is relatively poor.

The utility model content

The purpose of this utility model is in order to solve the big and relatively poor problem of Power Supply Rejection Ratio of existing non-resistance band gap reference temperature coefficient, to have proposed a kind of non-resistance cmos voltage reference source.

The technical solution of the utility model is: a kind of non-resistance cmos voltage reference source, comprise start-up circuit, biasing circuit, non-resistance PTAT voltage generation circuit, CTAT voltage generation circuit and stack output voltage circuit, described start-up circuit provides the startup bias voltage for voltage-reference, described biasing circuit provides current offset for voltage-reference, positive temperature-compensated voltage of single order that described stack output voltage circuit is produced non-resistance PTAT voltage generation circuit and CTAT voltage generation circuit and the single order negative temperature bucking voltage zero temperature voltage after the output compensation of suing for peace in proportion promptly obtains the reference voltage of voltage-reference.

Described non-resistance PTAT voltage generation circuit comprises PMOS pipe M1, M2, M3, M4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, NMOS pipe M5, M6 and PNP triode Q1, Q2,

Described CTAT voltage generation circuit comprises PMOS pipe MP1, MP2, MP3, MP4 and NMOS pipe MN1, MN2, MN3, MR,

Wherein, PMOS manages MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12 constitutes the cascode current mirror, PMOS manages MP5, MP7, MP9, the source electrode of MP11 is connected with external power supply, its grid is connected to the grid of CTAT voltage generation circuit PMOS pipe MP1 jointly, PMOS manages MP5, MP7, MP9, the grid of MP11 is connected to the grid of CTAT voltage generation circuit PMOS pipe MP2 jointly, the grid of PMOS pipe M1 and M2 is connected respectively to the drain electrode of emitter and PMOS pipe MP6 and the MP10 of PNP triode Q1 and Q2, the drain electrode of PMOS pipe M2 is connected to the grid of NMOS pipe M5, the grid of drain electrode and NMOS pipe M6, the grid of PMOS pipe M4 and drain electrode are connected to the drain electrode of NMOS pipe M6 as output node Y, the source electrode of PMOS pipe M1 and M2 connects the drain electrode of MP8, the source electrode of PMOS pipe M3 and M4 connects the drain electrode of MP12, the drain electrode of PMOS pipe M1, the drain electrode of PMOS pipe M3, NMOS pipe M5 and the source electrode of M6 and base stage and the collector common ground of PNP triode Q1 and Q2.

Wherein, PMOS pipe MP1, MP2, MP3, MP4 constitute the cascode current-mirror structure, the source electrode of MP1 and MP3 connects external power, NMOS pipe MN1, MN2, MN3, MR constitute the cascode current-mirror structure, the source ground of MN2 and MR, the drain electrode of PMOS pipe MP2 links to each other with drain electrode with the grid of NMOS pipe MN1, and the grid of PMOS pipe MP4 links to each other with the drain electrode of drain electrode with NMOS pipe MN3, the source electrode of NMOS pipe MN3 links to each other with the drain electrode of NMOS pipe MR, as nodes X.

The beneficial effects of the utility model: the utility model passes through non-resistance PTAT (Proporational To AbsoluteTemperature, be proportional to absolute temperature) voltage generation circuit and CTAT (Complementary To AbsoluteTemperature is inversely proportional to absolute temperature) the positive temperature-compensated voltage of single order that voltage generation circuit produced and the single order negative temperature bucking voltage zero temperature voltage after the output compensation of suing for peace in proportion.Because the threshold voltage V of metal-oxide-semiconductor _TnBecome once linear relationship with temperature, adopt V _TnAnd V _TCompensate mutually, i.e. V _REF=V _Tn+ α V _T, can obtain lower temperature coefficient.V _TnExtract circuit extraction and go out V _Tn, and bias current is provided for whole reference circuit, wherein current mirror adopts the cascode structure, helps to improve the PSRR of voltage-reference, has extraordinary Power Supply Rejection Ratio and low-down temperature coefficient.

Description of drawings

Fig. 1 is a non-resistance cmos voltage reference source structural representation of the present utility model.

Fig. 2 is a high-performance non-resistance cmos voltage reference source circuit schematic diagram of the present utility model.

Fig. 3 is the temperature characteristics figure of output voltage of the voltage-reference of the utility model embodiment.

Fig. 4 is the PSRR synoptic diagram of output voltage of voltage-reference of the voltage-reference of the utility model embodiment.

Embodiment

Below in conjunction with accompanying drawing and specific embodiment the utility model is further elaborated.

Non-resistance cmos voltage reference source structural representation of the present utility model comprises as shown in Figure 1: start-up circuit, biasing circuit, non-resistance PTAT voltage generation circuit, CTAT voltage generation circuit and stack output voltage circuit.Described start-up circuit provides the startup bias voltage for entire circuit, and after the entire circuit steady operation, start-up circuit quits work isolated with entire circuit; Described biasing circuit provides current offset for entire circuit, and wherein current mirror adopts the cascode structure, helps to improve the PSRR of voltage reference; Described non-resistance PTAT voltage generation circuit produces the positive temperature-compensated voltage of single order, and its temperature characteristics is a straight line; Described CTAT voltage generation circuit produces a single order negative temperature bucking voltage, and its temperature characteristics is a straight line; Positive temperature-compensated voltage of single order that described stack output voltage circuit is produced non-resistance PTAT voltage generation circuit and CTAT voltage generation circuit and the single order negative temperature bucking voltage zero temperature voltage after the output compensation of suing for peace in proportion promptly obtains the reference voltage of voltage-reference.

The physical circuit schematic diagram is shown in Figure 2, and non-resistance PTAT voltage generation circuit comprises PMOS pipe M1, M2, M3, M4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, NMOS pipe M5, M6 and PNP triode Q1, Q2; The CTAT voltage generation circuit comprises PMOS pipe MP1, MP2, MP3, MP4 and NMOS pipe MN1, MN2, MN3, MR.

Wherein, PMOS manages MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12 constitutes the cascode current mirror, PMOS manages MP5, MP7, MP9, the source electrode of MP11 is connected with external power supply VDD, its grid is connected to the grid of CTAT voltage generation circuit PMOS pipe MP1 jointly, PMOS manages MP5, MP7, MP9, the grid of MP11 is connected to the grid of CTAT voltage generation circuit PMOS pipe MP2 jointly, the grid of PMOS pipe M1 and M2 is connected respectively to the drain electrode of emitter and PMOS pipe MP6 and the MP10 of PNP triode Q1 and Q2, the drain electrode of PMOS pipe M2 is connected to the grid of NMOS pipe M5, the grid of drain electrode and NMOS pipe M6, the grid of PMOS pipe M4 and drain electrode are connected to the drain electrode of NMOS pipe M6 as output node Y, the source electrode of PMOS pipe M1 and M2 connects the drain electrode of MP8, the source electrode of PMOS pipe M3 and M4 connects the drain electrode of MP12, the drain electrode of PMOS pipe M1, the drain electrode of PMOS pipe M3, NMOS pipe M5 and the source electrode of M6 and base stage and the collector common ground VSS of PNP triode Q1 and Q2.

Wherein, PMOS pipe MP1, MP2, MP3, MP4 constitute the cascode current-mirror structure, the source electrode of MP1 and MP3 meets external power VDD, NMOS pipe MN1, MN2, MN3, MR constitute the cascode current-mirror structure, the source ground VSS of MN2 and MR, the drain electrode of PMOS pipe MP2 links to each other with drain electrode with the grid of NMOS pipe MN1, and the grid of PMOS pipe MP4 links to each other with the drain electrode of drain electrode with NMOS pipe MN3, the source electrode of NMOS pipe MN3 links to each other with the drain electrode of NMOS pipe MR, as nodes X.

Here, start-up circuit comprises PMOS pipe MSP1, MSP2, MSP3 and NMOS pipe MSN1, MSN2, the source ground of NMOS pipe MSN1, MSN2; The source electrode of PMOS pipe MSP1 connects external power supply VDD; PMOS pipe MSP1, MSP2, MSP3 serial connection; The grid of NMOS pipe MSN1 is connected with the grid of PMOS pipe MSP1, MSP2, MSP3, connects the drain electrode of CTAT voltage generation circuit NMOS pipe MN2 simultaneously; The drain electrode of NMOS pipe MSN1 is connected with the drain electrode of PMOS pipe MSP3, connects the grid of NMOS pipe MSN2 simultaneously; The drain electrode of NMOS pipe MSN2 is connected to the grid of the PMOS pipe MP2 in the CTAT voltage generation circuit.

Its effect of start-up circuit is to guarantee that circuit is operated in desired normal condition when powering on.The course of work is: when circuit working during at " zero " state, MN1 and MN2 grid voltage are low, through MSP1, and MSP2, the phase inverter that MSP3 and MSN1 form, be output as height, MSN2 opens, and the grid voltage of MP1 and MP3 is dragged down, pipe is opened, pour into electric current, MP2 and MP4 open, and the grid voltage of MN1 and MN2 is elevated.Because MP2 and MP4 and MP13 and MP14 form current-mirror structure, MP13 and MP14 open, and VBIAS is elevated, the MR conducting, and bias current forms, and the working point is set up and is finished, and circuit begins operate as normal.At this moment, the grid voltage of MN1 and MN2 is 2V _GS, through phase inverter, output is high, and MSN2 turn-offs, and start-up circuit is not worked.In order to reduce the overturn point of phase inverter, reduce the quiescent dissipation of start-up circuit, increase the long L of grid of metal-oxide-semiconductor, the P pipe in the phase inverter adopts MSP1, MSP2 and MSP3 series connection.

Here, biasing circuit comprises that PMOS pipe MP13, MP14 and NMOS manage MB1, MB2, MR.PMOS pipe MP13 and MP14 respectively with the CTAT voltage generation circuit in PMOS pipe MP3 and the grid of MP4 be connected with drain electrode, the source electrode of PMOS pipe MP13 meets external power VDD, the drain electrode of PMOS pipe MP13 connects the source electrode of PMOS pipe MP14, the grid of NMOS pipe MB1 and drain electrode link to each other and meet PMOS simultaneously and manage the drain electrode of MP14 and the grid that NMOS manages MR, the grid of NMOS pipe MB2 links to each other with drain electrode and connects the source electrode of NMOS pipe MB1 simultaneously, the drain electrode of NMOS pipe MR connects the X point, the source ground VSS of NMOS pipe MB2 and MR.

Biasing circuit provides current offset for entire circuit, and wherein current mirror adopts the cascode structure, helps to improve the PSRR of voltage reference.The cascode current-mirror structure is the known technology general knowledge of this area, no longer is described in detail at this.

The bucking voltage of non-resistance PTAT voltage generation circuit output single order positive temperature coefficient (PTC).

From Fig. 2, can obtain: $V_{\mathrm{GS}2}-{\mathrm{<figure-callout\; id="1"\; label="V\; GS"\; filenames="HDA0000060377760000022.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{GS}}=V_{Q2}-{\mathrm{<figure-callout\; id="1"\; label="V\; Q"\; filenames="HDA0000060377760000022.png"\; state="\{\{state\}\}">V</figure-callout>}}_Q=V_T\ln \left(\frac{I_{\mathrm{QD}1}}{I_{\mathrm{QD}2}}\frac{I_{\mathrm{QS}2}}{I_{\mathrm{QS}1}}\right)=V_T\ln \left(\mathrm{mn}\right)$

Wherein, V _GS2, V _GS1The gate source voltage of representing PMOS pipe M2, M1 respectively, V _Q1, V _Q2The BE junction voltage of representing PNP triode Q1, Q2 respectively, I _QD1, I _QD2The collector current of representing PNP triode Q1, Q2 respectively, I _QS1, I _QS2The reverse saturation current of representing PNP triode Q1, Q2 respectively, n=A ₁/ A ₂, A1, A2 are respectively the emitter area of triode Q1 and Q2, and m is the ratio that flows through the electric current of triode Q2 and Q1.

Can obtain simultaneously: $V_{\mathrm{GS}2}-{\mathrm{<figure-callout\; id="1"\; label="V\; GS"\; filenames="HDA0000060377760000022.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{GS}}=\sqrt{\frac{{2I}_{\mathrm{DS}2}}{k_p{(W/L)}_2}}-\sqrt{\frac{{2\mathrm{<figure-callout\; id="1k"\; label="I\; DS"\; filenames="HDA0000060377760000022.png"\; state="\{\{state\}\}">I</figure-callout>}}_{\mathrm{DS}}}{k_p{(W/L)}_1}}---\left(1\right)$

$V_{\mathrm{GS}4}-{\mathrm{<figure-callout\; id="3"\; label="V\; GS"\; filenames="HDA0000060377760000021.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{GS}}=\sqrt{\frac{{2I}_{\mathrm{DS}4}}{k_p{(W/L)}_4}}-\sqrt{\frac{{2I}_{\mathrm{DS}3}}{k_p{(W/L)}_3}}---\left(2\right)$

Wherein, V _GS3, V _GS4The gate source voltage of representing PMOS pipe M3, M4 respectively, I _DS4, I _DS3The drain current of representing PMOS pipe M3, M4 respectively, k _p=μ _pC _Ox, μ _pBe carrier mobility, C _OxBe the gate oxide electric capacity of unit area.

If the breadth length ratio of NMOS pipe M5 is W ₅/ L ₅, the breadth length ratio of NMOS pipe M6 is the integral multiple of M5, is designated as G*W ₅/ L ₅, G is an integer here.Therefore I is arranged _DS4=GI _DS2

I again _DS2+ I _DS1=I _T, I _DS4+ I _DS3=GI _T, so I _DS3=GI _T-I _DS4=GI _T-GI _DS2=GI _DS1

In order better threshold voltage VT to be extracted, PMOS pipe M1, M2, M3 and M4 will keep a multiple relation.

The breadth length ratio of establishing PMOS pipe M3 here is W/L, and then the breadth length ratio of M1 and M4 is respectively A*W/L, B*W/L, and the breadth length ratio of M2 is AB*W/L; Here A, B are integer.Therefore then have

$V_{\mathrm{GS}4}-{\mathrm{<figure-callout\; id="3"\; label="V\; GS"\; filenames="HDA0000060377760000021.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{GS}}=\sqrt{\mathrm{AG}}(V_{\mathrm{GS}2}-V_{\mathrm{GS}1}).$

The bucking voltage of CTAT voltage generation circuit output single order negative temperature coefficient.

From Fig. 2, can obtain: $V_X=({\mathrm{<figure-callout\; id="1"\; label="V\; tn"\; filenames="HDA0000060377760000022.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{tn}}+\sqrt{\frac{{2I}_{\mathrm{DS}1}}{K_1}})+({\mathrm{<figure-callout\; id="3"\; label="V\; tn"\; filenames="HDA0000060377760000021.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{tn}}+\sqrt{\frac{{2I}_{\mathrm{DS}2}}{K_2}})-({\mathrm{<figure-callout\; id="3"\; label="V\; tn"\; filenames="HDA0000060377760000021.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{tn}}+\sqrt{\frac{{2I}_{\mathrm{DS}3}}{K_3}})$

Again because I _DS1=I _DS2=1/4I _DS3And K ₁=K ₂=K ₃, V then _X=V _Tn1+ V _Tn2-V _Tn3, ignore the influence that serves as a contrast inclined to one side effect, V _X=V _Tn, be used as CTAT voltage.

Here, stack output voltage circuit comprises PMOS pipe M3, M4 and NMOS pipe MR.PMOS manages M3, and M4 itself is the part of non-resistance PTAT voltage generation circuit, and also as the part of ratio summation output voltage circuit, the grid of PMOS pipe M3 connects the drain electrode of NMOS pipe MR simultaneously; Two PMOS pipe M3, the source electrode interconnection of M4, the grid of PMOS pipe M4 is as the output terminal of ratio summation output voltage circuit.

Two temperature-compensated voltages that stack output voltage circuit is used to superpose and is produced.According to the voltage superposition principle, output voltage can be expressed as:

Because V _TnBe subzero temperature voltage, and become once linear relationship, select proper A, B, G, m and n, V with temperature _TnAnd V _TTemperature coefficient cancel out each other, can obtain zero warm voltage.Those of ordinary skills can remove to select A, B, G according to actual conditions, and m and n here be not described in detail.

Fig. 3 is the output temperature family curve of voltage-reference.Based on standard CMOS process the voltage reference circuit that proposes is carried out simulating, verifying, obtain following experimental result: when supply voltage is 3.6V, in 0～100 ℃ of temperature range, output voltage average value is 884.9mV, change 1.2mV in the whole temperature range, promptly temperature coefficient is 13.6ppm.

Fig. 4 is the PSRR of the reference voltage of voltage-reference.Based on CMOS technology the voltage reference circuit that proposes is carried out simulating, verifying, obtain following experimental result: when supply voltage is 3.6V, the absolute value of output voltage Power Supply Rejection Ratio, during 1KHz, PSRR is 63dB, during 1MHz, PSRR is 24dB.

Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present utility model, should to be understood that protection domain of the present utility model is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from the utility model essence according to disclosed these technology enlightenments of the utility model, and these distortion and combination are still in protection domain of the present utility model.

Claims (4)

1. non-resistance cmos voltage reference source, comprise start-up circuit and biasing circuit, it is characterized in that, also comprise PTAT voltage generation circuit, CTAT voltage generation circuit and stack output voltage circuit, described start-up circuit provides the startup bias voltage for voltage-reference, described biasing circuit provides current offset for voltage-reference, positive temperature-compensated voltage of single order that described stack output voltage circuit is produced PTAT voltage generation circuit and CTAT voltage generation circuit and the single order negative temperature bucking voltage zero temperature voltage after the output compensation of suing for peace in proportion.

2. non-resistance cmos voltage reference source according to claim 1, it is characterized in that, described PTAT voltage generation circuit comprises PMOS pipe M1, M2, M3, M4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, NMOS pipe M5, M6 and PNP triode Q1, Q2

Described CTAT voltage generation circuit comprises PMOS pipe MP1, MP2, MP3, MP4 and four NMOS pipe MN1, MN2, MN3, MR,

Wherein, PMOS manages MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12 constitutes the cascode current mirror, PMOS manages MP5, MP7, MP9, the source electrode of MP11 is connected with external power supply, its grid is connected to the grid of CTAT voltage generation circuit PMOS pipe MP1 jointly, four PMOS pipe MP5, MP7, MP9, the grid of MP11 is connected to the grid of CTAT voltage generation circuit PMOS pipe MP2 jointly, the grid of PMOS pipe M1 and M2 is connected respectively to the drain electrode of emitter and PMOS pipe MP6 and the MP10 of PNP triode Q1 and Q2, the drain electrode of PMOS pipe M2 is connected to the grid of NMOS pipe M5, the grid of drain electrode and NMOS pipe M6, the grid of PMOS pipe M4 and drain electrode are connected to the drain electrode of NMOS pipe M6 as output node Y, the source electrode of PMOS pipe M1 and M2 connects the drain electrode of MP8, the source electrode of PMOS pipe M3 and M4 connects the drain electrode of MP12, the drain electrode of PMOS pipe M1, the drain electrode of PMOS pipe M3, NMOS pipe M5 and the source electrode of M6 and base stage and the collector common ground of PNP triode Q1 and Q2;

Wherein, PMOS pipe MP1, MP2, MP3, MP4 constitute the cascode current-mirror structure, the source electrode of MP1 and MP3 connects external power, NMOS pipe MN1, MN2, MN3, MR constitute the cascode current-mirror structure, the source ground of MN2 and MR, the drain electrode of PMOS pipe MP2 links to each other with drain electrode with the grid of NMOS pipe MN1, and the grid of PMOS pipe MP4 links to each other with the drain electrode of drain electrode with NMOS pipe MN3, the source electrode of NMOS pipe MN3 links to each other with the drain electrode of NMOS pipe MR, as nodes X.

3. non-resistance cmos voltage reference source according to claim 2 is characterized in that, described start-up circuit comprises PMOS pipe MSP1, MSP2, MSP3 and NMOS pipe MSN1, MSN2, the source ground of NMOS pipe MSN1, MSN2; The source electrode of PMOS pipe MSP1 connects external power supply; PMOS pipe MSP1, MSP2, MSP3 serial connection; The grid of NMOS pipe MSN1 is connected with the grid of PMOS pipe MSP1, MSP2, MSP3, connects the drain electrode of CTAT voltage generation circuit NMOS pipe MN2 simultaneously; The drain electrode of NMOS pipe MSN1 is connected with the drain electrode of PMOS pipe MSP3, connects the grid of NMOS pipe MSN2 simultaneously; The drain electrode of NMOS pipe MSN2 is connected to the grid of the PMOS pipe MP2 in the CTAT voltage generation circuit.

4. non-resistance cmos voltage reference source according to claim 2, it is characterized in that, described biasing circuit comprises PMOS pipe MP13, MP14 and NMOS pipe MB1, MB2, MR, PMOS pipe MP13 and MP14 respectively with described CTAT voltage generation circuit in PMOS pipe MP3 and the grid of MP4 be connected with drain electrode, the source electrode of PMOS pipe MP13 connects external power, the drain electrode of PMOS pipe MP13 connects the source electrode of PMOS pipe MP14, the grid of NMOS pipe MB1 and drain electrode link to each other and meet PMOS simultaneously and manage the drain electrode of MP14 and the grid that NMOS manages MR, the grid of NMOS pipe MB2 links to each other with drain electrode and connects the source electrode of NMOS pipe MB1 simultaneously, the drain electrode of NMOS pipe MR connects the X point, the source ground of NMOS pipe MB2 and MR.

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