CN201946585U - 一种半导体功率器件封装结构 - Google Patents

一种半导体功率器件封装结构 Download PDF

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CN201946585U
CN201946585U CN 201120016198 CN201120016198U CN201946585U CN 201946585 U CN201946585 U CN 201946585U CN 201120016198 CN201120016198 CN 201120016198 CN 201120016198 U CN201120016198 U CN 201120016198U CN 201946585 U CN201946585 U CN 201946585U
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power device
semiconductor power
chip
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utility
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赵亚俊
尹华
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Tongfu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

本实用新型涉及一种半导体功率器件封装结构，所述封装结构包括散热片、引线脚、芯片、装片胶、金属焊线和塑封料，所述散热片上设有芯片承载区，所述散热片为阶梯结构。与现有技术相比，本实用新型请求保护的一种半导体功率器件封装结构，在保证功率及散热效果的同时，进一步降低了材料成本又提高了产品的可靠性。

Description

一种半导体功率器件封装结构
技术领域
本实用新型涉及半导体技术，尤其涉及一种半导体功率器件封装结构。
背景技术
在传统的半导体封装中，芯片被胶固定在引线框架的载片台上，用金属焊线将芯片焊垫与引线框上的引线脚部位进行互联，然后用塑封料将芯片、载片台及引线脚部分包覆起来，达到保护芯片级内部电路的目的。
在一些大功率器件封装中，如图1所示，为了满足高功率、高散热的需求，载片台往往被设计成大片的金属片，既承载芯片又能实现散热片功能，但这种方式往往存在以下不足：
1、成本：功率器件封装用的引线框架一般比较大、厚，从而造成框架成本在整个封装成本中占据较高比例，而框架成本中主要是金属原材料的成本，随着有色金属资源的日益紧缺，金属原材料成本压力将日益升高。
2、可靠性：由于不同材质特别是铜、铁镍等金属与塑封料间的热膨胀差异，大片金属材料在封装结构中容易产生分层甚至剥离等可靠性问题。
实用新型内容
本实用新型解决的技术问题是：如何在保证功率和散热要求的前提下，提供一种低成本、高可靠性的半导体功率器件封装结构。
为解决上述技术问题，本实用新型提供一种半导体功率器件封装结构，包括散热片、引线脚、芯片、装片胶、金属焊线和塑封料，所述散热片上设有芯片承载区，所述散热片为阶梯结构。
可选地，所述散热片的阶梯至少有两层。
可选地，所述散热片的阶梯结构为Z型。
可选地，所述芯片承载区厚度高于散热片上的无芯片承载区域。
可选地，所述散热片上无芯片承载区域的厚度与所述引线脚的厚度相同。
与现有技术相比，本实用新型请求保护的一种半导体功率器件封装结构，散热片的阶梯状结构在确保了芯片承载区域的平整度、厚度，以及整体散热面积不变的同时，阶梯状设计节省了金属材料的消耗，既降低了成本，又降低了不同材质间的应力残留。
另外，Z型的阶梯结构大大增加了散热片与塑封料间的咬合强度，进一步提升了产品的可靠性。
附图说明
图1为现有的一种半导体功率器件封装结构的剖面示意图；
图2为本实用新型实施例中一种半导体功率器件封装结构的剖面示意图。
具体实施方式
在下面的描述中阐述了很多具体细节以便于充分理解本实用新型。但是本实用新型能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本实用新型内涵的情况下做类似推广，因此本实用新型不受下面公开的具体实施的限制。
其次，本实用新型利用示意图进行详细描述，在详述本实用新型实施例时，为便于说明，所述示意图只是实例，其在此不应限制本实用新型保护的范围。
下面结合附图对本实用新型的具体实施方式做详细的说明。
如图1所示，本实用新型提供的一种半导体功率器件封装结构，由散热片1、引线脚3、芯片5、装片胶4、金属焊线6和塑封料2组成，所述散热片1上设有芯片承载区7。所述散热片1为阶梯结构，可确保芯片承载区域7的平整度、厚度以及整体散热面积不变，同时，阶梯状设计节省了金属材料的消耗，既降低了成本，又减少了金属材料与塑封料2间因不同材质的热膨胀差异而带来的应力残留。
散热片1的阶梯至少有两层，当进行多芯片5封装时，可在不同的阶梯安装芯片5以避免同一水平面安装多颗芯片5时，由于芯片5间距离较近而导致装片胶4上溢沾污芯片5焊垫。当芯片5较厚时，可在低厚度区域安装芯片5以降低整个封装体的厚度。
散热片1的阶梯结构为Z型，尖角部位大大增加了散热片1与塑封料2间的咬合强度，进一步提升了产品的可靠性。
芯片承载区7厚度可高于散热片1上的无芯片承载区域，特别是对于一些高散热芯片5，较厚的芯片承载区7可以为芯片5提供足够的电容和热容以保护芯片5。
散热片1上无芯片承载区域的厚度与所述引线脚3的厚度相同，在一些结构简单的功率封装结构中，框架上除芯片承载区域7外，其它区域厚度保持一致可减少引线框架制作过程中的冲压次数以降低引线框架的工艺成本。
虽然本实用新型已以较佳实施例披露如上，但本实用新型并非限定于此。任何本领域技术人员，在不脱离本实用新型的精神和范围内，均可作各种更动与修改，因此本实用新型的保护范围应当以权利要求所限定的范围为准。

Claims (5)

1.一种半导体功率器件封装结构，所述封装结构包括散热片、引线脚、芯片、装片胶、金属焊线和塑封料，所述散热片上设有芯片承载区，其特征在于：所述散热片为阶梯结构。
2.如权利要求1所述的一种半导体功率器件封装结构，其特征在于：所述散热片的阶梯至少有两层。
3.如权利要求2所述的一种半导体功率器件封装结构，其特征在于：所述散热片的阶梯结构为Z型。
4.如权利要求1所述的一种半导体功率器件封装结构，其特征在于：所述芯片承载区厚度高于散热片上的无芯片承载区域。
5.如权利要求4所述的一种半导体功率器件封装结构，其特征在于：所述散热片上无芯片承载区域的厚度与所述引线脚的厚度相同。
CN 201120016198 2011-01-19 2011-01-19 一种半导体功率器件封装结构 Expired - Lifetime CN201946585U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103187383A (zh) * 2013-02-26 2013-07-03 山东迪一电子科技有限公司 一种肖特基二极管的封装结构
CN105227129A (zh) * 2015-09-22 2016-01-06 常州星海电子有限公司 高导热贴片旁路二极管

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103187383A (zh) * 2013-02-26 2013-07-03 山东迪一电子科技有限公司 一种肖特基二极管的封装结构
CN105227129A (zh) * 2015-09-22 2016-01-06 常州星海电子有限公司 高导热贴片旁路二极管
CN105227129B (zh) * 2015-09-22 2017-11-28 常州星海电子股份有限公司 高导热贴片旁路二极管

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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288

Patentee after: Tongfu Microelectronics Co., Ltd.

Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288

Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong

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