CN201876644U - Thin film transistor liquid crystal display panel and liquid crystal display - Google Patents
Thin film transistor liquid crystal display panel and liquid crystal display Download PDFInfo
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- CN201876644U CN201876644U CN2010206261943U CN201020626194U CN201876644U CN 201876644 U CN201876644 U CN 201876644U CN 2010206261943 U CN2010206261943 U CN 2010206261943U CN 201020626194 U CN201020626194 U CN 201020626194U CN 201876644 U CN201876644 U CN 201876644U
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Abstract
The embodiment of the utility model provides a thin film transistor liquid crystal display panel and a liquid crystal display, and relates to the field of thin film transistor liquid crystal displays (TFT LCD). By adopting the thin film transistor liquid crystal display panel, short circuit caused by electrostatic breakdown between a lead wire of a data wire or a lead wire of a grid line and a common electrode of a color film substrate can be avoided during technological process, so that the reduction of yield rate can be avoided. The thin film transistor liquid crystal display panel comprises an array substrate and the color film substrate which are jointed with each other through a frame sealing adhesive, wherein Au-Balls are doped in the frame sealing adhesive, and the Au-Balls positioned at the lead wire of the data wire and the lead wire of the grid line in the region of the frame sealing adhesive are insulated from a common electrode layer of the color film substrate. The embodiment of the utility model is used for manufacturing the thin film transistor liquid crystal display panel.
Description
Technical field
The utility model relates to Thin Film Transistor-LCD (TFT LCD) field, relates in particular to a kind of liquid crystal display panel of thin film transistor and LCD.
Background technology
At present in the TFT LCD large-scale production process, production, test and conveyance process all can be introduced static inevitably, friction can produce instantaneous kilovoltage with contacting, can produce the big electric current of about 20A, and glass substrate belongs to nonconductor, is unfavorable for the release of static, and electrostatic accumulation (ESC) and electrostatic discharge (ESD) process ratio are easier to cause the puncture of passivation layer (PVX), the direct damage that forms the short circuit of data line or grid line or cause part TFT, thus yields influenced.
In addition, in TFT LCD production process, in order to enhance productivity, a lot of products adopt the technology of Au-Ball (generally being at plastic material outer wrap nickel (Ni) and gold (Au) layer) in technological design, Au-Ball can replace traditional conductive silver glue technology, in conducting color membrane substrates public electrode and array base palte public electrode, reduce processing step, enhance productivity.But, form data line bright line or grid line bright line because the lip-deep public electrode of color membrane substrates (being generally the ITO material) passes through Au-Ball easy and data lead or grid line lead-in wire generation electrostatic breakdown phenomenon.Its basic reason is because the exterior static of introducing in technological process has punctured data cable lead wire or the passivation layer (PVX) above the grid line lead-in wire, causes data cable lead wire or grid line lead-in wire and color membrane substrates public electrode wire to pass through the Au-Ball conducting.
In the general technology process, Au-Ball directly is entrained in the envelope frame glue and is coated with, Au-Ball forms dispersed particle in envelope frame glue, be assembled in the box process at array base palte and color membrane substrates, the Au-Ball particle is squeezed, form the conducting effect by abundant contact color membrane substrates public electrode and array base palte public electrode, in this process, formed Au-Ball inevitably and contacted with the direct of PVX, run into static in the technological process and be easy to puncture the PVX layer at data cable lead wire or grid line lead-in wire zone.
Figure 1 shows that TFT LCD structure commonly used, comprise array base palte 1 and color membrane substrates 2, array base palte 1 and color membrane substrates 2 are fitted by envelope frame glue 3 (doping Au-Ball), between array base palte edge and color membrane substrates edge, a plurality of data cable lead wires zone 4 and a plurality of grid line lead-in wire zone 5 are arranged.Fig. 2 is the enlarged diagram in data cable lead wire zone 4 among Fig. 1.Fig. 3 be among Fig. 2 A-A to sectional view.In conjunction with Fig. 2, Fig. 3, the part that overlaps of the public electrode 14 on the data lead 7 on the array base palte 1 and the color membrane substrates 2 contact by the Au-Ball12 in the envelope frame glue 3, has only top 10 buffer actions of passivation layer of data lead 7 at this moment.Behind molding process, after Au-Ball 12 is squeezed, Au-Ball 14 fully contacts with passivation layer 10, and passivation layer 10 thickness that data lead 7 forms in array processes are about 0.3um, therefore under the electric field action between data-signal and the common electrode signal, mainly be under the highfield between Au-Ball and data lead or the grid line lead-in wire, cause the puncture of passivation layer 10 easily, and then formation color membrane substrates public electrode and overlapping partial data lead short circuit, cause demonstration bad, the electrostatic breakdown position is referring to shown in the position 13 of Fig. 3.
The utility model content
Embodiment of the present utility model provides a kind of liquid crystal display panel of thin film transistor and LCD, after can preventing to adopt the Au-Ball technology, in technological process, take place between the public electrode of data cable lead wire or grid line lead-in wire and color membrane substrates to cause the yields reduction because of electrostatic breakdown causes short circuit.
For achieving the above object, embodiment of the present utility model adopts following technical scheme:
A kind of liquid crystal display panel of thin film transistor, comprise array base palte and color membrane substrates, close with envelope frame sticker between described array base palte and the color membrane substrates, be doped with Au-Ball in the described envelope frame glue, be positioned at the data cable lead wire in envelope frame glue zone, the Au-Ball at grid line lead-in wire place and the common electrode layer insulation of described color membrane substrates.
On the described color membrane substrates, the common electrode layer that is positioned at corresponding described data cable lead wire, the grid line lead-in wire in described envelope frame glue zone is removed.
On the described color membrane substrates, be positioned on the common electrode layer of corresponding described data cable lead wire, grid line lead-in wire in described envelope frame glue zone and be formed with insulation course.
On the described color membrane substrates, be positioned on the common electrode layer of corresponding described data cable lead wire, grid line lead-in wire in described envelope frame glue zone and be formed with insulation course, and described common electrode layer and the disconnection of other regional common electrode layer.
On the described array base palte, the data cable lead wire, the grid line lead-in wire that are arranged in described envelope frame glue zone are electrically connected with the Au-Ball of described envelope frame glue.
On the described array base palte, the data cable lead wire, the grid line lead-in wire that are arranged in described envelope frame glue zone are electrically connected by the Au-Ball of conductive membrane layer with described envelope frame glue.
Described conductive membrane layer is the ITO layer.
Described insulation course is a resin bed.
The utility model embodiment also provides a kind of LCD, comprises above-mentioned liquid crystal display panel of thin film transistor.
Liquid crystal display panel of thin film transistor that the utility model embodiment provides and LCD, comprise array base palte and color membrane substrates, close with envelope frame sticker between array base palte and the color membrane substrates, be doped with Au-Ball in the envelope frame glue, be positioned at the data cable lead wire in envelope frame glue zone, the Au-Ball at grid line lead-in wire place and the common electrode layer insulation of color membrane substrates.Like this, because Au-Ball directly is electrically connected with data cable lead wire and grid line lead-in wire by conductive film, and again with the corresponding public electrode insulation of color membrane substrates, thereby can be not charged, effectively eliminated the condition that electrostatic discharge (ESD) takes place between Au-Ball and data cable lead wire and the grid line lead-in wire, thereby prevented the short circuit that electrostatic breakdown causes, improved yields.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the liquid crystal display panel of thin film transistor structural representation;
Fig. 2 is the enlarged diagram in data cable lead wire zone 4 among Fig. 1;
Fig. 3 is that the A-A of Fig. 2 is to sectional view;
The schematic cross-section in the data cable lead wire zone of the liquid crystal display panel of thin film transistor that Fig. 4 provides for the utility model embodiment;
Another schematic cross-section in the data cable lead wire zone of the liquid crystal display panel of thin film transistor that Fig. 5 provides for the utility model embodiment;
The another schematic cross-section in the data cable lead wire zone of the liquid crystal display panel of thin film transistor that Fig. 6 provides for the utility model embodiment;
The enlarged diagram in the data cable lead wire zone of the liquid crystal display panel of thin film transistor that Fig. 7 provides for the utility model embodiment;
Fig. 8 is that the B-B of Fig. 7 is to sectional view;
Fig. 9 is that the C-C of Fig. 7 is to sectional view;
Figure 10 is that another B-B of Fig. 7 is to sectional view;
Figure 11 is that another C-C of Fig. 7 is to sectional view;
Figure 12 is that the another B-B of Fig. 7 is to sectional view;
Figure 13 is that the another C-C of Fig. 7 is to sectional view.
Embodiment
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the utility model protection.
Embodiment one
The liquid crystal display panel of thin film transistor that the utility model embodiment one provides comprises array base palte and color membrane substrates, closes with envelope frame sticker between this array base palte and the color membrane substrates, wherein, is doped with Au-Ball in the envelope frame glue.
Be positioned at the data cable lead wire in envelope frame glue zone, the Au-Ball of grid line lead-in wire position and the common electrode layer insulation of color membrane substrates.
Concrete, the insulation of the common electrode layer of Au-Ball and color membrane substrates can be by with on the color membrane substrates, is positioned at the respective data lines lead-in wire in envelope frame glue zone, common electrode layer that grid line goes between and gets rid of realization.With the data cable lead wire zone is example, as shown in Figure 4, array base palte 1 part is same as the prior art, 2 of color membrane substrates have removed the respective data lines lead-in wire 7 in envelope frame glue zone 3 (among the figure only to data cable lead wire label wherein, all the other are not marked, and data cable lead wire 7 all refers to each bar data cable lead wire in the literary composition) common electrode layer.
Have, the insulation of the common electrode layer of Au-Ball and color membrane substrates can also be by on color membrane substrates again, is positioned to form on the common electrode layer of respective data lines lead-in wire, grid line lead-in wire in envelope frame glue zone that insulation course realizes.With the data cable lead wire zone is example, and as shown in Figure 5, array base palte 1 part is same as the prior art, is formed with insulation course 15 on the common electrode layer 14 of the respective data lines lead-in wire 7 that is positioned at envelope frame glue zone 3 of color membrane substrates 2, for example resin bed etc.
Further, as shown in Figure 6, the common electrode layer 14 of the respective data lines lead-in wire 7 that is positioned at envelope frame glue zone 3 of color membrane substrates 2 ' on form insulation course 15 after, again with the mode of cut etc. make with this part common electrode layer 14 ' with other regional common electrode layer 14 disconnections.The further like this insulation that has guaranteed Au-Ball 12 and common electrode layer 14.
The go between structure of the structure of this part and data cable lead wire of grid line is similar, repeats no more.
The liquid crystal display panel of thin film transistor that the utility model embodiment provides, comprise array base palte and color membrane substrates, close with envelope frame sticker between array base palte and the color membrane substrates, be doped with Au-Ball in the envelope frame glue, be positioned at the data cable lead wire in envelope frame glue zone, the Au-Ball at grid line lead-in wire place and the common electrode layer insulation of color membrane substrates.Like this, because Au-Ball directly is electrically connected with data cable lead wire and grid line lead-in wire by conductive film, and again with the corresponding public electrode insulation of color membrane substrates, thereby can be not charged, effectively eliminated the condition that electrostatic discharge (ESD) takes place between Au-Ball and data cable lead wire and the grid line lead-in wire, thereby prevented the short circuit that electrostatic breakdown causes, improved yields.
Embodiment two
The liquid crystal display panel of thin film transistor that the utility model embodiment two provides comprises array base palte and color membrane substrates, closes with envelope frame sticker between this array base palte and the color membrane substrates, wherein, is doped with Au-Ball in the envelope frame glue.
For color membrane substrates, the mode that forms insulation course or the common electrode layer of respective regions is got rid of on the respective data lines lead-in wire by being positioned at envelope frame glue zone at color membrane substrates and the common electrode layer of grid line lead-in wire realizes being positioned on the array base palte that the data cable lead wire in envelope frame glue zone, the Au-Ball of grid line lead-in wire position and the common electrode layer of color membrane substrates insulate.
For array base palte, can form with existing 4mask technology.Concrete:
On glass substrate, form first conductive film earlier, obtain comprising the figure of grid line, gate electrode and grid line lead-in wire by the composition PROCESS FOR TREATMENT.
On the substrate that forms above-mentioned figure, form after the gate insulation layer again, on gate insulation layer, form semiconductor layer film, doped semiconductor layer film and second conductive film, on second conductive film, apply photoresist, obtain the figure of active layer, data line, source electrode, drain electrode and data cable lead wire afterwards by the composition PROCESS FOR TREATMENT.This source electrode, drain electrode and active layer, gate electrode constitute thin film transistor (TFT).
Then, on data line, form passivation layer, and apply photoresist thereon, form via hole by composition technology.Here, when forming this drain electrode via hole, can etch away the passivation layer that is positioned at envelope frame glue zone of data cable lead wire top, make the data cable lead wire that is positioned at envelope frame glue zone expose, as shown in Figure 7 by this composition PROCESS FOR TREATMENT.
Fig. 7 is another enlarged diagram in data cable lead wire zone 4 among Fig. 1.In Fig. 7, etched away the passivation layer (not shown) that is positioned at envelope frame glue zone 3 of data cable lead wire 7 tops, obtained exposing the via hole 8 of this data cable lead wire 7.
Accordingly, when obtaining the data cable lead wire via hole, also need the passivation layer, the gate insulation layer that are positioned at envelope frame glue zone of grid line top are etched away, obtain exposing the via hole of grid line lead-in wire by this composition technology.
After obtaining the via hole that is positioned at envelope frame glue zone of data cable lead wire, grid line lead-in wire, via hole is not processed, so that the data cable lead wire or the grid line lead-in wire of the direct contacted hole site of Au-Ball of respective regions when becoming box are realized Au-Ball and being electrically connected that data cable lead wire or grid line go between.
In addition, after obtaining the via hole that is positioned at envelope frame glue zone of data cable lead wire, grid line lead-in wire, can also be in this via hole the coated with conductive film.Like this, on the one hand conductive film have electric conductivity can be so that lead-in wire and Au-Ball electrical connection; Conductive film can also be protected lead-in wire on the other hand, prevents that it from being corroded.
Because step after this is a deposition ITO layer on passivation layer, then the ITO layer can be coated to the via hole that is arranged in envelope frame glue zone of data cable lead wire, grid line lead-in wire, as conductive film.
Ready-made array base palte and color membrane substrates are fitted by envelope frame glue, are example with the data cable lead wire zone, utilize Fig. 8,9 to describe, wherein, Fig. 8 be the B-B of Fig. 7 to sectional view, Fig. 9 is that the C-C of Fig. 7 is to sectional view.
In Fig. 8, Fig. 9, the bottom is an array base palte, comprise glass substrate 1, data cable lead wire 7 (only to data cable lead wire label wherein, all the other are not marked among the figure, and context data line lead-in wire 7 all refers to each bar data cable lead wire) and the passivation layer 10 that is formed at data line and data cable lead wire top.By above-mentioned manufacturing process, the passivation layer that is positioned at envelope frame glue 3 zones of data cable lead wire 7 tops is etched away, and is filled with conductive membrane layer (ITO layer) 11.Fig. 8, Fig. 9 top are color membrane substrates 2.The common electrode layer 14 of the respective data lines lead-in wire 7 that is positioned at envelope frame glue 3 zones on this color membrane substrates 2 is removed.
After array base palte and color membrane substrates fitted by envelope frame glue 3, the Au-Ball 12 in the envelope frame glue 3 directly was electrically connected with data cable lead wire 7 by conductive membrane layer (ITO layer) 11.Because the common electrode layer 14 of relevant position has been removed on the color membrane substrates 2, then insulate by the common electrode layer 14 on conductive membrane layer (ITO layer) 11 Au-Ball that are electrically connected 12 and the color membrane substrates 2 with data cable lead wire 7.
The go between structure of the structure of this part and data cable lead wire of grid line is similar, repeats no more.
Like this, under the highfield between data-signal, grid line signal and the common electrode signal, owing to effectively eliminated the condition that electrostatic discharge (ESD) takes place between Au-Ball and data cable lead wire and the grid line lead-in wire, therefore, Au-Ball just can not puncture passivation layer, and then the lead-in wire of color membrane substrates public electrode and the part that overlaps short circuit can not occur yet, thereby improved yields.
Embodiment three
The liquid crystal display panel of thin film transistor that the utility model embodiment three provides comprises array base palte and color membrane substrates, closes with envelope frame sticker between this array base palte and the color membrane substrates, wherein, is doped with Au-Ball in the envelope frame glue.
At array base palte, its manufacturing process is identical with the foregoing description two, and the passivation layer that is positioned at envelope frame glue zone of data cable lead wire top is etched away, and is filled with the ITO layer; The passivation layer, the gate insulation layer that are positioned at envelope frame glue zone of grid line lead-in wire top are etched away, and are filled with the ITO layer.
At color membrane substrates, on the common electrode layer that the respective data lines lead-in wire that is positioned at envelope frame glue zone on the color membrane substrates and grid line go between, form a layer insulating again, for example resin bed etc.
As Figure 10, shown in Figure 11, wherein, Figure 10 be the B-B of Fig. 7 to sectional view, Figure 11 is that the C-C of Fig. 7 is to sectional view.
In Figure 10, Figure 11, the bottom is an array base palte, comprise glass substrate 1, data cable lead wire 7 (only to data cable lead wire label wherein, all the other are not marked among the figure, and context data line lead-in wire 7 all refers to each bar data cable lead wire) and the passivation layer 10 that is formed at data line and data cable lead wire top.By manufacturing process, the passivation layer that is positioned at envelope frame glue 3 zones of data cable lead wire 7 tops is etched away, and is filled with conductive membrane layer (ITO layer) 11.Figure 10, Figure 11 top are color membrane substrates 2.Be formed with insulation course 15 on the common electrode layer 14 of the respective data lines lead-in wire 7 that is positioned at envelope frame glue 3 zones on this color membrane substrates 2.This insulation course 15 can be the resin bed that applies.
After array base palte and color membrane substrates fitted by envelope frame glue 3, the Au-Ball 12 in the envelope frame glue 3 directly was electrically connected with data cable lead wire 7 by conductive membrane layer (ITO layer) 11.Owing to be formed with insulation course 15 on the common electrode layer 14 of relevant position on the color membrane substrates 2, then insulate by the common electrode layer 14 on conductive membrane layer (ITO layer) 11 Au-Ball that are electrically connected 12 and the color membrane substrates 2 with data cable lead wire 7.
The go between structure of the structure of this part and data cable lead wire of grid line is similar, repeats no more.
Like this, under the highfield between data-signal, grid line signal and the common electrode signal, owing to effectively eliminated the condition that electrostatic discharge (ESD) takes place between Au-Ball and data cable lead wire and the grid line lead-in wire, therefore, Au-Ball just can not puncture passivation layer, and then the lead-in wire of color membrane substrates public electrode and the part that overlaps short circuit can not occur yet, thereby improved yields.
Embodiment four
The liquid crystal display panel of thin film transistor that the utility model embodiment three provides comprises array base palte and color membrane substrates, closes with envelope frame sticker between this array base palte and the color membrane substrates, wherein, is doped with Au-Ball in the envelope frame glue.
The structure of array base palte and the foregoing description two, three are identical.The structure of color membrane substrates, slightly different with the foregoing description three, be on the common electrode layer of respective data lines lead-in wire that is positioned at envelope frame glue zone and grid line lead-in wire, form a layer insulating after, the mode with cut etc. makes this part common electrode layer and the disconnection of other regional common electrode layer again.
As shown in Figure 12 and Figure 13, wherein, Figure 12 be the B-B of Fig. 7 to sectional view, Figure 13 is that the C-C of Fig. 7 is to sectional view.
Figure 12, Figure 13 top are color membrane substrates 2.The respective data lines that being positioned at envelope frame glue 3 zones on this color membrane substrates 2 go between 7 common electrode layer 14 ' on be formed with insulation course 15.This insulation course 15 can be the resin bed that applies.And,, make the common electrode layer 14 of above-mentioned zone ' disconnect with other regional common electrode layer 14 with modes such as cuies.
After array base palte and color membrane substrates fitted by envelope frame glue 3, the Au-Ball 12 in the envelope frame glue 3 directly was electrically connected with data cable lead wire 7 by conductive membrane layer (ITO layer) 11.Because the common electrode layer 14 of relevant position on the color membrane substrates 2 ' on be formed with insulation course 15, and common electrode layer 14 ' disconnect with common electrode layer 14 then insulate by the common electrode layer 14 on conductive membrane layer (ITO layer) 11 Au-Ball that are electrically connected 12 and the color membrane substrates 2 with data cable lead wire 7.
The go between structure of this part of grid line is identical with the structure of data cable lead wire, repeats no more.
Like this, under the highfield between data-signal, grid line signal and the common electrode signal, owing to effectively eliminated the condition that electrostatic discharge (ESD) takes place between Au-Ball and data cable lead wire and the grid line lead-in wire, therefore, Au-Ball just can not puncture passivation layer, and then the lead-in wire of color membrane substrates public electrode and the part that overlaps short circuit can not occur yet, thereby improved yields.
Embodiment five
The LCD that the utility model embodiment provides, its panel adopts is the liquid crystal display panel of thin film transistor that any one provided among the foregoing description one, embodiment two, embodiment three, the embodiment four.The concrete structure of its panel all has explanation in the above-described embodiments, does not repeat them here.
Utilize the LCD of the liquid crystal display panel of thin film transistor that the utility model embodiment provides, the color membrane substrates public electrode short circuit can not occur with the lead-in wire of the part that overlaps, thereby has reduced the demonstration fraction defective.
The above; it only is embodiment of the present utility model; but protection domain of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the variation that can expect easily or replacement all should be encompassed within the protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion with the protection domain of described claim.
Claims (9)
1. liquid crystal display panel of thin film transistor, comprise array base palte and color membrane substrates, close with envelope frame sticker between described array base palte and the color membrane substrates, be doped with Au-Ball in the described envelope frame glue, it is characterized in that, be positioned at the data cable lead wire in envelope frame glue zone, the Au-Ball at grid line lead-in wire place and the common electrode layer insulation of described color membrane substrates.
2. liquid crystal display panel of thin film transistor according to claim 1 is characterized in that, on the described color membrane substrates, the common electrode layer that is positioned at corresponding described data cable lead wire, the grid line lead-in wire in described envelope frame glue zone is removed.
3. liquid crystal display panel of thin film transistor according to claim 1, its feature just in, on the described color membrane substrates, be positioned on the common electrode layer of corresponding described data cable lead wire, grid line lead-in wire in described envelope frame glue zone and be formed with insulation course.
4. liquid crystal display panel of thin film transistor according to claim 1, its feature just in, on the described color membrane substrates, be positioned on the common electrode layer of corresponding described data cable lead wire, grid line lead-in wire in described envelope frame glue zone and be formed with insulation course, and described common electrode layer and the disconnection of other regional common electrode layer.
5. according to claim 3 or 4 described liquid crystal display panel of thin film transistor, it is characterized in that described insulation course is a resin bed.
6. according to any one described liquid crystal display panel of thin film transistor of claim 1-4, it is characterized in that on the described array base palte, the data cable lead wire, the grid line lead-in wire that are arranged in described envelope frame glue zone are electrically connected with the Au-Ball of described envelope frame glue.
7. liquid crystal display panel of thin film transistor according to claim 6 is characterized in that, on the described array base palte, the data cable lead wire, the grid line lead-in wire that are arranged in described envelope frame glue zone are electrically connected by the Au-Ball of conductive membrane layer with described envelope frame glue.
8. liquid crystal display panel of thin film transistor according to claim 7 is characterized in that, described conductive membrane layer is the ITO layer.
9. a LCD is characterized in that, comprises the arbitrary described liquid crystal display panel of thin film transistor of claim 1-8.
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| CN2010206261943U CN201876644U (en) | 2010-11-23 | 2010-11-23 | Thin film transistor liquid crystal display panel and liquid crystal display |
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| CN2010206261943U CN201876644U (en) | 2010-11-23 | 2010-11-23 | Thin film transistor liquid crystal display panel and liquid crystal display |
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| CN106200153A (en) * | 2016-08-30 | 2016-12-07 | 京东方科技集团股份有限公司 | A kind of liquid crystal indicator |
| CN108196409A (en) * | 2018-01-02 | 2018-06-22 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel, display device and production method |
| CN108196409B (en) * | 2018-01-02 | 2022-01-28 | 京东方科技集团股份有限公司 | Array substrate, display panel, display device and manufacturing method |
| CN111176027A (en) * | 2020-02-20 | 2020-05-19 | Tcl华星光电技术有限公司 | Liquid crystal display panel and preparation method thereof |
| WO2021164059A1 (en) * | 2020-02-20 | 2021-08-26 | Tcl华星光电技术有限公司 | Liquid crystal display panel and preparation method therefor |
| CN112859455A (en) * | 2021-03-03 | 2021-05-28 | Tcl华星光电技术有限公司 | Display panel and display device |
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