CN203733797U - Array substrate and display apparatus - Google Patents
Array substrate and display apparatus Download PDFInfo
- Publication number
- CN203733797U CN203733797U CN201420130961.XU CN201420130961U CN203733797U CN 203733797 U CN203733797 U CN 203733797U CN 201420130961 U CN201420130961 U CN 201420130961U CN 203733797 U CN203733797 U CN 203733797U
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- signal line
- array base
- base palte
- collets
- secondary signal
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- 239000000758 substrate Substances 0.000 title abstract description 9
- 239000012212 insulator Substances 0.000 claims description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 15
- 230000001154 acute effect Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 4
- 230000010354 integration Effects 0.000 abstract 3
- 230000003068 static effect Effects 0.000 description 18
- 239000004484 Briquette Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 208000028659 discharge Diseases 0.000 description 8
- 238000000151 deposition Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Abstract
The utility model discloses an array substrate and a display apparatus. A first signal line located under a gate insulation layer is formed in a gate integration drive area of the array substrate; a second signal line overlapped with the first signal line is formed on the gate insulation layer; and the portion, where the second signal line fails to be formed, of the gate insulation layer in the gate integration drive area is provided with at least one insulation block. According to the array substrate and the display apparatus, ESD defect generated in the gate integration drive area in the manufacturing process of the array substrate can be reduced; and meanwhile, the antistatic capability of the display apparatus in the using process can be improved, and the product quality and qualified rate are improved.
Description
Technical field
The utility model relates to Display Technique field, relates in particular to a kind of array base palte and display unit.
Background technology
Liquid crystal indicator (LCD, Liquid Crystal Display) there is the advantages such as frivolous, low-power consumption and low heating, it is shown one's talent in numerous dissimilar display unit, be widely used in as on the modernization information equipments such as TV, computer, panel computer and mobile phone.
At present in order to reduce costs and adopt the design of narrow frame, conventionally adopt GOA(Gate Driver on Array, the integrated driving of array base palte grid) structure replaces the fixed grid-driving integrated circuit chip of panel foreign countries, directly gate driver circuit is produced on array base palte.But after adopting the design of GOA, there is the overlapping region of many cablings (as shown in Figure 1) at the periphery of array base palte, in the process of manufacture and follow-up use, very easily there is ESD(ElectroStatic Discharge at these overlapping positions, static discharge), in order to relax the angle of gradient of overlapping place metal level, conventionally retain amorphous silicon (a-Si) layer in overlapping region to relax the angle of gradient (as shown in Figure 2) of grid layer, to reduce the incidence of the overlapping ESD of place at present.
But after overlapping region retains amorphous silicon layer; conventionally can there is another kind of ESD in GOA region; after there is amorphous silicon layer etching in this ESD; before source-drain electrode (S/D) layer deposition; mainly occur in the overlapping place of amorphous silicon layer and grid layer; conventionally all can there is GI(gate insulating in the region that ESD occurs; gate insulator) layer destruction (as shown in Figure 3); thereby make after source-drain layer deposition; cause grid layer and source-drain electrode layer to be short-circuited (as shown in Figure 4); produce demonstration bad, affect the yield of product.By analysis, this is bad contacts certain causality with equipment, and ESD all occurs near the position of manipulator or equipment and substrate contacts conventionally.After substrate contacts with equipment, substrate surface can produce static, because the amorphous silico briquette of contact position isolates, it is more that isolated amorphous silico briquette produces static in the larger position of deformation, and the static producing is difficult for deriving, in the time that static reaches certain level, can there is ESD, destroy gate insulator, when after source-drain layer deposition, can produce ESD bad, affect product yield.
Utility model content
(1) technical problem that will solve
The purpose of this utility model is to reduce the static discharge incidence of the integrated drive area of array base palte grid upward wiring crossover position.
(2) technical scheme
For achieving the above object, according to one side of the present utility model, a kind of array base palte is provided, the integrated drive area of grid of described array base palte is formed with the first signal line being positioned under gate insulator, and on described gate insulator, be formed with the secondary signal line overlapping with described first signal line, the part that is not formed with secondary signal line on the described gate insulator of the integrated drive area of described grid is provided with at least one first collets.
Preferably, first signal line and the overlapping position of secondary signal line are provided with the second collets between secondary signal line and gate insulator.
Preferably, described the second collets are circular or oval.
Preferably, described the second collets are made up of amorphous silicon.
Preferably, described at least one first collets are made up of amorphous silicon.
Preferably, described at least one first collets comprise acute angle portion.
Preferably, the side of described at least one the first collets is with sawtooth.
Preferably, on described at least one first collets, be formed with conductive layer.
Preferably, described at least one first collets are arranged on around the position or described position contacting with external device on described array base palte.
According to a further aspect in the invention, provide a kind of display unit, comprised above-mentioned array base palte.
(3) beneficial effect
The utility model arranges collets by the non-cabling overlapping region of the integrated drive area of grid at array base palte, reduce the static discharge incidence of cabling crossover position, thereby it is bad to be reduced in the ESD that in array base palte process, the integrated drive area of grid produces, can also improve display unit antistatic effect in use, improve product quality and yield simultaneously.
Brief description of the drawings
Fig. 1 is the integrated drive area of the grid with amorphous silico briquette partial schematic diagram not on array base palte in prior art.
Fig. 2 is the integrated drive area of the grid with amorphous silico briquette partial schematic diagram on array base palte in prior art.
Fig. 3 is the floor map that in prior art, on array base palte, the integrated drive area of the grid with amorphous silico briquette discharges in an amorphous silico briquette place generation static after etching method for amorphous silicon layer and before sedimentary origin drain electrode layer.
Fig. 4 is the floor map of the integrated drive area of grid after sedimentary origin drain electrode layer forms secondary signal line on the array base palte in Fig. 3.
Fig. 5 is generalized section when static release occurs in static release place in Fig. 3.
Fig. 6 is that in Fig. 3, the generalized section after static discharges occurs in static release place.
Fig. 7 is that in Fig. 3, static release place static occurs discharges and forms secondary signal line generalized section afterwards.
Fig. 8 does not form secondary signal line partial schematic diagram before according to the integrated drive area of the grid of the array base palte of the utility model embodiment.
Fig. 9 forms secondary signal line partial schematic diagram afterwards according to the integrated drive area of the grid of the array base palte of the utility model embodiment sedimentary origin drain electrode layer.
Figure 10 is according to the shape schematic diagram of the second amorphous silico briquette of the utility model embodiment.
Figure 11 is according to the shape schematic diagram of the first amorphous silico briquette of the utility model embodiment.
Embodiment
Below in conjunction with drawings and Examples, execution mode of the present utility model is described in further detail.Following examples are only for the utility model is described, and can not be used for limiting scope of the present utility model.
For clearer explanation the technical solution of the utility model and advantage, first describe as the utility model and improve basic related art below.
Fig. 1 is the partial schematic diagram of the array base palte with amorphous silico briquette not in prior art, can see, first signal line 1 is connected by wire jumper 4 one by one with secondary signal line 2, and secondary signal line 2 is connected to the integrated grid of GOA(array base palte and drives) unit 3.In some positions, first signal line 1 and secondary signal line 2 occur overlapping.Note, first signal line 1 forms in the time forming the grid layer of array base palte, on it, also there is gate insulator, and secondary signal line 2 is formed on gate insulator, in the time forming the source-drain electrode layer of array base palte, form, just not shown gate insulator (Reference numeral is 7 in Fig. 5-7) in Fig. 1, therefore first signal line 1 and secondary signal line 2 are not communicated with at the overlapping place that there is no wire jumper 4.Generally speaking, first signal line 1, for receiving driving signal, sends GOA unit 3 to by secondary signal line 2, and GOA unit 3 drives the grid of each pixel cell (not shown) again.
Fig. 2 is the partial schematic diagram of the array base palte with amorphous silico briquette in prior art, is with the difference of Fig. 1, and first signal line 1 and secondary signal line 2 are not having the overlapping amorphous silico briquette 5 that is provided with between the two of wire jumper 4.
Amorphous silico briquette 5 is not depositing S/D(source-drain electrode) layer (secondary signal line 2 is also to form in the time forming source-drain electrode layer) formation before, once now there is the ESD as shown in Reference numeral 6 in Fig. 3 and Fig. 5, will destroy amorphous silico briquette 5 and gate insulator 7, form breach, as shown in Figure 6.
When deposition S/D layer and after forming secondary signal line 2 simultaneously, directly contact first signal line 1 at indentation, there secondary signal line 2, as shown in Figure 7, thereby form unnecessary electrical connection, ESD is bad, makes the product of producing occur quality defect.Fig. 4 shows the schematic diagram forming after secondary signal line 2.
General principle of the present utility model is that the region division that is not laid with secondary signal line on the gate insulator of the integrated drive area of grid of array base palte has the first collets, avoid ESD to occur in cabling overlapping region, thereby reduce the ESD bad incidence of array base palte in production and use procedure, improve product quality and yield.
Fig. 8 does not form secondary signal line 2 partial schematic diagram before according to the array base palte of the utility model embodiment.Difference with the prior art is, in Fig. 8, is not only formed with the second collets 5 at predetermined cabling overlapping region, and is also formed with the first collets 7 at predetermined non-cabling overlapping region.Certainly, in certain embodiments, also can not form the second collets 5.
The material of noting the second collets 5 and the first collets 7 can be the same or different, and is all preferably amorphous silicon, and this is in order to form the second collets 5 and the first collets 7 when the technique of existing formation amorphous silicon layer simultaneously, thus simplified manufacturing technique.
The first collets 7 in figure are all formed on the top of first signal line 1, in fact also can be formed on other positions, the utility model does not limit this, preferably the first collets 7 are arranged near position that the integrated drive area of grid contacts with external device or its, can avoid like this accumulation of static electricity to the second collets 5.
Note, in fact between the first collets 7 and the second collets 5 and first signal line 1, also have gate insulator, but do not illustrate in figure.
Fig. 9 forms secondary signal line 2 partial schematic diagram afterwards according to the integrated drive area of the grid of the array base palte of the utility model embodiment sedimentary origin drain electrode layer.Now on the second collets 5, there is secondary signal line 2 to pass through.
As shown in figure 10, the second collets 5 can be made square, are preferably circle or ellipse, can prevent like this ESD.Accordingly, as shown in figure 11, the first collets 7 also can be arranged to square, but preferably include acute angle portion, for example can be in its side with sawtooth, and make like this ESD more easily occur in the first collets 7 and do not occur in the second collets 5.Nearly (shown in Figure 11) of edge of the distance between two tips downside metal level (being first signal line 1) that makes sawtooth can be set, in the time of external device contact array substrate, laciniation generation distortion and static more easily concentrate on the tip of sawtooth, after static acquires a certain degree, there is ESD in sawtooth tip and downside metal level edge, thereby effectively discharge the static of amorphous silicon layer, although likely destroy gate insulator, but because this position does not exist secondary signal line 2, therefore can't cause unnecessary electrical connection and to produce ESD bad.
In the utility model embodiment, can also on the first collets 7, form conductive layer, conductive layer for example forms in the time forming source-drain electrode layer, makes so more easily on the first collets 7, ESD to occur.
The utility model embodiment also provides a kind of display unit, and it comprises above-mentioned array base palte.Display unit is for example: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
Prove effect of the present utility model below by experimental data.
Table 1 is the ESD fraction defective list in array base palte manufacturing process of the present utility model.Visible, adopt after the utility model scheme, the ESD fraction defective in manufacturing process has obvious decline, wherein has the scheme effect of S/D layer best to increase with sawtooth amorphous silicon piece and upside.
Table 2 is to adopt different voltage to carry out after the antistatic breaking test of noncontact GOA region, the ESD fraction defective list that different structures produces under different voltage.Visible, adopt the antistatic effect of the utility model scheme to have obvious lifting, particularly increase and have the scheme effect of conductive layer best with sawtooth amorphous silicon piece and upside.
Table 1
Table 2
Above embodiment is only for the utility model is described, but not to restriction of the present utility model.Although the utility model is had been described in detail with reference to embodiment; but those of ordinary skill in the art is to be understood that; the technical solution of the utility model is carried out to various combinations, revises or is equal to replacement; it does not depart from principle of the present utility model and spirit, within all should be encompassed in the protection range of the utility model claim.
Claims (10)
1. an array base palte, it is characterized in that, the integrated drive area of grid of described array base palte is formed with the first signal line being positioned under gate insulator, and on described gate insulator, be formed with the secondary signal line overlapping with described first signal line, the part that is not formed with secondary signal line on the described gate insulator of the integrated drive area of described grid is provided with at least one first collets.
2. array base palte according to claim 1, is characterized in that, first signal line and the overlapping position of secondary signal line are provided with the second collets between secondary signal line and gate insulator.
3. array base palte according to claim 2, is characterized in that, described the second collets are circular or oval.
4. array base palte according to claim 2, is characterized in that, described the second collets are made up of amorphous silicon.
5. according to the array base palte described in any one in claim 1-4, it is characterized in that, described at least one first collets are made up of amorphous silicon.
6. according to the array base palte described in any one in claim 1-4, it is characterized in that, described at least one first collets comprise acute angle portion.
7. array base palte according to claim 6, is characterized in that, the side of described at least one the first collets is with sawtooth.
8. according to the array base palte described in any one in claim 1-4, it is characterized in that, on described at least one first collets, be formed with conductive layer.
9. according to the array base palte described in any one in claim 1-4, it is characterized in that, described at least one first collets are arranged on around the position or described position that the integrated drive area of described grid contacts with external device.
10. a display unit, is characterized in that, comprises array base palte as claimed in any one of claims 1-9 wherein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420130961.XU CN203733797U (en) | 2014-03-21 | 2014-03-21 | Array substrate and display apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420130961.XU CN203733797U (en) | 2014-03-21 | 2014-03-21 | Array substrate and display apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203733797U true CN203733797U (en) | 2014-07-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420130961.XU Expired - Fee Related CN203733797U (en) | 2014-03-21 | 2014-03-21 | Array substrate and display apparatus |
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| Country | Link |
|---|---|
| CN (1) | CN203733797U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105549288A (en) * | 2016-03-04 | 2016-05-04 | 京东方科技集团股份有限公司 | Array substrate, preparing method of array substrate and display device |
| CN109411411A (en) * | 2018-12-07 | 2019-03-01 | 深圳市华星光电半导体显示技术有限公司 | The production method and liquid crystal display of GOA array substrate |
| WO2020088445A1 (en) * | 2018-10-29 | 2020-05-07 | 京东方科技集团股份有限公司 | Display substrate and display device |
| US11227910B2 (en) | 2018-08-06 | 2022-01-18 | Yungu (Gu'an) Technology Co., Ltd. | Display panel, display screen, and display terminal |
-
2014
- 2014-03-21 CN CN201420130961.XU patent/CN203733797U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105549288A (en) * | 2016-03-04 | 2016-05-04 | 京东方科技集团股份有限公司 | Array substrate, preparing method of array substrate and display device |
| US11227910B2 (en) | 2018-08-06 | 2022-01-18 | Yungu (Gu'an) Technology Co., Ltd. | Display panel, display screen, and display terminal |
| WO2020088445A1 (en) * | 2018-10-29 | 2020-05-07 | 京东方科技集团股份有限公司 | Display substrate and display device |
| US11221531B2 (en) | 2018-10-29 | 2022-01-11 | Beijing Boe Technology Development Co., Ltd. | Display substrate and display device |
| CN109411411A (en) * | 2018-12-07 | 2019-03-01 | 深圳市华星光电半导体显示技术有限公司 | The production method and liquid crystal display of GOA array substrate |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140723 |
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| CF01 | Termination of patent right due to non-payment of annual fee |