CN107179639B - Array substrate, manufacturing method thereof and display panel - Google Patents
Array substrate, manufacturing method thereof and display panel Download PDFInfo
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- CN107179639B CN107179639B CN201710381254.6A CN201710381254A CN107179639B CN 107179639 B CN107179639 B CN 107179639B CN 201710381254 A CN201710381254 A CN 201710381254A CN 107179639 B CN107179639 B CN 107179639B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
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Abstract
The invention discloses an array substrate, a manufacturing method thereof and a display panel. The array substrate includes: a substrate; the display panel comprises a first metal layer, a second metal layer and a plurality of data lines, wherein the first metal layer is used for arranging gate lines and data lines, the gate lines are arranged along a first direction of the surface of a substrate, the data lines are arranged along a second direction of the surface of the substrate, the data lines are disconnected at positions crossed with the gate lines to form a plurality of data line segments, and the first direction is vertical to the second direction; a first insulating layer provided with a plurality of first via holes; and the second metal layer is used for setting the touch control line and the data bridge crossing line, the data bridge crossing line is connected with two adjacent data line segments of the data line through the first via hole, and the resistance of the metal forming the second metal layer is smaller than that of the metal forming the first metal layer. According to the invention, when the display panel is switched from the touch sensing stage to the display stage, the data line does not have instantaneous large current, so that the reliability of the display performance of the display panel is ensured.
Description
Technical Field
The invention relates to the technical field of display panels, in particular to an array substrate, a manufacturing method of the array substrate and a display panel.
Background
With the development of science and technology, intelligent devices such as mobile phones, tablet computers, digital cameras and intelligent wearable products with touch functions simplify human-computer interaction, and bring high-quality user experience to users.
The existing touch technologies of the display panel include an "In cell" technology and an "On cell" technology, where the "On cell" technology embeds a touch panel function between a color film substrate and a polarizing plate, and the "In cell" technology embeds a touch panel function between an array substrate and a color film substrate. In the "In cell" technology, the integrated process route of the array substrate is the same as the integrated process route of the non-touch function, and two metal layers are usually arranged, one metal layer runs through the gate line, and the other metal layer runs through the touch line and the data line.
Because the touch control line and the data line are arranged on the same metal layer, the touch control line and the data line are made of the same metal, and wiring is completed in the same process, the resistance of the touch control line and the resistance of the data line are the same. The touch control line is required to have lower resistance in order to ensure the sensitive and accurate touch control characteristics of the display panel, and therefore, the resistance of the data line using the same metal wiring is also very low, at the moment, a touch control signal is inserted into a picture under 120Hz, and when the display signal is input again, the data line has instantaneous large current to cause H-line (the display panel has horizontal lines), so that the reliability of the display performance of the display panel is influenced.
Therefore, it is an urgent need in the art to provide an array substrate, a method for manufacturing the same, and a display panel, which can improve the reliability of the display performance of the display panel.
Disclosure of Invention
In view of this, the invention provides an array substrate, a manufacturing method thereof and a display panel, which solve the technical problem of improving the reliability of the display performance of the display panel.
The present invention provides an array substrate, including:
a substrate;
the first metal layer is arranged on one side of the substrate and used for arranging a gate line and a data line, the gate line is arranged along a first direction of the surface of the substrate, the data line is arranged along a second direction of the surface of the substrate, the data line is disconnected at a position crossed with the gate line to form a plurality of data line segments, and the first direction is perpendicular to the second direction;
the first insulating layer is arranged on one side, far away from the substrate, of the first metal layer, wherein the first insulating layer is provided with a plurality of first through holes;
and the second metal layer is arranged on one side, far away from the first metal layer, of the first insulating layer, and is used for arranging a touch line and a data bridge line, the data bridge line is connected with two adjacent data line segments of the data line through the first via hole, and the resistance of the metal forming the second metal layer is smaller than that of the metal forming the first metal layer.
Optionally, the array substrate includes a display area and a frame area, and the array substrate further includes:
the gate driving circuit is arranged in the frame area and comprises a plurality of signal lines, each signal line comprises a first signal line segment arranged on the first metal layer and a second signal line segment arranged on the second metal layer, and the first signal line segments are connected with the second signal line segments through the first through holes.
Optionally, the array substrate includes a plurality of sub-pixels arranged in a matrix, the gate line is located between two rows of sub-pixels arranged along the first direction, and the data line is located between two rows of sub-pixels arranged along the second direction;
the extension directions of the touch control line and the data line are the same, and the touch control line and the data line between two same rows of sub-pixels are spaced by a preset distance in the first direction.
Optionally, a thin film transistor is disposed on the array substrate, the first metal layer is further configured to dispose a gate of the thin film transistor, and the second metal layer is further configured to dispose a source and a drain of the thin film transistor;
the array substrate further includes:
the first electrode layer is arranged on the same layer as the second metal layer and is used for arranging a pixel electrode, and the pixel electrode is connected with the drain electrode of the thin film transistor;
the second insulating layer is arranged on one side, far away from the first insulating layer, of the second metal layer, wherein the second insulating layer is provided with a plurality of second through holes;
and the second electrode layer is arranged on one side, away from the second metal layer, of the second insulating layer, and is used for arranging a plurality of touch electrodes distributed in an array manner, and the touch electrodes are connected with the touch lines through the second via holes.
Optionally, the touch electrode is reused as a common electrode in a display stage, and the common electrode and the pixel electrode form a pixel capacitor.
Optionally, the touch electrode covers a plurality of the sub-pixels;
and one data line is arranged between every two rows of sub-pixels arranged along the second direction, and one touch line is arranged at every three intervals behind the data lines.
Optionally, the data bridge-crossing line and the touch line extend in the same direction, and the data bridge-crossing line is located between two adjacent sub-pixels in the second direction, so that the data bridge-crossing line is insulated from the touch line.
Optionally, the predetermined distance is 1um to 2 um.
The invention also provides a manufacturing method of the array substrate, which comprises the following steps:
arranging a substrate;
arranging a first metal layer on one side of the substrate;
etching the first metal layer to form a gate line and a data line, wherein the gate line is wired along a first direction of the surface of the substrate, the data line is wired along a second direction of the surface of the substrate, the data line is disconnected at a position crossing the gate line to form a plurality of data line segments, and the first direction is perpendicular to the second direction;
providing a first insulating layer on the first metal layer;
punching the first insulating layer to form a plurality of first through holes;
disposing a second metal layer on the first insulating layer;
and etching the second metal layer to form a touch line and a data bridge line, wherein the data bridge line is connected with two adjacent data line segments of the data line through the first via hole, and the resistance of the metal forming the second metal layer is smaller than that of the metal forming the first metal layer.
Optionally, the array substrate includes a display area and a frame area, and the array substrate further includes a gate driving circuit disposed in the frame area, the gate driving circuit is connected to the gate lines, the gate driving circuit includes a plurality of signal lines, and the signal lines include a first signal line segment and a second signal line segment;
in the step of etching the first metal layer to form the gate line and the data line, etching the first metal layer to form the first signal line segment while forming the gate line and the data line;
in the step of etching the second metal layer to form the touch line and the data bridge crossing line, the second metal layer is etched to form the second signal line segment while forming the touch line and the data bridge crossing line, wherein the first signal line segment is connected with the second signal line segment through the first via hole.
Optionally, the array substrate includes a plurality of sub-pixels arranged in a matrix, the gate line is located between two rows of sub-pixels arranged along the first direction, and the data line is located between two rows of sub-pixels arranged along the second direction;
the extension direction of the touch line is the same as that of the data line, and the touch line and the data line between two same rows of sub-pixels are separated by a preset distance.
Optionally, a thin film transistor is arranged on the array substrate;
in the step of etching the first metal layer to form the gate line and the data line, etching the first metal layer to form the gate line and the data line and simultaneously form the gate of the thin film transistor;
in the step of etching the second metal layer to form the touch line and the data bridge crossing line, etching the second metal layer to form the source and the drain of the thin film transistor while forming the touch line and the data bridge crossing line;
the manufacturing method of the array substrate further comprises the following steps:
after the second metal layer is etched to form a touch line, a data bridge line, and a source electrode and a drain electrode of the thin film transistor, a first electrode layer is arranged at the same layer as the second metal layer;
etching the first electrode layer to form a pixel electrode, wherein the pixel electrode is connected with a drain electrode of the thin film transistor;
providing a second insulating layer on the second metal layer and the first electrode layer;
punching the second insulating layer to form a plurality of second via holes;
providing a second electrode layer on the second insulating layer;
and etching the second electrode layer to form a plurality of touch electrodes distributed in an array, wherein the touch electrodes are connected with the touch lines through the second via holes.
Optionally, the touch electrode is reused as a common electrode in a display stage, and the common electrode and the pixel electrode form a pixel capacitor.
Optionally, the touch electrode covers a plurality of the sub-pixels;
and one data line is arranged between every two rows of sub-pixels arranged along the second direction, and one touch line is arranged at every three intervals behind the data lines.
Optionally, the data bridge-crossing line and the touch line extend in the same direction, and the data bridge-crossing line is located between two adjacent sub-pixels in the first direction, so that the data bridge-crossing line is insulated from the touch line.
Optionally, the predetermined distance is 1um to 2 um.
The invention also provides a display panel comprising the array substrate.
Compared with the prior art, the array substrate, the manufacturing method thereof and the display panel have the following beneficial effects that:
the array substrate provided by the invention is provided with a gate line and a data line which are wired on a first metal layer, a touch line and a data bridge line which are wired on a second metal layer, wherein the data line is disconnected on the first metal layer at the crossing position of the gate line and the data line, and is connected with the data bridge line through the data bridge line of the second metal layer, the transmission of a data line signal is ensured through the bridge connection mode, moreover, as most of the data line and the touch line are not in the same metal layer, the metal resistance of the second metal layer where the touch line is positioned can be set to be smaller to meet the touch function requirement, the touch induction performance is improved, for the data line, most of the routing is arranged on the first metal layer, only a small part of the data bridge line is arranged on the second metal layer, the resistance of the metal arranged on the first metal layer can be the same as the resistance of the data line in the conventional design, or the resistance of the metal arranged on the first metal layer can be properly increased to make up the small resistance of the, the whole resistance on the data line is ensured to be large enough, and when the display panel is switched from the touch sensing stage to the display stage, the data line is not provided with instantaneous large current, so that the display performance reliability of the display panel is ensured.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic diagram of a film structure of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a first metal layer inner wiring of the array substrate according to the embodiment of the invention;
fig. 3 is a schematic cross-sectional view of a data line cross-bridge routing of an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a signal line via connection in a frame region of an array substrate according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a touch line arrangement of an array substrate according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a film layer of an embodiment of an array substrate according to the present invention;
fig. 7 is a schematic top view of an array substrate according to an embodiment of the invention;
FIG. 8 is a schematic cross-sectional view of the array substrate at the position of the line A;
FIG. 9 is a cross-sectional view of the array substrate at the position of the cross-section line B;
fig. 10 is a schematic layout view of touch electrodes of an array substrate according to an embodiment of the present invention;
fig. 11 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 12 is a flowchart of an alternative implementation of a manufacturing method of an array substrate according to an embodiment of the present invention;
fig. 13 is a flowchart of another alternative implementation of a manufacturing method of an array substrate according to an embodiment of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
The embodiment of the invention provides an array substrate, a schematic diagram of a film structure of the array substrate is shown in fig. 1, and the array substrate comprises: the circuit board comprises a substrate 101, a first metal layer 102 arranged on one side of the substrate 101, a first insulating layer 103 arranged on one side of the first metal layer 102 far away from the substrate 101, and a second metal layer 104 arranged on one side of the first insulating layer 103 far away from the first metal layer 102.
The first metal layer 102 is used for providing a gate line 105 and a data line 106, the schematic diagram of the inner wiring of the first metal layer refers to fig. 2, the gate line 105 is routed along a first direction a of the substrate surface, the data line 106 is routed along a second direction b of the substrate surface, the data line 106 is disconnected at a position crossing the gate line 105 to form a plurality of data line segments, and the first direction a is perpendicular to the second direction b.
The gate lines are used for transmitting gate scanning signals, the data lines are used for transmitting data signals, the gate lines and the data lines are arranged on the first metal layer, the routing direction of the gate lines is perpendicular to the routing direction of the data lines, in order to ensure that the gate lines and the data lines are not short-circuited, the data lines are disconnected at the crossing positions of the gate lines, and the data lines form a plurality of data line segments in the second direction.
Fig. 3 shows a cross-sectional view of a data line crossing bridge trace, wherein a plurality of first vias K1 are disposed in the first insulating layer 103. The second metal layer 104 is used to provide a touch line (not shown) and a data bridge line 108, the data bridge line 108 connects two adjacent data line segments of the data line 106 through a first via K1, and the resistance of the metal forming the second metal layer 104 is smaller than the resistance of the metal forming the first metal layer 102.
As shown in fig. 3, the data line 106 disposed in the first metal layer 102 is disconnected at a position crossing the gate line 105 to form a plurality of data line segments, and the data bridge 108 disposed in the second metal layer 104 connects two adjacent data line segments of the data line 106 disposed in the first metal layer 102 through the first via K1.
The touch control line and the data bridge crossing line are arranged on the second metal layer, the data bridge crossing line is connected with two adjacent data line segments of the data line on the first metal layer through the first via hole, and the data line is conducted in a bridge crossing mode. The resistance of the metal forming the second metal layer is smaller than that of the metal forming the first metal layer, and the resistance of the metal forming the first metal layer may be the same as that of the metal of the first metal layer employed in the conventional design, or the resistance of the metal of the first metal layer may be increased appropriately.
The array substrate provided by the invention is provided with a gate line and a data line which are wired on a first metal layer, a touch line and a data bridge line which are wired on a second metal layer, wherein the data line is disconnected on the first metal layer at the crossing position of the gate line and the data line, and is connected with the data bridge line through the data bridge line of the second metal layer, the transmission of a data line signal is ensured through the bridge connection mode, moreover, as most of the data line and the touch line are not in the same metal layer, the metal resistance of the second metal layer where the touch line is positioned can be set to be smaller to meet the touch function requirement, the touch induction performance is improved, for the data line, most of the routing is arranged on the first metal layer, only a small part of the data bridge line is arranged on the second metal layer, the resistance of the metal arranged on the first metal layer can be the same as the resistance of the data line in the conventional design, or the resistance of the metal arranged on the first metal layer can be properly increased to make up the small resistance of the, the whole resistance on the data line is ensured to be large enough, and when the display panel is switched from the touch sensing stage to the display stage, the data line is not provided with instantaneous large current, so that the display performance reliability of the display panel is ensured.
Further, in some optional embodiments, the array substrate provided in the embodiments of the present invention includes a display area and a frame area, and the array substrate further includes: the grid driving circuit is arranged in the frame area and comprises a plurality of signal wires, each signal wire comprises a first signal wire section arranged on the first metal layer and a second signal wire section arranged on the second metal layer, and the first signal wire sections are connected with the second signal wire sections through first through holes.
Specifically, as shown in fig. 4, the first signal line segment X1 disposed on the first metal layer and the second signal line segment X2 disposed on the second metal layer are connected through the first via K1 disposed on the first insulating layer 103.
The signal line of the grid driving circuit in the frame area is directly connected with the first via hole between the first metal layer and the second metal layer, and compared with the conventional design, the signal line does not pass through the indium tin oxide thin film layer when the line is replaced, so that the electrochemical corrosion of the line replacement hole caused by the fact that water vapor enters the frame glue in 8585 testing (the temperature is 85 ℃ and the relative humidity is 85%) and the using process is avoided, and the using performance of the array substrate is influenced.
Further, in some alternative embodiments, as shown in fig. 5, the array substrate includes a plurality of sub-pixels sp arranged in a matrix, the gate line 105 is located between two rows of sub-pixels sp arranged along the first direction a, and the data line 106 is located between two rows of sub-pixels sp arranged along the second direction b; the extending direction of the touch line 107 is the same as that of the data line 106, and the touch line 107 and the data line 106 between two same rows of sub-pixels are spaced apart by a predetermined distance d in the first direction a, preferably, the predetermined distance d is 1um to 2 um.
In fig. 5, the position C is a data bridge line connection position, the extending directions of the data bridge line 108 and the touch line 107 are the same, and the data bridge line 108 is located between two adjacent sub-pixels in the second direction b, so that the data bridge line 108 is insulated from the touch line 107.
The data line sets up and walks the line at first metal level, the touch-control line sets up and walks the line at the second metal level, touch-control line and data line that the setting is located between two lines of same sub-pixels are at the interval predetermined distance of first direction, signal mutual interference between touch-control line and the data line has been avoided, compare simultaneously with touch-control line and data line when setting up in same metal level, can shorten the interval distance of touch-control line and data line in the first direction to 1um to 2um, the distance between touch-control line and the data line has obviously been shortened, pixel district transmission area increases, the aperture opening ratio has effectively been increased.
Further, in some optional embodiments, a schematic view of a film layer of an array substrate provided in the embodiment of the present invention is shown in fig. 6, and includes: the semiconductor device includes a substrate 101, a first metal layer 102 disposed on one side of the substrate 101, a first insulating layer 103 disposed on one side of the first metal layer 102 away from the substrate 101, a second metal layer 104 disposed on one side of the first insulating layer 103 away from the first metal layer 102, a first electrode layer (not shown) disposed on the same layer as the second metal layer, a second insulating layer 109 disposed on one side of the second metal layer 104 away from the first insulating layer 103, and a second electrode layer 110 disposed on one side of the second insulating layer 109 away from the second metal layer 104.
Specifically, referring to fig. 7 to 9, fig. 7 is a schematic top view of an array substrate according to an embodiment of the present invention, fig. 8 is a schematic cross-sectional view of the array substrate at a position of a cross-sectional line a, and fig. 9 is a schematic cross-sectional view of the array substrate at a position of a cross-sectional line B.
The schematic plan view of the array substrate is shown in fig. 7, a thin film transistor is disposed on the array substrate, the first metal layer 102 is provided with a gate line 105 and a data line 106, a gate 111 of the thin film transistor is further disposed, the second metal layer 104 is provided with a touch line 107 and a data bridge line 108, and a source 112 and a drain 113 of the thin film transistor are further disposed, wherein the data bridge line 108 is connected to two adjacent data line segments of the data line 106 through a first via K1; the first electrode layer arranged on the same layer as the second metal layer is used for arranging a pixel electrode 114, and the pixel electrode 114 is connected with the drain 113 of the thin film transistor; the second insulating layer 109 arranged on the side of the second metal layer 104 far away from the first insulating layer 103 is provided with a plurality of second via holes K2; the second electrode layer disposed on the side of the second insulating layer 109 away from the second metal layer 104 is used to dispose a plurality of touch electrodes (not shown) distributed in an array, and the touch electrodes are connected to the touch lines 107 through the second vias K2.
Fig. 8 is a schematic cross-sectional view of the array substrate at the position of the cross-sectional line a, which shows a gate 111 of the thin film transistor disposed on the first metal layer, a source 112 and a drain 113 disposed on the second metal layer, a pixel electrode 114 connected to the drain 113, a touch line 107 disposed on the second metal layer, and a touch electrode 115 disposed on the side of the second insulating layer 109 away from the second metal layer.
Fig. 9 is a schematic cross-sectional view of the array substrate at the position of the cross-sectional line B, which shows a data line 106 disposed on the first metal layer, a touch line 107 disposed on the second metal layer, a pixel electrode 114 disposed on the same layer as the second metal layer, and a touch electrode 115 disposed on one side of the second insulating layer 109 away from the second metal layer.
The array substrate provided by the embodiment has few film structures, is beneficial to manufacturing a thinned array substrate, and meanwhile, only the first insulating layer and the second insulating layer are provided with through hole connections, so that the through hole-less process is simple.
Further, in some optional embodiments, the touch electrode is reused as a common electrode in the display stage, and the common electrode and the pixel electrode form a pixel capacitor. The touch electrode is reused as a common electrode in the display stage, so that the thickness of the array substrate can be reduced while the embedded touch function is realized.
In some optional embodiments, in the touch electrode arrangement of the array substrate provided in the embodiments of the present invention, as shown in fig. 10, the array substrate includes a plurality of touch electrodes 115 arranged in an m × n array, where m and n are integers greater than 1 (where m is 4, and n is 3, for example). Each touch electrode 115 is connected to at least one touch line 107 (one touch line is exemplarily shown in the figure), and the touch electrode 115 and the touch line 107 can be electrically connected through a via K2. The touch lines 107 are led out to the non-display area and electrically connected to a touch driving chip (not shown in the figure), and the touch driving chip is configured to provide touch scanning signals for the touch electrodes 115 and perform touch detection according to touch detection signals output by the touch electrodes 115. The touch driving chip can be arranged separately from the display driving chip, and can also be integrated into the same chip.
The touch electrode 115 is reused as a common electrode in the display stage, and in the display stage, a common voltage is applied to each common electrode, and an electric field for driving liquid crystal molecules in the liquid crystal layer to rotate is formed between the common electrode and a pixel electrode arranged in the sub-pixel; in the touch control stage, touch control signals are respectively applied to the touch control electrodes, and capacitance change transmitted to the touch control electrodes in the touch control driving circuit is detected in a self-capacitance mode so as to realize touch control detection. It should be noted that, in the embodiment of the present invention, the specific shape of the touch electrode 115 is not limited, and may be a rectangle, a windmill, or any irregular pattern.
Further, in some optional embodiments, the touch electrode covers a plurality of sub-pixels; a data line is arranged between every two rows of sub-pixels arranged along the second direction, and a touch line is arranged after every three data lines. The touch electrode covers the plurality of sub-pixels and is distributed in an array mode, one touch line is arranged at intervals of three data lines, touch detection precision is met, and meanwhile the aperture opening ratio is guaranteed.
While the present invention further provides an embodiment of a method for fabricating an array substrate, the following description is provided for the method for fabricating an array substrate, and those skilled in the art can refer to the embodiment of the array substrate and the embodiment of the method for fabricating the array substrate when understanding the technical solution of the present invention.
The method for manufacturing an array substrate provided by the embodiment of the present invention, with reference to fig. 11 in the flowchart, includes:
step S101: a substrate is disposed.
Step S102: a first metal layer is disposed on one side of the substrate.
Step S103: and etching the first metal layer to form a gate line and a data line, wherein the gate line is arranged along the first direction of the substrate surface, the data line is arranged along the second direction of the substrate surface, the data line is disconnected at the position crossed with the gate line to form a plurality of data line segments, and the first direction is vertical to the second direction.
Step S104: a first insulating layer is disposed on the first metal layer.
Step S105: and punching the first insulating layer to form a plurality of first through holes.
Step S106: and arranging a second metal layer on the first insulating layer, wherein the resistance of the metal forming the second metal layer is smaller than that of the metal forming the first metal layer.
Step S107: and etching the second metal layer to form a touch line and a data bridge crossing line, wherein the data bridge crossing line is connected with two adjacent data line segments of the data line through the first via hole.
The array substrate provided in this embodiment is configured to have the gate lines and the data lines wired in the first metal layer, and the touch lines and the data bridge lines wired in the second metal layer, where the data bridge lines are connected to two adjacent data line segments of the data lines in the first metal layer through the first via holes, so as to ensure signal transmission of the data lines in a bridge-crossing connection manner, and the resistance of the metal forming the second metal layer is smaller than that of the metal forming the first metal layer, and the resistance of the metal forming the touch lines is set small, so as to improve touch sensing performance, most of the routing lines of the data lines are disposed in the first metal layer, only a small part of the data bridge lines are disposed in the second metal layer, and the resistance of the metal forming the first metal layer is the same as that in a conventional design, or the resistance of the metal forming the first metal layer can be appropriately increased to compensate for the small resistance of the data bridge lines disposed in the second metal layer, the whole resistance on the data line is ensured to be large enough, and when the display panel is switched from the touch sensing stage to the display stage, the data line is not provided with instantaneous large current, so that the display performance reliability of the display panel is ensured.
Further, in some optional embodiments, the array substrate includes a display region and a frame region, the array substrate further includes a gate driving circuit disposed in the frame region, the gate driving circuit is connected to the gate lines, the gate driving circuit includes a plurality of signal lines, and the signal lines include a first signal line segment and a second signal line segment; the method for manufacturing an array substrate provided by the embodiment of the invention, as shown in fig. 12, includes:
step S201: a substrate is disposed.
Step S202: a first metal layer is disposed on one side of the substrate.
Step S203: and etching the first metal layer to form a gate line and a data line, and simultaneously forming a first signal line segment, wherein the gate line is arranged along the first direction of the substrate plate surface, the data line is arranged along the second direction of the substrate plate surface, the data line is disconnected at the position crossed with the gate line to form a plurality of data line segments, and the first direction is vertical to the second direction.
Step S204: a first insulating layer is disposed on the first metal layer.
Step S205: and punching the first insulating layer to form a plurality of first through holes.
Step S206: and arranging a second metal layer on the first insulating layer, wherein the resistance of the metal forming the second metal layer is smaller than that of the metal forming the first metal layer.
Step S207: and etching the second metal layer to form a touch line and a data bridge line, and simultaneously forming a second signal line segment, wherein the first signal line segment is connected with the second signal line segment through a first via hole, and the data bridge line is connected with two adjacent data line segments of the data line through the first via hole.
The signal line of the grid driving circuit in the frame area is directly connected with the first via hole between the first metal layer and the second metal layer, and compared with the conventional design, the signal line does not pass through an indium tin oxide thin film layer when the line is replaced, so that the problem that in the 8585 (the temperature is 85 ℃, and the relative humidity is 85%) test and use processes, water vapor enters the frame glue to cause electrochemical corrosion of the line replacement hole and influence the use performance of the array substrate is avoided.
Further, in some optional embodiments, the array substrate includes a plurality of sub-pixels arranged in a matrix, the gate line is located between two rows of sub-pixels arranged along the first direction, and the data line is located between two rows of sub-pixels arranged along the second direction; the extending direction of the touch control line is the same as that of the data line, and the touch control line and the data line between two rows of same sub-pixels are spaced by a preset distance, preferably, the preset distance is 1um to 2 um.
Further, in some optional embodiments, the data bridge line and the touch line extend in the same direction, and the data bridge line is located between two adjacent sub-pixels in the first direction, so that the data bridge line is insulated from the touch line.
The data line sets up and walks the line at first metal level, the touch-control line sets up and walks the line at the second metal level, touch-control line and data line that the setting is located between two lines of same sub-pixels are at the interval predetermined distance of first direction, signal mutual interference between touch-control line and the data line has been avoided, compare simultaneously with touch-control line and data line when setting up in same metal level, can shorten the interval distance of touch-control line and data line in the first direction to 1um to 2um, the distance between touch-control line and the data line has obviously been shortened, pixel district transmission area increases, the aperture opening ratio has effectively been increased.
Further, in some optional embodiments, a thin film transistor is disposed on the array substrate; the method for manufacturing an array substrate provided by the embodiment of the present invention, as shown in fig. 13, includes:
step S301: a substrate is disposed.
Step S302: a first metal layer is disposed on one side of the substrate.
Step S303: and etching the first metal layer to form a gate line and a data line, and simultaneously forming a gate of the thin film transistor, wherein the gate line is arranged along the first direction of the surface of the substrate, the data line is arranged along the second direction of the surface of the substrate, the data line is disconnected at the position crossed with the gate line to form a plurality of data line segments, and the first direction is vertical to the second direction.
Step S304: a first insulating layer is disposed on the first metal layer.
Step S305: and punching the first insulating layer to form a plurality of first through holes.
Step S306: and arranging a second metal layer on the first insulating layer, wherein the resistance of the metal forming the second metal layer is smaller than that of the metal forming the first metal layer.
Step S307: and etching the second metal layer to form a touch line and a data bridge line and also form a source electrode and a drain electrode of the thin film transistor, wherein the data bridge line is connected with two adjacent data line segments of the data line through the first via hole.
Step S308: arranging a first electrode layer at the position of the same layer as the second metal layer;
step S309: etching the first electrode layer to form a pixel electrode, wherein the pixel electrode is connected with a drain electrode of the thin film transistor;
step S310: a second insulating layer is arranged on the second metal layer and the first electrode layer;
step S311: punching the second insulating layer to form a plurality of second through holes;
step S312: providing a second electrode layer on the second insulating layer;
step S313: and etching the second electrode layer to form a plurality of touch electrodes distributed in an array, wherein the touch electrodes are connected with the contact control lines through the second through holes.
The array substrate provided by the embodiment has few film structures, is beneficial to manufacturing a thinned array substrate, and meanwhile, only the first insulating layer and the second insulating layer are provided with through hole connections, so that the through hole-less process is simple.
Further, in some optional embodiments, the touch electrode is reused as a common electrode in the display stage, and the common electrode and the pixel electrode form a pixel capacitor. The touch electrode is reused as a common electrode in the display stage, so that the thickness of the array substrate can be reduced while the embedded touch function is realized.
Further, in some optional embodiments, the touch electrode covers a plurality of sub-pixels; a data line is arranged between every two rows of sub-pixels arranged along the second direction, and a touch line is arranged after every three data lines. The touch electrode covers the plurality of sub-pixels and is distributed in an array mode, one touch line is arranged at intervals of three data lines, touch detection precision is met, and meanwhile the aperture opening ratio is guaranteed.
The embodiment of the invention also provides a display panel which comprises the array substrate. The display panel has good reliability of display performance, large transmission area of a pixel area and high aperture ratio.
By the embodiment, the display panel and the display panel detection method disclosed by the invention have the following beneficial effects that:
(1) the array substrate provided by the invention is provided with a gate line and a data line which are wired on a first metal layer, a touch line and a data bridge line which are wired on a second metal layer, wherein the data line is disconnected on the first metal layer at the crossing position of the gate line and the data line, and is connected with the data bridge line through the data bridge line of the second metal layer, the transmission of a data line signal is ensured in a bridge-crossing connection mode, and as most of the data line and the touch line are not in the same metal layer, the metal resistance of the second metal layer where the touch line is located can be set to be smaller to meet the touch function requirement, the touch induction performance is improved The resistance guarantees that the overall resistance on the data line is large enough, and when the display panel is switched to the display stage from the touch sensing stage, the data line does not have instantaneous large current, so that the display performance reliability of the display panel is guaranteed.
(2) The signal line of the grid driving circuit is directly connected between the first metal layer and the second metal layer through the first via hole, and compared with the conventional design, the signal line does not pass through the indium tin oxide thin film layer when the line is replaced, so that the problem that the service performance of the array substrate is influenced by electrochemical corrosion of the line replacement hole due to the fact that water vapor enters the frame glue in 8585 (the temperature is 85 ℃ and the relative humidity is 85%) testing and using processes is avoided.
(3) The data lines are arranged on the first metal layer, the touch lines are arranged on the second metal layer, the touch lines and the data lines which are arranged between two lines of same sub-pixels are arranged at a preset distance in the first direction, signal mutual interference between the touch lines and the data lines is avoided, meanwhile, compared with the case that the touch lines and the data lines are arranged on the same metal layer, the distance between the touch lines and the data lines is obviously shortened, the transmission area of a pixel area is increased, and the aperture opening ratio is effectively increased.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (13)
1. An array substrate, comprising:
a substrate;
the first metal layer is arranged on one side of the substrate and used for arranging a gate line and a data line, the gate line is arranged along a first direction of the surface of the substrate, the data line is arranged along a second direction of the surface of the substrate, the data line is disconnected at a position crossed with the gate line to form a plurality of data line segments, and the first direction is perpendicular to the second direction;
the first insulating layer is arranged on one side, far away from the substrate, of the first metal layer, wherein the first insulating layer is provided with a plurality of first through holes;
the second metal layer is arranged on one side, far away from the first metal layer, of the first insulating layer and used for arranging a touch line and a data bridge line, the data bridge line is connected with two adjacent data line segments of the data line through the first via hole, and the resistance of the metal forming the second metal layer is smaller than that of the metal forming the first metal layer;
the display panel comprises a display area, a frame area and a gate drive circuit arranged in the frame area, wherein the gate drive circuit comprises a plurality of signal wires, each signal wire comprises a first signal wire section arranged in the first metal layer and a second signal wire section arranged in the second metal layer, and the first signal wire section is connected with the second signal wire section through the first through hole;
the gate lines are positioned between two rows of sub-pixels arranged along the first direction, and the data lines are positioned between two rows of sub-pixels arranged along the second direction; the extension directions of the touch control line and the data line are the same, and the touch control line and the data line between two same rows of sub-pixels are spaced by a preset distance in the first direction.
2. The array substrate of claim 1,
the array substrate is provided with a thin film transistor, the first metal layer is also used for arranging a grid electrode of the thin film transistor, and the second metal layer is also used for arranging a source electrode and a drain electrode of the thin film transistor;
the array substrate further includes:
the first electrode layer is arranged on the same layer as the second metal layer and is used for arranging a pixel electrode, and the pixel electrode is connected with the drain electrode of the thin film transistor;
the second insulating layer is arranged on one side, far away from the first insulating layer, of the second metal layer, wherein the second insulating layer is provided with a plurality of second through holes;
and the second electrode layer is arranged on one side, away from the second metal layer, of the second insulating layer, and is used for arranging a plurality of touch electrodes distributed in an array manner, and the touch electrodes are connected with the touch lines through the second via holes.
3. The array substrate of claim 2, wherein the touch electrode is reused as a common electrode in a display stage, and the common electrode and the pixel electrode form a pixel capacitor.
4. The array substrate of claim 2,
the touch electrode covers a plurality of sub-pixels;
and one data line is arranged between every two rows of sub-pixels arranged along the second direction, and one touch line is arranged at every three intervals behind the data lines.
5. The array substrate of claim 1, wherein the data bridge line and the touch line extend in the same direction, and the data bridge line is located between two adjacent sub-pixels in the second direction, so as to insulate the data bridge line from the touch line.
6. The array substrate of claim 1, wherein the predetermined distance is 1um to 2 um.
7. The manufacturing method of the array substrate is characterized in that the array substrate comprises a display area and a frame area, the array substrate further comprises a gate driving circuit arranged in the frame area, the gate driving circuit is connected with a gate line, the gate driving circuit comprises a plurality of signal lines, and the signal lines comprise first signal line segments and second signal line segments; the array substrate further comprises a plurality of sub-pixels distributed in a matrix; the manufacturing method of the array substrate comprises the following steps:
arranging a substrate;
arranging a first metal layer on one side of the substrate;
etching the first metal layer to form a gate line, a data line and a first signal line segment, wherein the gate line is arranged along a first direction of the surface of the substrate, the data line is arranged along a second direction of the surface of the substrate, the data line is disconnected at a position crossed with the gate line to form a plurality of data line segments, the gate line is positioned between two rows of sub-pixels arranged along the first direction, the data line is positioned between two rows of sub-pixels arranged along the second direction, and the first direction is perpendicular to the second direction;
providing a first insulating layer on the first metal layer;
punching the first insulating layer to form a plurality of first through holes;
disposing a second metal layer on the first insulating layer;
etching the second metal layer to form a touch line, a data bridge line and a second signal line segment, wherein the data bridge line is connected with two adjacent data line segments of the data line through the first via hole, the first signal line segment is connected with the second signal line segment through the first via hole, and the resistance of the metal forming the second metal layer is smaller than that of the metal forming the first metal layer; the extension direction of the touch line is the same as that of the data line, and the touch line and the data line between two same rows of sub-pixels are separated by a preset distance.
8. The method for manufacturing an array substrate of claim 7,
a thin film transistor is arranged on the array substrate;
in the step of etching the first metal layer to form the gate line and the data line, etching the first metal layer to form the gate line and the data line and simultaneously form the gate of the thin film transistor;
in the step of etching the second metal layer to form the touch line and the data bridge crossing line, etching the second metal layer to form the source and the drain of the thin film transistor while forming the touch line and the data bridge crossing line;
the manufacturing method of the array substrate further comprises the following steps:
after the second metal layer is etched to form a touch line, a data bridge line, and a source electrode and a drain electrode of the thin film transistor, a first electrode layer is arranged at the same layer as the second metal layer;
etching the first electrode layer to form a pixel electrode, wherein the pixel electrode is connected with a drain electrode of the thin film transistor;
providing a second insulating layer on the second metal layer and the first electrode layer;
punching the second insulating layer to form a plurality of second via holes;
providing a second electrode layer on the second insulating layer;
and etching the second electrode layer to form a plurality of touch electrodes distributed in an array, wherein the touch electrodes are connected with the touch lines through the second via holes.
9. The method for manufacturing the array substrate according to claim 8, wherein the touch electrode is reused as a common electrode in a display stage, and the common electrode and the pixel electrode form a pixel capacitor.
10. The method of claim 8, wherein the step of forming the array substrate comprises forming a first metal layer on the substrate,
the touch electrode covers a plurality of sub-pixels;
and one data line is arranged between every two rows of sub-pixels arranged along the second direction, and one touch line is arranged at every three intervals behind the data lines.
11. The method for manufacturing the array substrate of claim 7, wherein the data bridge line and the touch line extend in the same direction, and the data bridge line is located between two adjacent sub-pixels in the first direction, so as to insulate the data bridge line from the touch line.
12. The method of claim 7, wherein the predetermined distance is 1um to 2 um.
13. A display panel comprising the array substrate according to any one of claims 1 to 6.
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| CN107085332B (en) * | 2017-06-27 | 2020-05-22 | 上海天马微电子有限公司 | Display panel and display device |
| CN107908304B (en) * | 2017-09-29 | 2021-06-01 | 信利（惠州）智能显示有限公司 | Wiring method of touch wire |
| CN108732832B (en) * | 2018-05-18 | 2020-04-28 | 京东方科技集团股份有限公司 | Touch display panel and electronic device |
| CN111627938B (en) * | 2020-06-29 | 2022-02-22 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| US11403991B2 (en) | 2020-09-03 | 2022-08-02 | Tcl China Star Optoelectronics Technology Co., Ltd. | Display panel and spliced display panel |
| CN112071192B (en) * | 2020-09-03 | 2022-01-25 | Tcl华星光电技术有限公司 | Display panel and splicing display panel |
| CN118076917A (en) * | 2022-08-19 | 2024-05-24 | 京东方科技集团股份有限公司 | Display panel, maintenance method thereof and display device |
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