CN107179639A - Array base palte and preparation method thereof and display panel - Google Patents
Array base palte and preparation method thereof and display panel Download PDFInfo
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- CN107179639A CN107179639A CN201710381254.6A CN201710381254A CN107179639A CN 107179639 A CN107179639 A CN 107179639A CN 201710381254 A CN201710381254 A CN 201710381254A CN 107179639 A CN107179639 A CN 107179639A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
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- General Physics & Mathematics (AREA)
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- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Human Computer Interaction (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Position Input By Displaying (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a kind of array base palte and preparation method thereof and display panel.The array base palte includes：Substrate；The first metal layer, wherein, the first metal layer is used to set gate line and data wire, first direction cabling of the gate line along substrate surface, second direction cabling of the data wire along substrate surface, data wire disconnects forming multiple data line segments with the position that gate line intersects, and first direction is vertical with second direction；It is provided with the first insulating barrier of multiple first vias；Second metal layer for setting touch-control line and data bridge line, data bridge line connects two adjacent data line segments of data wire by the first via, and the resistance for forming the metal of second metal layer is less than the resistance for the metal for forming the first metal layer.By the present invention, display panel does not have the high current of moment from when being switched to the display stage in the touch-control sensing stage on data wire, it is ensured that the display performance reliability of display panel.
Description
Technical field
The present invention relates to technical field of display panel, more particularly, to a kind of array base palte and preparation method thereof and aobvious
Show panel.
Background technology
With the development of science and technology, the intelligence such as mobile phone, tablet personal computer, digital camera with touch controllable function, intelligence wearing product
Energy equipment simplifies human-computer interaction, and the Consumer's Experience of high-quality is brought to user.
The touch technology of existing relatively common display panel has " In cell " technologies and " On cell " technologies, " On
Cell " technologies are that touch panel function is embedded between color membrane substrates and Polarizer, and " In cell " technologies are by touch surface
Plate function is embedded between array base palte and color membrane substrates." in In cell " technologies, the integrated process route of array base palte with
The integrated process route of non-touch-control function is identical, generally sets two metal layers, and layer of metal walks gate line, in addition layer of metal
Walk touch-control line and data wire.
Because touch-control line and data wire are set in same metal level, touch-control line and data wire use identical metal, and
Wiring is completed in same manufacturing process, thus, touch-control line is identical with the resistance of data wire.Wherein, in order to ensure display surface
The sensitive and accurate touch control characteristics of plate, it is desirable to which touch-control line has relatively low resistance, based on this, cause what is connected up using same metal
The resistance of data wire is also very low, now, inserts touching signals in picture at 120 hz, then re-enter display signal when
Wait, the high current that data wire has moment causes H-line (horizontal horizontal line occurs in display panel), influences the display of display panel
Performance reliability.
Therefore it provides a kind of array base palte and preparation method thereof and display panel, improve display panel display performance reliable
Property is this area urgent problem to be solved.
The content of the invention
In view of this, the invention provides a kind of array base palte and preparation method thereof and display panel, raising is solved aobvious
Show the technical problem of Display panel performance reliability.
A kind of bright array base palte of offer of this law, including：
Substrate；
The first metal layer of the substrate side is arranged at, wherein, the first metal layer is used to set gate line sum
According to line, first direction cabling of the gate line along the substrate surface, second party of the data wire along the substrate surface
To cabling, the data wire disconnects forming multiple data line segments in the position intersected with the gate line, the first direction with
The second direction is vertical；
First insulating barrier of the first metal layer away from the substrate side is arranged at, wherein, first insulating barrier
It is provided with multiple first vias；
Second metal layer of first insulating barrier away from the first metal layer side is arranged at, wherein, described second
Metal level is used to set touch-control line and data bridge line, and the data bridge line connects the data wire by first via
Two adjacent data line segments, the resistance for forming the metal of the second metal layer is less than the metal for forming the first metal layer
Resistance.
Optionally, the array base palte includes viewing area and rim area, and the array base palte also includes：
The gate driving circuit of the rim area is arranged at, the gate driving circuit includes many signal lines, the letter
Number line includes being arranged at the first signal line segment of the first metal layer and is arranged at the secondary signal line of the second metal layer
Section, the first signal line segment is connected with the secondary signal line segment by first via.
Optionally, the array base palte includes multiple sub-pixels in matrix distribution, and the gate line is positioned at along described the
Between two row sub-pixels of one direction arrangement, the data line bit is between the two row sub-pixels arranged along the second direction；
The touch-control line is identical with the bearing of trend of the data wire, described tactile between the row sub-pixel of identical two
Control line and the data wire in said first direction spaced a predetermined distance.
Optionally, thin film transistor (TFT) is provided with the array base palte, the first metal layer is additionally operable to set described thin
The grid of film transistor, the second metal layer is additionally operable to set source electrode and the drain electrode of the thin film transistor (TFT)；
The array base palte also includes：
The first electrode layer set with the second metal layer with layer, wherein, the first electrode layer is used to set pixel
Electrode, the pixel electrode is connected with the drain electrode of the thin film transistor (TFT)；
Second insulating barrier of the second metal layer away from the first insulating barrier side is arranged at, wherein, described second
Insulating barrier is provided with multiple second vias；
The second electrode lay of second insulating barrier away from the second metal layer side is arranged at, wherein, described second
Electrode layer is used to set multiple touch control electrodes in array distribution, and the touch control electrode is touched via second via connection is described
Control line.
Optionally, the touch control electrode is multiplexed with public electrode, the public electrode and pixel electricity in the display stage
Pole constitutes pixel capacitance.
Optionally, the touch control electrode covers multiple sub-pixels；
A data wire is provided between the every two rows sub-pixel arranged along the second direction, at interval of three
A touch-control line is provided with after the data wire.
Optionally, the data bridge line is identical with the bearing of trend of the touch-control line, and the data bridge line is located at
In the second direction between two adjacent sub-pixels, so that the data bridge line insulate with the touch-control line.
Optionally, the preset distance is 1um to 2um.
Also a kind of preparation method of array base palte of the present invention, including：
One substrate is set；
In the substrate side, the first metal layer is set；
The first metal layer is performed etching, gate line and data wire is formed, wherein, the gate line is along the substrate
The first direction cabling of plate face, second direction cabling of the data wire along the substrate surface, the data wire with it is described
The position that gate line intersects disconnects forming multiple data line segments, and the first direction is vertical with the second direction；
First insulating barrier is set on the first metal layer；
First insulating barrier is punched to form multiple first vias；
Second metal layer is set on first insulating barrier；
The second metal layer is performed etching, touch-control line and data bridge line is formed, wherein, the data bridge line leads to
Cross first via and connect two adjacent data line segments of the data wire, form the resistance of the metal of the second metal layer
Less than the resistance for the metal for forming the first metal layer.
Optionally, the array base palte includes viewing area and rim area, and the array base palte also includes being arranged at the side
The gate driving circuit in frame area, the gate driving circuit is connected with the gate line, grid described in the gate driving circuit
Pole drive circuit includes many signal lines, and the signal wire includes the first signal line segment and secondary signal line segment；
Performed etching to the first metal layer, in the step of forming gate line and data wire, to first metal
Layer is performed etching, and while forming gate line and data wire, also forms the first signal line segment；
Performed etching to the second metal layer, in the step of forming touch-control line and data bridge line, to described second
Metal level is performed etching, and while forming touch-control line and data bridge line, also forms the secondary signal line segment, wherein, it is described
First signal line segment is connected with the secondary signal line segment by first via.
Optionally, the array base palte includes multiple sub-pixels in matrix distribution, and the gate line is positioned at along described the
Between two row sub-pixels of one direction arrangement, the data line bit is between the two row sub-pixels arranged along the second direction；
The touch-control line is identical with the bearing of trend of the data wire, described tactile between the row sub-pixel of identical two
Control line and the data wire spaced a predetermined distance.
Optionally, it is provided with thin film transistor (TFT) on the array base palte；
Performed etching to the first metal layer, in the step of forming gate line and data wire, to first metal
Layer is performed etching, and while forming gate line and data wire, also forms the grid of the thin film transistor (TFT)；
Performed etching to the second metal layer, in the step of forming touch-control line and data bridge line, to described second
Metal level is performed etching, and while forming touch-control line and data bridge line, also forms source electrode and the drain electrode of the thin film transistor (TFT)；
The manufacture method of the array base palte also includes：
Performed etching to the second metal layer, form touch-control line, data bridge line, the source electrode of the thin film transistor (TFT)
After drain electrode, first electrode layer is being set with the position of layer with the second metal layer；
The first electrode layer is performed etching to form pixel electrode, wherein, the pixel electrode and the film crystal
The drain electrode of pipe is connected；
The second insulating barrier is set in the second metal layer and the first electrode layer；
Punching is carried out to second insulating barrier and forms multiple second vias；
The second electrode lay is set on second insulating barrier；
The multiple touch control electrodes to be formed in array distribution are performed etching to the second electrode lay, wherein, the touch-control electricity
Pole connects the touch-control line via second via.
Optionally, the touch control electrode is multiplexed with public electrode, the public electrode and pixel electricity in the display stage
Pole constitutes pixel capacitance.
Optionally, the touch control electrode covers multiple sub-pixels；
A data wire is provided between the every two rows sub-pixel arranged along the second direction, at interval of three
A touch-control line is provided with after the data wire.
Optionally, the data bridge line is identical with the bearing of trend of the touch-control line, and the data bridge line is located at
On the first direction between two adjacent sub-pixels, so that the data bridge line insulate with the touch-control line.
Optionally, the preset distance is 1um to 2um.
The present invention also provides a kind of display panel, including above-mentioned array base palte.
Compared with prior art, array base palte of the invention and preparation method thereof and display panel, realizing following has
Beneficial effect：
The array base palte that the present invention is provided, sets gate line and data wire to be connected up in the first metal layer, set touch-control line and
Data bridge line is connected up in second metal layer, in gate line and the crossover location of data wire, and data wire disconnects in the first metal layer,
Connected by the data bridge line of second metal layer, the transmission of data line signal is ensure that by way of bridge is connected, also,
Because most of data wire and touch-control line be not in the metallic resistance of the second metal layer where same metal level, settable touch-control line
It is smaller to meet touch controllable function requirement, the performance of touch-control sensing is lifted, for data wire, most of cabling is arranged on first
Metal level, only small part data bridge line are arranged on second metal layer, set the first metal layer metal resistance can with it is normal
The resistance of data wire is identical in rule design, or the resistance of metal of increase the first metal layer that can also be suitably makes up setting
In the small resistor of the data bridge line of second metal layer, it is ensured that overall resistance is sufficiently large on data wire, display panel is from touch-control
When phase of sensitization is switched to the display stage, the high current of moment is not had on data wire, it is ensured that the display performance of display panel
Reliability.
By referring to the drawings to the detailed description of the exemplary embodiment of the present invention, further feature of the invention and its
Advantage will be made apparent from.
Brief description of the drawings
The accompanying drawing for being combined in the description and constituting a part for specification shows embodiments of the invention, and even
It is used for the principle for explaining the present invention together with its explanation.
Fig. 1 is the film layer structure schematic diagram of array base palte provided in an embodiment of the present invention；
Fig. 2 is schematic wiring diagram in the first metal layer of array base palte provided in an embodiment of the present invention；
Fig. 3 is the data wire bridge cabling schematic cross-section of array base palte provided in an embodiment of the present invention；
Fig. 4 is signal wire via connection diagram in array base palte rim area provided in an embodiment of the present invention；
Fig. 5 is the touch-control line arrangement schematic diagram of array base palte provided in an embodiment of the present invention；
Fig. 6 is a kind of film layer schematic diagram of embodiment of array base palte provided in an embodiment of the present invention；
Fig. 7 is the schematic top plan view of array base palte provided in an embodiment of the present invention；
Fig. 8 is the schematic cross-sectional view of array base palte at hatching line location A；
Fig. 9 is the schematic cross-sectional view of array base palte at hatching line B location；
Figure 10 is the touch control electrode arrangement schematic diagram of array base palte provided in an embodiment of the present invention；
Figure 11 is the preparation method flow chart of array base palte provided in an embodiment of the present invention；
Figure 12 is a kind of flow chart of optional embodiment of preparation method of array base palte provided in an embodiment of the present invention；
Figure 13 is the flow chart of another optional embodiment of preparation method of array base palte provided in an embodiment of the present invention.
Embodiment
The various exemplary embodiments of the present invention are described in detail now with reference to accompanying drawing.It should be noted that：Unless had in addition
Body illustrates that the part and the positioned opposite of step, numerical expression and numerical value otherwise illustrated in these embodiments does not limit this
The scope of invention.
The description only actually at least one exemplary embodiment is illustrative below, never as to the present invention
And its any limitation applied or used.
It may be not discussed in detail for technology, method and apparatus known to person of ordinary skill in the relevant, but suitable
In the case of, the technology, method and apparatus should be considered as a part for specification.
In shown here and discussion all examples, any occurrence should be construed as merely exemplary, without
It is as limitation.Therefore, other examples of exemplary embodiment can have different values.
It should be noted that：Similar label and letter represents similar terms in following accompanying drawing, therefore, once a certain Xiang Yi
It is defined, then it need not be further discussed in subsequent accompanying drawing in individual accompanying drawing.
The embodiment of the present invention provides a kind of array base palte, the film layer structure schematic diagram of array base palte as shown in figure 1, including：
Substrate 101, is arranged at the first metal layer 102 of the side of substrate 101, is arranged at the first metal layer 102 away from the side of substrate 101
First insulating barrier 103, is arranged at second metal layer 104 of first insulating barrier 103 away from the side of the first metal layer 102.
The first metal layer 102 is used to set schematic wiring diagram in gate line 105 and data wire 106, the first metal layer to refer to
Fig. 2, first direction a cabling of the gate line 105 along substrate surface, second direction b cabling of the data wire 106 along substrate surface, number
Disconnect forming multiple data line segments in the position intersected with gate line 105 according to line 106, first direction a is vertical with second direction b.
Gate line is used to transmit gated sweep signal, and data wire is used to transmitting data-signal, and gate line and data wire are the
One metal layer routes, and gate line is vertical with the direction of routing of data wire, in order to ensure that gate line and data wire be not short-circuit, if
Put data wire and be the position disconnection that gate line intersects, data wire forms multiple data line segments in a second direction.
Data wire bridge cabling schematic cross-section in the first insulating barrier 103 as shown in figure 3, be provided with multiple first vias
K1.Second metal layer 104 is used to set touch-control line (not shown) and data bridge line 108, and data bridge line 108 passes through the
Two adjacent data line segments of one via K1 connection data wires 106, the resistance of the metal of formation second metal layer 104, which is less than, to be formed
The resistance of the metal of the first metal layer 102.
As shown in figure 3, the data wire 106 for being arranged at the first metal layer 102 disconnects shape in the position intersected with gate line 105
Into multiple data line segments, the data bridge line 108 for being arranged at second metal layer 104 is connected in first by the first via K1
Two adjacent data line segments of the data wire 106 of metal level 102.
Touch-control line and data bridge line are set in second metal layer, data bridge line is located at first by the connection of the first via
Two adjacent data line segments of the data wire of metal level, data wire is turned on by way of bridge.Form the gold of second metal layer
The resistance of category is less than the resistance for the metal for forming the first metal layer, forms the resistance of the metal of the first metal layer and can be set with conventional
The resistance of the metal of the first metal layer used in meter is identical, or can also be suitably increase the first metal layer metal electricity
Resistance.
The array base palte that the present invention is provided, sets gate line and data wire to be connected up in the first metal layer, set touch-control line and
Data bridge line is connected up in second metal layer, in gate line and the crossover location of data wire, and data wire disconnects in the first metal layer,
Connected by the data bridge line of second metal layer, the transmission of data line signal is ensure that by way of bridge is connected, also,
Because most of data wire and touch-control line be not in the metallic resistance of the second metal layer where same metal level, settable touch-control line
It is smaller to meet touch controllable function requirement, the performance of touch-control sensing is lifted, for data wire, most of cabling is arranged on first
Metal level, only small part data bridge line are arranged on second metal layer, set the first metal layer metal resistance can with it is normal
The resistance of data wire is identical in rule design, or the resistance of metal of increase the first metal layer that can also be suitably makes up setting
In the small resistor of the data bridge line of second metal layer, it is ensured that overall resistance is sufficiently large on data wire, display panel is from touch-control
When phase of sensitization is switched to the display stage, the high current of moment is not had on data wire, it is ensured that the display performance of display panel
Reliability.
Further, in some optional embodiments, array base palte provided in an embodiment of the present invention includes viewing area
And rim area, array base palte also includes：The gate driving circuit of rim area is arranged at, gate driving circuit includes many bars
Line, signal wire includes being arranged at the first signal line segment of the first metal layer and is arranged at the secondary signal line segment of second metal layer,
First signal line segment is connected with secondary signal line segment by the first via.
Specifically, gate driving circuit signal wire via connection diagram is as shown in figure 4, be arranged at the of the first metal layer
One signal line segment X1 and the secondary signal line segment X2 of second metal layer is arranged at by being arranged on the first mistake of the first insulating barrier 103
Hole K1 connections.
The signal wire of design frame region gate driving circuit directly passes through between the first metal layer and second metal layer
First via is connected, and does not pass through indium and tin oxide film layer during thread-changing with conventional design compared with, it is to avoid 8585 test that (temperature is
85 degrees Celsius, relative humidity is that 85%) and during use, steam, which enters frame glue, causes the electrochemical corrosion in thread-changing hole, is influenceed
Array base palte performance.
Further, in some optional embodiments, as shown in figure 5, it is in matrix distribution that array base palte, which includes multiple,
Sub-pixel sp, gate line 105 is located between two row sub-pixel sp of a arrangements in the first direction, and data wire 106 is located at along second
Between two row sub-pixel sp of direction b arrangements；Touch-control line 107 is identical with the bearing of trend of data wire 106, positioned at the row of identical two
Touch-control line 107 and data wire 106 between sub-pixel d spaced a predetermined distance on a in a first direction, it is preferred that predetermined distance d is
1um to 2um.
Location of C is data bridge line link position, data bridge line 108 and the bearing of trend phase of touch-control line 107 in Fig. 5
Together, and data bridge line 108 is located at the upper two adjacent sons of second direction b as between sp elements, so that data bridge line 108 with it is tactile
Control line 107 insulate.
Data wire is arranged on the first metal layer cabling, and touch-control line is arranged on second metal layer cabling, sets and is located at identical
Touch-control line and data wire between two row sub-pixels be in a first direction spaced a predetermined distance, it is to avoid touch-control line and data wire it
Between signal interfere, can be touch-control line and data while compared with when touch-control line and data wire are arranged at same metal level
The spacing distance of line in a first direction foreshortens to 1um to 2um, hence it is evident that shorten the distance between touch-control line and data wire, as
Plain area's transmission area increase, effectively increases aperture opening ratio.
Further, in some optional embodiments, array base palte film layer schematic diagram provided in an embodiment of the present invention
As shown in fig. 6, including：Substrate 101, is arranged at the first metal layer 102 of the side of substrate 101, is arranged at the first metal layer 102 remote
From the first insulating barrier 103 of the side of substrate 101, second gold medal of first insulating barrier 103 away from the side of the first metal layer 102 is arranged at
Belong to layer 104, the first electrode layer (not shown) set with second metal layer with layer is arranged at second metal layer 104 away from first
Second insulating barrier 109 of the side of insulating barrier 103, is arranged at second electricity of second insulating barrier 109 away from the side of second metal layer 104
Pole layer 110.
Specifically, with reference to Fig. 7 to Fig. 9, Fig. 7 is the schematic top plan view of array base palte provided in an embodiment of the present invention, and Fig. 8 is
The schematic cross-sectional view of array base palte at hatching line location A, Fig. 9 is the schematic cross-sectional view of array base palte at hatching line B location.
The schematic top plan view of array base palte is as shown in fig. 7, be provided with thin film transistor (TFT) on array base palte, the first metal layer
102 are provided with gate line 105 and data wire 106, are additionally provided with the grid 111 of thin film transistor (TFT), and second metal layer 104 is provided with
Touch-control line 107 and data bridge line 108, also set up source electrode 112 and the drain electrode 113 of thin film transistor (TFT), wherein data bridge line 108
Pass through two adjacent data line segments of the first via K1 connection data wires 106；The first electrode set with second metal layer with layer
Layer is used to set pixel electrode 114, and pixel electrode 114 is connected with the drain electrode 113 of thin film transistor (TFT)；It is arranged at second metal layer
104 the second insulating barriers 109 away from the side of the first insulating barrier 103 have multiple second via K2；It is arranged at the second insulating barrier 109 remote
The second electrode lay from the side of second metal layer 104 is used to set multiple touch control electrode (not shown) in array distribution, touch-control
Electrode is via the second via K2 connections touch-control line 107.
The film for being arranged at the first metal layer is shown at hatching line location A in the schematic cross-sectional view of array base palte such as Fig. 8, figure
The grid 111 of transistor, is arranged at source electrode 112 and the drain electrode 113 of second metal layer, the pixel electrode being connected with drain electrode 113
114, the touch-control line 107 of second metal layer is arranged at, touch-control electricity of second insulating barrier 109 away from second metal layer side is arranged at
Pole 115.
The data for being arranged at the first metal layer are shown at hatching line B location in the schematic cross-sectional view of array base palte such as Fig. 9, figure
Line 106, is arranged at the touch-control line 107 of second metal layer, the pixel electrode 114 set with second metal layer with layer, is arranged at
Touch control electrode 115 of two insulating barriers 109 away from second metal layer side.
The array base palte film layer structure that the present embodiment is provided is few, is conducive to making the array base palte being thinned, while only existing
First insulating barrier and the second insulating barrier set via to connect, and the few manufacturing process of via is simple.
Further, in some optional embodiments, touch control electrode is multiplexed with public electrode in the display stage, public
Electrode constitutes pixel capacitance with pixel electrode.Touch control electrode is multiplexed with public electrode in the display stage, realizes embedded touch work(
While energy, the thickness of array base palte can be thinned.
In some optional embodiments, the touch control electrode arrangement of array base palte provided in an embodiment of the present invention is such as schemed
Shown in 10, array base palte includes the multiple touch control electrodes 115 arranged in m n array, and wherein m and n are the integer (figure more than 1
In with m=4, exemplified by n=3).Each touch control electrode 115 connects at least one touch-control line 107 and (one is exemplarily illustrated in figure
Bar), touch control electrode 115 and touch-control line 107 can be realized by via K2 and electrically connected.Touch-control line 107 leads to non-display area with touching
The electrical connection of driving chip (not shown) is controlled, touch-control driving chip is used to provide touch scanning signals for touch control electrode 115, and
The touch control detection signal exported according to touch control electrode 115 carries out touch control detection.The touch-control driving chip can be with display driving core
Piece is provided separately, and can also be integrated into same chip.
Touch control electrode 115 is multiplexed with public electrode in the display stage, in the display stage, applies public to each public electrode
Voltage, public electrode and the electricity for being arranged at the liquid crystal molecule rotation formed between the pixel electrode in sub-pixel in driving liquid crystal layer
；In the touch-control stage, touching signals are applied respectively to each touch control electrode, is detected by self-capacitance mode and is transferred to touch-control driving
The capacitance variations in each touch control electrode in circuit, to realize touch control detection.It should be noted that the embodiment of the present invention is to touching
The concrete shape of control electrode 115 is not limited, and can be rectangle, windmill-shape or any irregular figure.
Further, in some optional embodiments, touch control electrode covers multiple sub-pixels；Arrange in a second direction
Every two rows sub-pixel between be provided with a data line, at interval of being provided with a touch-control line after three data lines.Touch
Control electrode and cover multiple sub-pixels, in array distribution, at interval of a touch-control line is provided with after three data lines, meet touch-control
Aperture opening ratio is ensure that while accuracy of detection.
The real embodiment explanation that a kind of preparation method of array base palte is also provided of the invention, below with regard to above-mentioned array base palte
Preparation method is introduced, those skilled in the art when understanding technical solution of the present invention, on array base palte embodiment and
On the embodiment of the preparation method of array base palte, can mutually it refer to.
The preparation method of array base palte provided in an embodiment of the present invention, flow chart refers to Figure 11, including：
Step S101：One substrate is set.
Step S102：In substrate side, the first metal layer is set.
Step S103：The first metal layer is performed etching, gate line and data wire is formed, wherein, gate line is along substrate plate
The first direction cabling in face, second direction cabling of the data wire along substrate surface, data wire is disconnected in the position intersected with gate line
Open form is into multiple data line segments, and first direction is vertical with second direction.
Step S104：First insulating barrier is set on the first metal layer.
Step S105：First insulating barrier is punched to form multiple first vias.
Step S106：Second metal layer is set on the first insulating barrier, and the resistance for forming the metal of second metal layer is less than
Form the resistance of the metal of the first metal layer.
Step S107：Second metal layer is performed etching, touch-control line and data bridge line is formed, wherein, data bridge line
Two adjacent data line segments of data wire are connected by the first via.
The array base palte that the embodiment is provided, sets gate line and data wire to be connected up in the first metal layer, sets touch-control line
Connected up with data bridge line in second metal layer, data bridge line connects the data wire positioned at the first metal layer by the first via
Two adjacent data line segments, ensure that the transmission of data line signal, and form the second metal by way of bridge is connected
The resistance of the metal of layer is less than the resistance for the metal for forming the first metal layer, sets the resistance of the metal of touch-control line small, Neng Gouti
The performance of touch-control sensing is risen, most of cabling of data wire is arranged on the first metal layer, and only small part data bridge line is set
In second metal layer, set the resistance of the metal of the first metal layer identical with resistance in conventional design, or can also be suitably
The resistance for increasing the metal of the first metal layer makes up the small resistor for the data bridge line for being arranged on second metal layer, it is ensured that data
Overall resistance is sufficiently large on line, and display panel does not have wink from when being switched to the display stage in the touch-control sensing stage on data wire
Between high current, it is ensured that the display performance reliability of display panel.
Further, in some optional embodiments, array base palte includes viewing area and rim area, and array base palte is also
Gate driving circuit including being arranged at rim area, gate driving circuit is connected with gate line, and gate driving circuit grid drives
Dynamic circuit includes many signal lines, and signal wire includes the first signal line segment and secondary signal line segment；It is provided in an embodiment of the present invention
The preparation method of array base palte, flow chart is as shown in figure 12, including：
Step S201：One substrate is set.
Step S202：In substrate side, the first metal layer is set.
Step S203：The first metal layer is performed etching, gate line and data wire is formed, meanwhile, also form the first signal
Line segment, wherein, first direction cabling of the gate line along substrate surface, second direction cabling of the data wire along substrate surface, data
Line disconnects forming multiple data line segments with the position that gate line intersects, and first direction is vertical with second direction.
Step S204：First insulating barrier is set on the first metal layer.
Step S205：First insulating barrier is punched to form multiple first vias.
Step S206：Second metal layer is set on the first insulating barrier, and the resistance for forming the metal of second metal layer is less than
Form the resistance of the metal of the first metal layer.
Step S207：Second metal layer is performed etching, touch-control line and data bridge line is formed, meanwhile, also form second
Signal line segment, wherein, the first signal line segment is connected with secondary signal line segment by the first via, and data bridge line passes through the first mistake
Two adjacent data line segments of hole connection data wire.
The signal wire of rim area gate driving circuit is designed between the first metal layer and second metal layer directly by the
One via is connected, and does not pass through indium and tin oxide film layer during thread-changing with conventional design compared with, it is to avoid 8585 (temperature is Celsius for 85
Degree, during relative humidity is 85%) test and use, steam, which enters frame glue, causes the electrochemical corrosion in thread-changing hole, influences battle array
Row substrate performance.
Further, in some optional embodiments, array base palte includes multiple sub-pixels in matrix distribution, grid
Polar curve is located between the two row sub-pixels arranged in the first direction, data line bit in the two row sub-pixels arranged in a second direction it
Between；Touch-control line is identical with the bearing of trend of data wire, touch-control line and data wire interval between the row sub-pixel of identical two
Preset distance, it is preferred that preset distance is 1um to 2um.
Further, in some optional embodiments, data bridge line is identical with the bearing of trend of touch-control line, and number
It is located at according to bridge line between two sub-pixels adjacent on first direction, so that data bridge line insulate with touch-control line.
Data wire is arranged on the first metal layer cabling, and touch-control line is arranged on second metal layer cabling, sets and is located at identical
Touch-control line and data wire between two row sub-pixels be in a first direction spaced a predetermined distance, it is to avoid touch-control line and data wire it
Between signal interfere, can be touch-control line and data while compared with when touch-control line and data wire are arranged at same metal level
The spacing distance of line in a first direction foreshortens to 1um to 2um, hence it is evident that shorten the distance between touch-control line and data wire, as
Plain area's transmission area increase, effectively increases aperture opening ratio.
Further, in some optional embodiments, thin film transistor (TFT) is provided with array base palte；The present invention is implemented
The preparation method for the array base palte that example is provided, flow chart is as shown in figure 13, including：
Step S301：One substrate is set.
Step S302：In substrate side, the first metal layer is set.
Step S303：The first metal layer is performed etching, gate line and data wire is formed, meanwhile, also form film crystal
The grid of pipe, wherein, first direction cabling of the gate line along substrate surface, second direction cabling of the data wire along substrate surface,
Data wire disconnects forming multiple data line segments with the position that gate line intersects, and first direction is vertical with second direction.
Step S304：First insulating barrier is set on the first metal layer.
Step S305：First insulating barrier is punched to form multiple first vias.
Step S306：Second metal layer is set on the first insulating barrier, and the resistance for forming the metal of second metal layer is less than
Form the resistance of the metal of the first metal layer.
Step S307：Second metal layer is performed etching, while forming touch-control line and data bridge line, film is also formed
The source electrode of transistor and drain electrode, wherein, data bridge line connects two adjacent data line segments of data wire by the first via.
Step S308：First electrode layer is being set with the position of layer with second metal layer；
Step S309：First electrode layer is performed etching to form pixel electrode, wherein, pixel electrode and thin film transistor (TFT)
Drain electrode is connected；
Step S310：Second insulating barrier is set in second metal layer and first electrode layer；
Step S311：Punching is carried out to the second insulating barrier and forms multiple second vias；
Step S312：The second electrode lay is set over the second dielectric；
Step S313：The multiple touch control electrodes to be formed in array distribution are performed etching to the second electrode lay, wherein, touch-control electricity
Pole connects touch-control line via the second via.
The array base palte film layer structure that the present embodiment is provided is few, is conducive to making the array base palte being thinned, while only existing
First insulating barrier and the second insulating barrier set via to connect, and the few manufacturing process of via is simple.
Further, in some optional embodiments, touch control electrode is multiplexed with public electrode in the display stage, public
Electrode constitutes pixel capacitance with pixel electrode.Touch control electrode is multiplexed with public electrode in the display stage, realizes embedded touch work(
While energy, the thickness of array base palte can be thinned.
Further, in some optional embodiments, touch control electrode covers multiple sub-pixels；Arrange in a second direction
Every two rows sub-pixel between be provided with a data line, at interval of being provided with a touch-control line after three data lines.Touch
Control electrode and cover multiple sub-pixels, in array distribution, at interval of a touch-control line is provided with after three data lines, meet touch-control
Aperture opening ratio is ensure that while accuracy of detection.
The embodiment of the present invention also provides a kind of display panel, including the array base palte described in above-described embodiment.The display surface
Plate display performance good reliability, pixel region transmission area is big, and aperture opening ratio is high.
By above-described embodiment, display panel and display panel testing method of the invention, having reached following has
Beneficial effect：
(1) array base palte that the present invention is provided, sets gate line and data wire to be connected up in the first metal layer, sets touch-control line
Connected up with data bridge line in second metal layer, in gate line and the crossover location of data wire, data wire is disconnected in the first metal layer
Open, connected by the data bridge line of second metal layer, the transmission of data line signal is ensure that by way of bridge is connected, and
And, due to most of data wire with touch-control line not in the metal of the second metal layer where same metal level, settable touch-control line
Resistance is smaller to meet touch controllable function requirement, lifts the performance of touch-control sensing, for data wire, most of cabling is arranged on
The first metal layer, only small part data bridge line are arranged on second metal layer, set the resistance of the metal of the first metal layer can
It is identical with the resistance of data wire in conventional design, or the resistance of metal of increase the first metal layer that can also be suitably makes up
Be arranged on the small resistor of the data bridge line of second metal layer, it is ensured that overall resistance is sufficiently large on data wire, display panel from
When the touch-control sensing stage is switched to the display stage, the high current of moment is not had on data wire, it is ensured that the display of display panel
Performance reliability.
(2) signal wire of design gate driving circuit directly passes through the first mistake between the first metal layer and second metal layer
Hole is connected, and does not pass through indium and tin oxide film layer during thread-changing with conventional design compared with, it is to avoid 8585 (temperature is 85 degrees Celsius,
Relative humidity be 85%) test and use during, steam enter frame glue cause thread-changing hole electrochemical corrosion influence array base
Plate performance.
(3) data wire is arranged on the first metal layer cabling, and touch-control line is arranged on second metal layer cabling, sets positioned at identical
Two row sub-pixels between touch-control line and data wire in a first direction spaced a predetermined distance, it is to avoid touch-control line and data wire
Between signal interfere, while compared with when touch-control line and data wire are arranged at same metal level, hence it is evident that shorten touch-control line
The distance between with data wire, the increase of pixel region transmission area effectively increases aperture opening ratio.
Although some specific embodiments of the present invention are described in detail by example, the skill of this area
Art personnel are it should be understood that example above is merely to illustrate, the scope being not intended to be limiting of the invention.The skill of this area
Art personnel to above example it should be understood that can modify without departing from the scope and spirit of the present invention.This hair
Bright scope is defined by the following claims.
Claims (17)
1. a kind of array base palte, it is characterised in that including：
Substrate；
The first metal layer of the substrate side is arranged at, wherein, the first metal layer is used to set gate line and data wire,
First direction cabling of the gate line along the substrate surface, second direction of the data wire along the substrate surface is walked
Line, the data wire disconnects forming multiple data line segments in the position intersected with the gate line, the first direction with it is described
Second direction is vertical；
First insulating barrier of the first metal layer away from the substrate side is arranged at, wherein, first insulating barrier is set
There are multiple first vias；
Second metal layer of first insulating barrier away from the first metal layer side is arranged at, wherein, second metal
Layer is used to set touch-control line and data bridge line, and it is adjacent that the data bridge line connects the data wire by first via
Two data line segments, the resistance for forming the metal of the second metal layer is less than the electricity for the metal for forming the first metal layer
Resistance.
2. array base palte according to claim 1, it is characterised in that the array base palte includes viewing area and rim area,
The array base palte also includes：
The gate driving circuit of the rim area is arranged at, the gate driving circuit includes many signal lines, the signal wire
Including being arranged at the first signal line segment of the first metal layer and being arranged at the secondary signal line segment of the second metal layer, institute
The first signal line segment is stated to be connected by first via with the secondary signal line segment.
3. array base palte according to claim 1, it is characterised in that
The array base palte includes multiple sub-pixels in matrix distribution, and the gate line is located at what is arranged along the first direction
Between two row sub-pixels, the data line bit is between the two row sub-pixels arranged along the second direction；
The touch-control line is identical with the bearing of trend of the data wire, the touch-control line between the row sub-pixel of identical two
With the data wire in said first direction spaced a predetermined distance.
4. array base palte according to claim 3, it is characterised in that
Thin film transistor (TFT) is provided with the array base palte, the first metal layer is additionally operable to set the grid of the thin film transistor (TFT)
Pole, the second metal layer is additionally operable to set source electrode and the drain electrode of the thin film transistor (TFT)；
The array base palte also includes：
The first electrode layer set with the second metal layer with layer, wherein, the first electrode layer is used to set pixel electrode,
The pixel electrode is connected with the drain electrode of the thin film transistor (TFT)；
Second insulating barrier of the second metal layer away from the first insulating barrier side is arranged at, wherein, second insulation
Layer is provided with multiple second vias；
The second electrode lay of second insulating barrier away from the second metal layer side is arranged at, wherein, the second electrode
Layer is used to set multiple touch control electrodes in array distribution, and the touch control electrode connects the touch-control via second via
Line.
5. array base palte according to claim 4, it is characterised in that the touch control electrode is multiplexed with public in the display stage
Electrode, the public electrode constitutes pixel capacitance with the pixel electrode.
6. array base palte according to claim 4, it is characterised in that
The touch control electrode covers multiple sub-pixels；
A data wire is provided between the every two rows sub-pixel arranged along the second direction, at interval of described in three
A touch-control line is provided with after data wire.
7. array base palte according to claim 3, it is characterised in that the data bridge line and the extension of the touch-control line
Direction is identical, and the data bridge line is located between two sub-pixels adjacent in the second direction, so that the data
Bridge line insulate with the touch-control line.
8. array base palte according to claim 3, it is characterised in that the preset distance is 1um to 2um.
9. a kind of preparation method of array base palte, it is characterised in that including：
One substrate is set；
In the substrate side, the first metal layer is set；
The first metal layer is performed etching, gate line and data wire is formed, wherein, the gate line is along the substrate surface
First direction cabling, second direction cabling of the data wire along the substrate surface, the data wire with the grid
The position that line intersects disconnects forming multiple data line segments, and the first direction is vertical with the second direction；
First insulating barrier is set on the first metal layer；
First insulating barrier is punched to form multiple first vias；
Second metal layer is set on first insulating barrier；
The second metal layer is performed etching, touch-control line and data bridge line is formed, wherein, the data bridge line passes through institute
State the first via and connect two adjacent data line segments of the data wire, the resistance for forming the metal of the second metal layer is less than
Form the resistance of the metal of the first metal layer.
10. the preparation method of array base palte according to claim 9, it is characterised in that
The array base palte includes viewing area and rim area, and the grid that the array base palte also includes being arranged at the rim area drives
Dynamic circuit, the gate driving circuit is connected with the gate line, gate driving circuit bag described in the gate driving circuit
Many signal lines are included, the signal wire includes the first signal line segment and secondary signal line segment；
Perform etching, in the step of forming gate line and data wire, the first metal layer is entered to the first metal layer
Row etching, while forming gate line and data wire, also forms the first signal line segment；
Performed etching to the second metal layer, in the step of forming touch-control line and data bridge line, to second metal
Layer is performed etching, and while forming touch-control line and data bridge line, also forms the secondary signal line segment, wherein, described first
Signal line segment is connected with the secondary signal line segment by first via.
11. the preparation method of array base palte according to claim 9, it is characterised in that
The array base palte includes multiple sub-pixels in matrix distribution, and the gate line is located at what is arranged along the first direction
Between two row sub-pixels, the data line bit is between the two row sub-pixels arranged along the second direction；
The touch-control line is identical with the bearing of trend of the data wire, the touch-control line between the row sub-pixel of identical two
With the data wire spaced a predetermined distance.
12. the preparation method of array base palte according to claim 11, it is characterised in that
Thin film transistor (TFT) is provided with the array base palte；
Perform etching, in the step of forming gate line and data wire, the first metal layer is entered to the first metal layer
Row etching, while forming gate line and data wire, also forms the grid of the thin film transistor (TFT)；
Performed etching to the second metal layer, in the step of forming touch-control line and data bridge line, to second metal
Layer is performed etching, and while forming touch-control line and data bridge line, also forms source electrode and the drain electrode of the thin film transistor (TFT)；
The manufacture method of the array base palte also includes：
Performed etching to the second metal layer, form touch-control line, data bridge line, the source electrode of the thin film transistor (TFT) and leakage
After pole, first electrode layer is being set with the position of layer with the second metal layer；
The first electrode layer is performed etching to form pixel electrode, wherein, the pixel electrode and the thin film transistor (TFT)
Drain electrode is connected；
The second insulating barrier is set in the second metal layer and the first electrode layer；
Punching is carried out to second insulating barrier and forms multiple second vias；
The second electrode lay is set on second insulating barrier；
The multiple touch control electrodes to be formed in array distribution are performed etching to the second electrode lay, wherein, the touch control electrode warp
The touch-control line is connected by second via.
13. the preparation method of array base palte according to claim 12, it is characterised in that the touch control electrode is in display rank
Section is multiplexed with public electrode, and the public electrode constitutes pixel capacitance with the pixel electrode.
14. the preparation method of array base palte according to claim 12, it is characterised in that
The touch control electrode covers multiple sub-pixels；
A data wire is provided between the every two rows sub-pixel arranged along the second direction, at interval of described in three
A touch-control line is provided with after data wire.
15. the preparation method of array base palte according to claim 11, it is characterised in that the data bridge line with it is described
The bearing of trend of touch-control line is identical, and the data bridge line is located between two sub-pixels adjacent on the first direction,
So that the data bridge line insulate with the touch-control line.
16. the preparation method of array base palte according to claim 11, it is characterised in that the preset distance be 1um extremely
2um。
17. a kind of display panel, it is characterised in that including the array base palte described in any one of claim 1 to 9.
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