CN106876330A - A kind of array base palte and preparation method thereof, display panel and display device - Google Patents
A kind of array base palte and preparation method thereof, display panel and display device Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 82
- 239000002184 metal Substances 0.000 claims description 106
- 229910052751 metal Inorganic materials 0.000 claims description 106
- 230000004888 barrier function Effects 0.000 claims description 62
- 239000000758 substrate Substances 0.000 claims description 20
- 230000008569 process Effects 0.000 abstract description 60
- 238000000059 patterning Methods 0.000 abstract description 38
- 238000004519 manufacturing process Methods 0.000 abstract description 19
- 239000010408 film Substances 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000003086 colorant Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract
The embodiment of the invention provides a kind of array base palte and preparation method thereof, display panel and display device, set with layer by by drain electrode, source electrode, data wire and touch-control cabling, so as to avoid being separately provided film layer where touch-control cabling, so as to make touch-control routing layer by corresponding patterning processes without using single mask plate；And, also directly it is electrically connected with the case where via is not passed through with drain electrode by by pixel electrode, so that without carrying out hole quarter by the patterning processes of mask plate；And then eliminate mask plate patterning processes twice.Therefore, technical scheme provided in an embodiment of the present invention can simplify the manufacturing process of array base palte, reduce technological process complexity, reduce mask plate usage quantity, low production cost.
Description
【Technical field】
The present invention relates to technical field of touch control, more particularly to a kind of array base palte and preparation method thereof, display panel and aobvious
Showing device.
【Background technology】
With the development of technical field of touch control, the display panel with touch controllable function has increasingly becomed main flow display and has produced
Product.The integration mode of existing display panel and contact panel is generally divided into in-cell (embedded) and on-cell (the outer formula of box)
Two ways, in-cell touch-screens are more frivolous compared to for on-cell touch-screens.At present, the in-cell of prior art
The array base palte of touch-screen at least includes gate metal layer, semiconductor layer, source-drain electrode metal level, the first silicon nitride layer, pixel electricity
Pole, touch-control metal level, the second silicon nitride layer and public electrode.
Inventor has found that at least there are the following problems in the prior art：
In the prior art in the preparation process of array base palte, above-mentioned gate metal layer, semiconductor layer, source-drain electrode gold are being formed
When category layer, the first insulating barrier, pixel electrode, touch-control metal level, the second insulating barrier and public electrode, every layer is required to using independent
Mask plate made by corresponding patterning processes, technological process is complex, it is necessary to the more mask plate of usage quantity, raw
Produce high cost.
【The content of the invention】
In view of this, a kind of array base palte and preparation method thereof, display panel and display dress be the embodiment of the invention provides
Put, the usage quantity of mask plate can be reduced, simplify the manufacturing process of array base palte.
On the one hand, a kind of array base palte is the embodiment of the invention provides, including：
Underlay substrate；
The first metal layer on the underlay substrate, the first metal layer includes grid and grid line；
Active layer on the first metal layer；
Pixel electrode in film layer where the grid and grid line；
Second metal layer on the active layer and the pixel electrode, the second metal layer includes drain electrode, source
Pole and data wire, wherein, the drain electrode is electrically connected with the pixel electrode；
Common electrode layer in the second metal layer, the common electrode layer includes multiple with array way setting
Public electrode block, the public electrode block is multiplexed with touch control electrode；The array base palte also includes：
Touch-control cabling, positioned at the second metal layer；The touch-control cabling and the drain electrode, source electrode, data wire and pixel
Electrode is electrically insulated, and is electrically connected with the public electrode block of the common electrode layer by via.
Specifically, the array base palte also includes：
First insulating barrier, between the first metal layer and the active layer.
Specifically, the array base palte also includes：
Second insulating barrier, between the common electrode layer and the second metal layer；Set on second insulating barrier
There is via.
Specifically, the drain electrode is directly electrically connected with the pixel electrode.
Specifically, the touch-control cabling is disposed adjacent with the data wire, and the touch-control cabling is flat with the data wire
OK.
On the other hand, a kind of display panel is the embodiment of the invention provides, including：Above-mentioned array base palte.
On the other hand, a kind of display device is the embodiment of the invention provides, including：Above-mentioned display panel.
On the other hand, a kind of preparation method of array base palte is the embodiment of the invention provides, including：
The first metal layer is formed in underlay substrate, the first metal layer includes grid and grid line；
Active layer is formed on the first metal layer；
Pixel electrode is formed in film layer where the grid and grid line；,
Second metal layer and touch-control cabling are formed on the active layer and the pixel electrode, wherein, second gold medal
Belong to layer and including the second metal layer where the drain electrode, source electrode and data wire, wherein, it is described to drain and the pixel electrode
It is electrically connected with；
The second insulating barrier of covering second metal layer is formed, via is formed on second insulating barrier；Described second
Common electrode layer is formed on metal level, wherein, the common electrode layer includes multiple public electrode blocks set with array way,
The public electrode block is multiplexed with touch control electrode, and the public electrode block is electrically connected by the via with the touch-control cabling
Connect.
Specifically, methods described also includes：
The first insulating barrier is formed between the first metal layer and the active layer.
Specifically, methods described also includes：
The second insulating barrier is formed between the common electrode layer and the second metal layer, and in second insulating barrier
Upper formation via.
Specifically, the drain electrode is directly electrically connected with the pixel electrode.
Specifically, the touch-control cabling is disposed adjacent with the data wire, and the touch-control cabling is flat with the data wire
OK.
A technical scheme in above-mentioned technical proposal has the advantages that：
A kind of array base palte and preparation method thereof, display panel and display device are the embodiment of the invention provides, by inciting somebody to action
Drain electrode, source electrode, data wire and touch-control cabling are set with layer, it is to avoid be separately provided film layer where touch-control cabling, therefore without using list
Only mask plate simultaneously makes touch-control routing layer by corresponding patterning processes, can simplify the manufacturing process of array base palte, drops
Low technological process complexity, reduces mask plate usage quantity, low production cost.
【Brief description of the drawings】
Technical scheme in order to illustrate more clearly the embodiments of the present invention, below will be attached to what is used needed for embodiment
Figure is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this area
For those of ordinary skill, without having to pay creative labor, can also obtain other attached according to these accompanying drawings
Figure.
Fig. 1 is a kind of structural representation of pixel cell on a kind of array base palte that the embodiment of the present invention is provided；
Fig. 2 be in Fig. 1 AA ' to cross-sectional view；
Fig. 3 is the structural representation of another pixel cell on a kind of array base palte that the embodiment of the present invention is provided；
A kind of the step of preparation method of array base palte that Fig. 4 is provided by the embodiment of the present invention schematic diagram；
A kind of the step of preparation method of array base palte that Fig. 5 is provided by the embodiment of the present invention schematic diagram；
A kind of structural representation of display panel that Fig. 6 is provided by the embodiment of the present invention；
A kind of structural representation of display device that Fig. 7 is provided by the embodiment of the present invention.
【Specific embodiment】
In order to be better understood from technical scheme, the embodiment of the present invention is retouched in detail below in conjunction with the accompanying drawings
State.
It will be appreciated that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Base
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of creative work is not made it is all its
Its embodiment, belongs to the scope of protection of the invention.
The term for using in embodiments of the present invention is the purpose only merely for description specific embodiment, and is not intended to be limiting
The present invention." one kind ", " described " and " being somebody's turn to do " of singulative used in the embodiment of the present invention and appended claims
It is also intended to include most forms, unless context clearly shows that other implications.
It will be appreciated that though insulation may be described using term first, second, third, etc. in embodiments of the present invention
Layer, but these insulating barriers should not necessarily be limited by these terms.These terms are only used for being distinguished from each other open insulating barrier.For example, not taking off
In the case of range of embodiment of the invention, the first insulating barrier can also be referred to as the second insulating barrier, similarly, the second insulating barrier
The first insulating barrier can also be referred to as.
As depicted in figs. 1 and 2, a kind of pixel cell on a kind of array base palte that Fig. 1 is provided by the embodiment of the present invention
Structural representation, Fig. 2 by Fig. 1 AA ' to cross-sectional view, a kind of array bases for being provided for inventive embodiments of Fig. 3
The structural representation of another pixel cell on plate, the present invention provides a kind of array base palte, including：Underlay substrate 1；Positioned at substrate
The first metal layer 2 on substrate 1, the first metal layer includes grid 21 and grid line 22；Active layer 3 on the first metal layer 2；
Pixel electrode 4 on grid 21 and the place film layer of grid line 22；Second metal layer on active layer 3 and pixel electrode 4
5, second metal layer 5 includes drain electrode 51, source electrode 52 and data wire 53, wherein, drain electrode 51 is electrically connected with pixel electrode 4；It is located at
Common electrode layer 6 in second metal layer 5, common electrode layer 6 includes multiple public electrode blocks set with array way, public
Electrode block is multiplexed with touch control electrode；Touch-control cabling 7, positioned at second metal layer 5；Touch-control cabling 7 and drain electrode 51, source electrode 52, data
Line 53 and pixel electrode 4 are electrically insulated, and the public electrode block electric connection for passing through via 91 and common electrode layer 6.Wherein, battle array
Row substrate includes intersecting the multiple sub-pixel units for limiting by multirow grid line and multiple columns of data lines, in each sub-pixel unit,
, respectively positioned at the both sides of active layer, grid is oppositely arranged with the channel region of active layer for source electrode and drain electrode, source electrode, drain electrode, active
Layer and grid form the thin film transistor (TFT) (Thin Film Transistor, TFT) in array base palte.
It should be noted that each public electrode corresponds to a touch-control cabling respectively in Fig. 1 and Fig. 3, in real process,
It is far smaller than display precision for the requirement of touch accuracy, therefore a public electrode can be to that should have multiple sub-pixels, each
Public electrode is electrically connected by via with a touch-control cabling.In embodiment shown in Fig. 1, two adjacent data lines 53 and phase
Adjacent two grid lines 22 intersection surrounds a sub-pixel.The sub-pixel unit of adjacent multiple different colours may be constructed a picture
Plain unit, for example, an adjacent in the row direction red sub-pixel, a green sub-pixels and blue subpixels can be with
A pixel is constituted, the multiple sub-pixels in a pixel can carry out the display of different colours according to the difference of GTG.Production
In, for different design requirements, the quantity of public electrode is adjustable, and under identical situation, the quantity of public electrode is got over
Many, the corresponding sub-pixel quantity of each public electrode is fewer, because each public electrode still corresponds to a touch-control cabling, so
The quantity of touch-control cabling and via also can accordingly increase.
With reference to Fig. 1 and Fig. 3, it can be seen that in the case of other structures all same, in Fig. 1 implementation methods, per height picture
Element is correspondingly arranged a public electrode, and in Fig. 3, each pixel, i.e., every three sub-pixels are correspondingly arranged a public electrode,
Public electrode quantity in Fig. 1 implementation methods is more than the public electrode quantity in Fig. 3 implementation methods, correspondingly, Fig. 1 implementation methods
Quantity of the quantity of middle touch-control cabling and via also greater than touch-control cabling and via in Fig. 3 implementation methods.Each pixel in Fig. 3
Unit one touch-control cabling of correspondence, correspondingly, each pixel cell correspondence one is used to connect touch-control cabling and public electrode block
Via, pixel cell include line direction on three sub-pixels of different colours, reduce via quantity, with simplify make battle array
The complexity of row substrate process.
It should be noted that the present embodiment is only schematically illustrated, in actual implementation process, in an array base palte
In, the block public electrode in the matrix arrangement of m*n, wherein m can be included>2, n>2, and m, n are natural number, and the bulk
Public electrode is preferably rectangular.Each block public electrode can be corresponded to and cover i*j subpixel area, wherein i>2, j>2, and
I, j are natural number.Because in the display stage, each public electrode needs to form electric field and pixel electrode between, therefore, each
Public electrode needs to cover the open area of each sub-pixel, i.e. the slit formed between two neighboring public electrode, vertical
In on the direction of plane where array base palte, with scan line or data line overlap.Each public electrode block passes through a touch-control
Cabling is connected to driving chip, and in the display stage, driving chip is input into common electrode signal to each public electrode, with this and respectively
Electric field is formed between individual pixel electrode.In the touch-control stage, driving chip is to each public electrode while or timesharing input touch-control
Signal, position of touch is detected by detecting the change of the self-capacitance on each public electrode, namely touch control electrode.Due to each
Public electrode is arranged in arrays, and each public electrode is connected to driving chip, Ke Yitong by corresponding touch-control cabling respectively
When detect on each public electrode self-capacitance change, with this realize multi-point touch detect.
In array base palte in the present embodiment, drain electrode, source electrode, data wire and touch-control cabling are set with layer, by once
The patterning processes of mask plate can be formed includes the second metal layer of drain electrode, source electrode, data wire and touch-control cabling, it is to avoid individually set
Film layer where putting touch-control cabling, touch-control routing layer, energy are made by corresponding patterning processes without using single mask plate
Enough simplify the manufacturing process of array base palte, reduce technological process complexity, reduce mask plate usage quantity, low production cost.
Alternatively, as shown in Figure 1-Figure 3, above-mentioned array base palte also includes：First insulating barrier 8, positioned at first metal
Between layer 2 and the active layer 3.First insulating barrier is used to completely cut off grid and semiconductor layer and second metal layer, and the present invention is real
The first insulating barrier for applying example forms pattern without using the patterning processes of mask plate, in real process, if desired first
Insulating barrier is formed correspondingly pattern and can be also patterned by extra mask plate, and the above does not limit protection model of the invention
Enclose.
Wherein, because the first insulating barrier of array base palte in the present embodiment is not provided with via, therefore mask plate need not be passed through
Patterning processes carry out hole quarter, so as to reducing a patterning processes, can simplify the manufacturing process of array base palte, reduce technique
Flow complexity, reduces mask plate usage quantity, low production cost.
Alternatively, as shown in Figure 1-Figure 3, above-mentioned array base palte also includes：Second insulating barrier 9, positioned at the public electrode
Between layer 6 and the second metal layer 5；Second insulating barrier 9 is provided with via 91.Second insulating barrier is used to completely cut off second metal layer
And common electrode layer, the touch-control cabling needs of second metal layer connect the public electrode block of common electrode layer, on the second insulating barrier
Via is provided with, therefore the second insulating barrier needs to carry out hole quarter by the patterning processes of mask plate.
In actual production process, the outer peripheral areas of viewing area are being surrounded, various cablings are being often provided with, for example, grid
The cabling of the signal lead of drive circuit cabling, connection driving chip and data wire, connection touch-control cabling and driving chip.Non-
When viewing area connects up, the first metal layer and second metal layer thread-changing electrical connection are often realized into different signals and is passed
Transmission function.Due to the first insulating barrier after coating, via etch is not carried out, now, to connection the first metal layer and second
Metal level, can be realized by increasing a patterning processes.The structure of via 91 can also be carried out on the second insulating barrier 9 jointly
In the step of figure technique, while the deep via through the first insulating barrier 8 and the second insulating barrier 9 is formed, now, the deep via exposure
Part is needed to realize the first metal layer of thread-changing, is formed in the second insulating barrier and via 91 is with the shallow via of layer, needed with expose portion
The second metal layer of thread-changing is realized, the connection electrode with public electrode with layer, first are deposited in the deep via and shallow via
Metal level and second metal layer realize electrical connection by the connection electrode through deep via and shallow via.Now, composition is not increased
Technique, does not increase the process time.
It should be noted that the material of the first insulating barrier and/or the second insulating barrier is silicon nitride (SiNx) and silica
(SiOx) any one in.
Alternatively, the drain electrode 51 is directly electrically connected with the pixel electrode 4.Specifically as shown in Figure 1-Figure 3, pixel electricity
Pole is located at the top of film layer where grid and grid line, is directly electrically connected with by overlapping mode between pixel electrode and drain electrode, and
Without being connected with wire by way of separately setting via, the manufacturing process of array base palte can be simplified, reduce technological process complicated
Degree.
Below by the relative position relation to touch-control cabling and data wire, the touch-control to the embodiment of the present invention walks line position
Implementation method illustrate.
Alternatively, the touch-control cabling 7 is disposed adjacent with data wire 53, and touch-control cabling 7 is parallel with the data wire 53.
Specific the touch-control cabling 7 is disposed adjacent and is parallel to each other with data wire 53 as shown in Figure 1-Figure 3, while the two is positioned at same
Film layer, simplifies the complexity for making array base palte technique.And because both be arranged in parallel, can be in the opposed of array base palte
The light-shielding structure for covering data wire and touch-control cabling simultaneously is formed on substrate, the influence by touch-control cabling to showing transmitance is down to
It is minimum.
Array base palte in the embodiment of the present invention, is set by by drain electrode, source electrode, data wire and touch-control cabling with layer, keeps away
Exempt to be separately provided film layer where touch-control cabling, therefore make tactile without using single mask plate and by corresponding patterning processes
Control routing layer, reduces by a mask plate patterning processes；Meanwhile, by by pixel electrode with drain electrode not pass through via in the case of
Directly it is electrically connected with, hole quarter is carried out without the patterning processes by mask plate, reduces by a mask plate patterning processes again；From
And, the manufacturing process of array base palte can be simplified, technological process complexity is reduced, mask plate usage quantity is reduced, it is produced into
This is low.
On the other hand, as shown in figure 4, being based on same inventive concept, the embodiment of the invention provides a kind of array base palte
Preparation method, including：
Step 410, the first metal layer is formed on underlay substrate, the first metal layer includes grid and grid line.
Specifically, step 410 is by first mask plate patterning processes the first metal layer on underlay substrate, then the
One metal level covers the first insulating barrier, because the first insulating barrier need not carry out hole etching, therefore without using mask plate patterning processes,
First insulating barrier is located between the first metal layer and active layer, it is ensured that be electrically insulated between grid and source-drain electrode.
Step 420, on the first metal layer form active layer.
Specifically, step 420 forms active layer, active layer on the first metal layer by second mask plate patterning processes
That is semiconductor layer, it is located on the first metal layer, while being also located on the first insulating barrier, active layer is based on correspondence grid voltage
Size selection is switched on or off source-drain electrode.
Step 430, in film layer where the grid and grid line form pixel electrode.
Specifically, step 430 is formed by the 3rd road mask plate patterning processes in film layer where the grid and grid line
Pixel electrode, pixel electrode is located on the first insulating barrier.Step 440, is formed on the active layer and the pixel electrode
Two metal levels and touch-control cabling, wherein, the second metal layer includes drain electrode, source electrode and data wire, the drain electrode and the picture
Plain electrode is electrically connected with.
Specifically, step 440 passes through the 4th road mask plate patterning processes shape on the active layer and the pixel electrode
Into second metal layer and touch-control cabling, touch-control cabling is electrically insulated with drain electrode, source electrode, data wire and pixel electrode, touch-control cabling
Set with layer with second metal layer, therefore eliminate one mask plate patterning processes, the side between drain electrode and pixel electrode to overlap
Formula is directly electrically connected with.In addition, touch-control cabling is disposed adjacent with data wire, and touch-control cabling is parallel with data wire.
Step 450, the second insulating barrier for forming covering second metal layer, via is formed on second insulating barrier.
Specifically, the second insulating barrier is coated with second metal layer and film layer where touch-control cabling, step 450 passes through the 5th
Road mask plate patterning processes etch to form via in hole over the second dielectric, and the via is located at touch-control cabling top.
Step 460, in the second metal layer common electrode layer is formed, wherein, the common electrode layer includes multiple
With the public electrode block that array way is set, the public electrode block is multiplexed with touch control electrode, and the public electrode block passes through institute
Via is stated to be electrically connected with the touch-control cabling.Specifically, is provided between the common electrode layer and affiliated second metal layer
Two insulating barriers, the public electrode block is electrically connected with by the via in the second insulating barrier and touch-control cabling.
On the basis of the preparation method based on above-mentioned array base palte, below the preparation method of array substrate carry out in detail
Explanation.Specifically as described in Figure 5, the detailed step of above-mentioned preparation method is specific as follows：
Step 1, on underlay substrate 1 formed include the first metal layer 2 of grid and grid line；
Wherein, by first time mask plate patterning processes, being formed on underlay substrate 1 includes the first gold medal of grid and grid line
Category layer 2, grid and grid line are electrically connected with.The technique for forming the first metal layer can be that one layer first is first deposited on underlay substrate
Metal material layer, the deposition process of the first metal material layer can be the methods such as sputtering, can be with deposited metal in the prior art
The method of layer is identical, will not be repeated here.Then photoresist is coated on the first metal material layer, using first mask plate pair
Photoresist is exposed.After end exposure, developing process is carried out, in developing process, the photoresist of exposed portion is washed away, not
The photoresist of exposed portion still remains in the first metal material layer top.The first metal material layer for exposing is entered after development
Row wet etching, the part not being etched is the part for being photo-etched glue protection, and the partial pattern carries out the first metal layer.Finally
Photoresist lift off is carried out, the patterning process of the first metal layer is to terminate.
Step 2, the first insulating barrier 8 is formed on the first metal layer 2 where grid and grid line；
Wherein, the first insulating barrier 8 is not provided with via, therefore without carrying out hole quarter by mask plate patterning processes.
Step 3, the formation active layer 3 on the first insulating barrier 8；
Wherein, by second mask plate patterning processes, active layer 3 is formed on the first insulating barrier 8.Likewise, active
The formation of layer is also required to by coating semiconductor material layer, such as figure photoresist, photoresist exposure imaging, etching, stripping photoresist
Etc. process.From unlike formation the first metal layer, the etching of semiconductor material layer typically uses dry etching.Its etching technics
It is identical with prior art with etching material, will not be repeated here.
Step 4, the formation pixel electrode 4 on the first metal layer 2 where grid and grid line；
Wherein, by third time mask plate patterning processes, picture is being formed on the first metal layer 2 where grid and grid line
Plain electrode 4.Pixel electrode 4 and active layer 3 are respectively positioned on the top of the first insulation 8, the forming process of pixel electrode and the first metal
The forming process of layer is similar to, and will not be repeated here.
Step 5, formation second metal layer 5 and the touch-control cabling 7 on active layer 3 and pixel electrode 4, second metal layer 5 are wrapped
Include drain electrode 51, source electrode 52 and data wire；
Wherein, by the 4th mask plate patterning processes, the He of second metal layer 5 is formed on active layer 3 and pixel electrode 4
Touch-control cabling 7, second metal layer 5 includes drain electrode 51, source electrode 52 and data wire, and touch-control cabling is disposed adjacent with data wire, and touches
Control cabling is parallel with the data wire, and second metal layer 5 and touch-control cabling 7 are set with layer, it is possible to reduce one time mask plate is used
Number of times；Directly it is electrically connected with by overlapping mode between drain electrode 51 and pixel electrode 4, so as to reduce a mask plate again use
Number of times.Second metal layer is similar with the forming process of the first metal layer with the forming process of touch-control cabling, will not be repeated here.
Alternatively, the touch-control cabling 7 is disposed adjacent with data wire 53, and touch-control cabling 7 is parallel with the data wire 53.
Specific the touch-control cabling 7 is disposed adjacent and is parallel to each other with data wire 53 as shown in Figure 1-Figure 3, while the two is positioned at same
Film layer, simplifies the complexity for making array base palte technique.And because both be arranged in parallel, can be in the opposed of array base palte
The light-shielding structure for covering data wire and touch-control cabling simultaneously is formed on substrate, the influence by touch-control cabling to showing transmitance is down to
It is minimum.Step 6, second insulation of the formation comprising the via 91 for spilling touch-control cabling 7 in second metal layer 5 and touch-control cabling 7
Layer 9；
Wherein, by the 5th mask plate patterning processes, the via for spilling touch-control cabling 7 is formed in the second insulating barrier 9
91.The forming method of the second insulating barrier 9 is identical with the forming method of active layer, will not be repeated here.
In actual production process, the outer peripheral areas of viewing area are being surrounded, various cablings are being often provided with, for example, grid
The cabling of the signal lead of drive circuit cabling, connection driving chip and data wire, connection touch-control cabling and driving chip.Non-
When viewing area connects up, the first metal layer and second metal layer thread-changing electrical connection are often realized into different signals and is passed
Transmission function.Due to the first insulating barrier after coating, via etch is not carried out, now, to connection the first metal layer and second
Metal level, can be realized by increasing a patterning processes.The structure of via 91 can also be carried out on the second insulating barrier 9 jointly
In the step of figure technique, while the deep via through the first insulating barrier 8 and the second insulating barrier 9 is formed, now, the deep via exposure
Part is needed to realize the first metal layer of thread-changing, is formed in the second insulating barrier and via 91 is with the shallow via of layer, needed with expose portion
The second metal layer of thread-changing is realized, the connection electrode with public electrode with layer, first are deposited in the deep via and shallow via
Metal level and second metal layer realize electrical connection by the connection electrode through deep via and shallow via.Now, composition is not increased
Technique, does not increase the process time.
Step 7, the formation common electrode layer 6 in second metal layer 5；
Wherein, by the 6th mask plate patterning processes, common electrode layer 6, public electrode are formed in second metal layer 5
Layer includes multiple public electrode blocks set with array way, and public electrode block is multiplexed with touch control electrode, the public affairs of common electrode layer 6
Common electrode block is electrically connected with by via 91 with touch-control cabling 7.
To sum up, in embodiments of the present invention in the preparation method of array base palte, 6 mask plate patterning processes need to be only used,
With need 8-10 mask plate patterning processes to compare in prior art preparation method, reduce mask plate usage quantity, simplify
The manufacturing process of array base palte, reduces technological process complexity.
As shown in fig. 6, the embodiment of the present invention also provides a kind of liquid crystal display panel, including above-mentioned array base palte 610, coloured silk
Ilm substrate 620 and liquid crystal layer 630.
Wherein, the concrete structure and principle of array base palte 610 are same as the previously described embodiments, will not be repeated here.
Liquid crystal display panel in the present embodiment, by the drain electrode of the array base palte in liquid crystal display panel, source electrode, data
Line and touch-control cabling are set with layer, so as to avoid being separately provided film layer where touch-control cabling；And, pixel electrode is with drain electrode not
Directly it is electrically connected with the case of by via, so that without carrying out hole quarter by the patterning processes of mask plate；And then save
Mask plate patterning processes, therefore, it is possible to simplify the manufacturing process of array base palte, reduce technological process complexity twice, reduce
Mask plate usage quantity, low production cost.
As shown in fig. 7, the embodiment of the present invention also provides a kind of display device, including above-mentioned liquid crystal display panel 700.
Wherein, the concrete structure and principle of liquid crystal display panel 700 are same as the previously described embodiments, will not be repeated here.It is aobvious
Showing device can be such as touch display screen, mobile phone, tablet PC, notebook computer, any tool of electric paper book or television set etc.
There is the electronic equipment of crystal display.
Display device in the present embodiment, by the drain electrode of the array base palte in liquid crystal display panel, source electrode, data wire and
Touch-control cabling is set with layer, so as to avoid being separately provided film layer where touch-control cabling；And, pixel electrode is not passing through with drain electrode
Directly it is electrically connected with the case of via, so that without carrying out hole quarter by the patterning processes of mask plate；And then eliminate two
Secondary mask plate patterning processes, therefore, it is possible to simplify the manufacturing process of array base palte, reduce technological process complexity, reduce mask
Version usage quantity, low production cost.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Within god and principle, any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (12)
1. a kind of array base palte, it is characterised in that including：
Underlay substrate；
The first metal layer on the underlay substrate, the first metal layer includes grid and grid line；
Active layer on the first metal layer；
Pixel electrode in film layer where the grid and grid line；
Second metal layer on the active layer and the pixel electrode, the second metal layer include drain electrode, source electrode and
Data wire, wherein, the drain electrode is electrically connected with the pixel electrode；
Common electrode layer in the second metal layer, the common electrode layer includes multiple public affairs set with array way
Common electrode block, the public electrode block is multiplexed with touch control electrode；The array base palte also includes：
Touch-control cabling, positioned at the second metal layer；The touch-control cabling and the drain electrode, source electrode, data wire and pixel electrode
It is electrically insulated, and is electrically connected with the public electrode block of the common electrode layer by via.
2. array base palte as claimed in claim 1, it is characterised in that the array base palte also includes：
First insulating barrier, between the first metal layer and the active layer.
3. array base palte as claimed in claim 1, it is characterised in that the array base palte also includes：
Second insulating barrier, between the common electrode layer and the second metal layer；Second insulating barrier was provided with
Hole.
4. array base palte as claimed in claim 1, it is characterised in that the drain electrode directly electrically connects with the pixel electrode
Connect.
5. array base palte as claimed in claim 1, it is characterised in that the touch-control cabling is disposed adjacent with the data wire,
And the touch-control cabling is parallel with the data wire.
6. a kind of display panel, it is characterised in that including the array base palte as described in any one of Claims 1 to 5.
7. a kind of display device, it is characterised in that including display panel as claimed in claim 6.
8. a kind of preparation method of array base palte as claimed in claim 1, it is characterised in that including：
The first metal layer is formed on underlay substrate, the first metal layer includes grid and grid line；
Active layer is formed on the first metal layer；
Pixel electrode is formed in film layer where the grid and grid line；
Second metal layer and touch-control cabling are formed on the active layer and the pixel electrode, wherein, the second metal layer
Including drain electrode, source electrode and data wire, the drain electrode is electrically connected with the pixel electrode；
The second insulating barrier of the covering second metal layer is formed, via is formed on second insulating barrier；
Common electrode layer is formed in the second metal layer, wherein, the common electrode layer includes that multiple is set with array way
The public electrode block put, the public electrode block is multiplexed with touch control electrode, the public electrode block by the via with it is described
Touch-control cabling is electrically connected with.
9. the preparation method of array base palte as claimed in claim 8, it is characterised in that methods described also includes：
The first insulating barrier is formed between the first metal layer and the active layer.
10. the preparation method of array base palte as claimed in claim 8, it is characterised in that methods described also includes：
The second insulating barrier, and the shape on second insulating barrier are formed between the common electrode layer and the second metal layer
Into via.
The preparation method of 11. array base paltes as claimed in claim 8, it is characterised in that the drain electrode and the pixel electrode
Directly it is electrically connected with.
The preparation method of 12. array base paltes as claimed in claim 8, it is characterised in that the touch-control cabling and the data
Line is disposed adjacent, and the touch-control cabling is parallel with the data wire.
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| CN108682653A (en) * | 2018-04-28 | 2018-10-19 | 武汉华星光电技术有限公司 | Array substrate and preparation method thereof |
| CN109683743A (en) * | 2018-12-24 | 2019-04-26 | 武汉华星光电技术有限公司 | A kind of touch-control display panel and electronic device |
| CN110516637A (en) * | 2019-08-30 | 2019-11-29 | 上海中航光电子有限公司 | Array substrate and preparation method thereof, display device |
| WO2020133808A1 (en) * | 2018-12-29 | 2020-07-02 | 武汉华星光电技术有限公司 | Array substrate and manufacture method therefor |
| CN111367431A (en) * | 2020-02-25 | 2020-07-03 | 京东方科技集团股份有限公司 | Array substrate and display device |
| US10896921B2 (en) | 2018-04-28 | 2021-01-19 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Manufacturing method of array substrate |
| CN114078401A (en) * | 2021-11-12 | 2022-02-22 | 武汉华星光电半导体显示技术有限公司 | Touch control integrated Micro-LED display panel |
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Application publication date: 20170620 |