CN201654096U

CN201654096U - Equivalent sampling oscilloscope based on external delay technology

Info

Publication number: CN201654096U
Application number: CN2010201668703U
Authority: CN
Inventors: 杨静竹; 刘思勤; 徐安莹; 姜帅; 陶启成
Original assignee: Wuhan University WHU
Current assignee: Wuhan University WHU
Priority date: 2010-04-16
Filing date: 2010-04-16
Publication date: 2010-11-24
Anticipated expiration: 2020-04-16

Abstract

The utility model relates to the technical field of oscilloscope design and particularly relates to an equivalent sampling oscilloscope based on external delay technology. The equivalent sampling oscilloscope based on the external delay technology comprises a micro control system, a measuring circuit and an external delay module, wherein the micro control system is directly electrically connected with the measuring circuit and is simultaneously connected with the external delay module; the micro control system comprises a singlechip, an FPGA chip and an LCD liquid crystal display; the singlechip is bidirectionally electrically connected with the FPGA chip; the FPGA chip is also connected with the LCD liquid crystal display; the measuring circuit comprises a signal conditioning circuit, an A/D sampler and a shaping circuit. The utility model has the advantages of simple structure and convenient use, can further shorten delay time and improve equivalent sampling efficiency according to different external delay units, realizes rapid, efficient and high-precision measurement, improves sampling speed of equivalent sampling and strengthens performance of the oscilloscope.

Description

Equivalent Sample Oscilloscope based on outside delay technique

Technical field

The utility model relates to the oscilloscope design technical field, relates in particular to a kind of Equivalent Sample Oscilloscope based on outside delay technique.

Background technology

Oscillograph is a kind of electronic measuring instrument that sightless electric signal is changed into visual picture.Oscillograph needs to carry out the A/D sampling to measuring electric signal in the course of the work, and in the process that high-frequency signal is sampled, because it is limited that A/D transforms the sample rate of chip, often realize the function of low speed sampling rate collection high-frequency signal, Equivalent Sample Oscilloscope that Here it is by the mode of equivalent sampling.The essence of equivalent sampling is exactly the signal to be measured n Δ t (n=0,1,2,3 that delays time successively ...) after, time-delay is each time once sampled, reply out original waveform according to the point after the sampling then, and show.

Present oscillograph often uses fpga chip as the control core, and in the inner time-delay that realizes this Δ t of FPGA.But because the restriction of the frequency of operation of FPGA (frequency of operation of FPGA is generally about 200M at present) own, this time-delay minimum can only reach 5ns, corresponding equivalent sampling frequency also can only reach 200M, and more and more higher for the oscillograph requirement of high-speed sampling rate now, the sampling rate of 200M can not meet the demands.

Technical matters at above-mentioned existence, the utility model has designed the Equivalent Sample Oscilloscope of a cover based on outside delay technique, the delay time weak point reaches 1ns, the equivalent sampling frequency is up to 1G, and can be interrupted delay time greatly by the performance that improves outside chronotron, improve sample frequency.

The utility model content

The purpose of this utility model provides a kind of Equivalent Sample Oscilloscope based on outside delay technique, utilize the equivalent sampling principle, in conjunction with the embedded system control technology, sample, measure and show at high frequency electric signal to be measured, be applicable to that people carry out effectively Measurement and analysis of high speed to electric signal.

For achieving the above object, the utility model adopts following technical scheme:

Micro control system, metering circuit, outside time delay module, described micro control system directly is electrically connected with metering circuit, and described micro control system connects outside time delay module simultaneously;

Described micro control system comprises single-chip microcomputer, fpga chip, LCD LCD, and single-chip microcomputer links to each other with the two-way electricity of fpga chip, and fpga chip connects the LCD LCD simultaneously;

Described metering circuit comprises signal conditioning circuit, A/D sampling thief and shaping circuit; The input end of described signal conditioning circuit connects signal input port, and the output terminal of signal conditioning circuit divides two-way, and one the tunnel connects the A/D sampling thief, and one the tunnel connects shaping circuit; A/D sampling thief and shaping circuit are electrically connected with fpga chip respectively.

Described outside time delay module adopts programmable Timer chip DS1023 to constitute.

Described shaping circuit is made up of amplifying circuit and comparator circuit, and wherein amplifying circuit adopts the automatic gain mode, uses chip AD603, and comparator circuit adopts the hysteresis manner of comparison, uses chip TL3116.

Described A/D sampling thief adopts high-speed sampling chip MAX1425 to constitute, and comprises input isolation circuit, filtering circuit and data bus.

The utlity model has following advantage and good effect:

1) simple and practical, easy to use, and can further shorten delay time and improve the equivalent sampling frequency according to the difference of outside chronotron;

2) realized fast that efficient, high-acruracy survey has improved the sampling rate of equivalent sampling, has strengthened oscillographic performance.

Description of drawings

Fig. 1 is the structured flowchart based on the Equivalent Sample Oscilloscope of outside delay technique that the utility model provides.

Fig. 2 is the circuit diagram of the utility model based on signal conditioning circuit in the Equivalent Sample Oscilloscope of outside delay technique.

Fig. 3 is the circuit diagram of the utility model based on shaping circuit in the Equivalent Sample Oscilloscope of outside delay technique.

Fig. 4 is the circuit diagram of the utility model based on A/D sampling thief in the Equivalent Sample Oscilloscope of outside delay technique.

Fig. 5 is the circuit diagram of the utility model based on outside time delay module in the Equivalent Sample Oscilloscope of outside delay technique.

Embodiment

The utility model is described in further detail in conjunction with the accompanying drawings with specific embodiment below:

The Equivalent Sample Oscilloscope based on outside delay technique that the utility model provides specifically adopts following technical scheme, referring to Fig. 1, comprising:

Micro control system (101,102,103), metering circuit (104,105,106), outside time delay module (107), the whole oscillographic work of micro control system (101,102,103) control, and this micro control system (101,102,103) directly links to each other with metering circuit (104,105,106), and micro control system (101,102,103) connects outside time delay module (107) simultaneously;

Micro control system (101,102,103) comprises single-chip microcomputer (101), fpga chip (102), LCD LCD (103), single-chip microcomputer (101) links to each other with the two-way electricity of fpga chip (102), and fpga chip (102) connects LCD LCD (103) simultaneously; Single-chip microcomputer (101) initialization total system, and the process of each module in control FPGA (102) show by FPGA (102) control LCD LCD (103) and to survey waveform;

Metering circuit (104,105,106) comprises signal conditioning circuit (104), A/D sampling thief (105) and shaping circuit (106); Signal conditioning circuit (104) input end connects signal input port, and signal conditioning circuit (104) output terminal divides two-way, and one the tunnel connects A/D sampling thief (105), and one the tunnel connects shaping circuit (106); A/D sampling thief (105) and shaping circuit (106) are electrically connected with fpga chip (102) respectively;

In the above-mentioned Equivalent Sample Oscilloscope based on outside delay technique, outside time delay module (107) adopts programmable Timer chip DS1023 to constitute; Shaping circuit (106) is made up of amplifying circuit and comparator circuit, and wherein amplifying circuit adopts the automatic gain mode, uses chip AD603, and comparator circuit adopts the hysteresis manner of comparison, uses chip TL3116; A/D sampling thief (105) adopts high-speed sampling chip MAX1425 to constitute, and comprises input isolation circuit, filtering circuit and data bus.

The principle of work that further describes below that the utility model provides based on the Equivalent Sample Oscilloscope of outside delay technique:

Oscillograph at first carries out signal condition to input signal, by detecting the measurement gear that the user selects, has the control program control signal modulate circuit among the FPGA to carry out the amplification of corresponding gear.As shown in Figure 2, select each gear gain by relay, relay is by Single-chip Controlling.

The bandwidth of Ths3001 has 420MHz, presses pendulum to be 6500V/us, is fit to do the broadband and amplifies.First Ths3001 and second Ths3001 adopt the homophase input to realize impedance matching, and the input impedance of Ths3001 homophase is 1.5M Ω, so insert the resistance R 1 of 3M Ω and the 1M Ω input impedance that R2 realizes two-way as shown in FIG. respectively.R3, R4, R5 and R6 constitute an attenuation network.Ths7002 can be stepping realization-22dB～20dB attenuation/gain control with 6dB, and native system is only used wherein three gain control, 2dB, 8dB and 14dB, i.e. and gain is respectively 1.25,2.5 and 5 times.Ths7002 can also be with voltage clamp in the scope of AD sampling, when preventing to import large-signal vertical sensitivity gear be provided with improperly and signal is put very large big, considerably beyond the scope of AD sampling, unfavorable to the ADC conversion chip like this.

This passage can select to be shown as interchange shelves or zero frequency span by relay S3.Because relate to zero frequency span, offset voltage that amplifier is introduced in the therefore necessary elimination passage and bias voltage etc., therefore the signal input pin in each amplifier inserts zeroing circuit, as passing through Rp zeroing among the adjusting figure.Resistance among the figure is through the numerical value that obtains after the precision measurement, a bit comes in and goes out with the actual nominal value, and be in order to obtain accurate gain like this.The 4th ths3001 realizes a totalizer among the figure, pin 2 inserts " DAC output ", be to make DC voltage of signal stack by Single-chip Controlling DAC converter, can realize that like this waveform Relative Zero level moves up and down, amplify by ths7002 again and clamp and the 5th ths3001 amplification, can intercept each part of waveform like this it is exaggerated, each portion waveshape can be clearly observed, especially sine-shaped zero crossing place and crest and trough can easily be observed.

To nurse one's health too much electric signal then and compare the shaping processing.This part core devices adopts ultrahigh-speed comparator TL3116.Input signal guarantees can both reach suitable amplitude when signal enters TL3116 through the auto-gain circuit that controllable gain amplifier AD603 constitutes like this.As Fig. 3, signal is through through entering the input end of AD603 behind the resistance-capacitance network, and the controllable gain of AD603 part is by the triode networking, and with the output of AD603 as feedback, realize automatic gain control.Signal enters TL3116 and realizes that hysteresis relatively, is shaped to square-wave signal with input signal afterwards.This square-wave signal enters FPGA, and two purposes are arranged: the one, as the input signal of frequency measurement module, with the frequency of Test input signal; The 2nd, as trigger pip, for the equivalent sampling use of back.

Electric signal after will nursing one's health simultaneously directly carries out the A/D conversion, and this process is a real-time sampling, and native system A/D sampling A adopts MAX1425, and a high-speed sampling chip carries sampling and keeps function, provides sampling to keep during for equivalent sampling.As Fig. 4, MAX1425 is 10 AD, and high sampling rate is 20MSa/s, but the high sampling rate of in fact controlling it is 1MSa/s, and only uses most-significant byte as significance bit, and promptly vertical resolution is 8bits.MAX1425 sample circuit such as Fig. 4.MAX1425 has internal voltage reference, and input signal adopts the difference input, and the difference input voltage range is-2V is to 2V, and peak-to-peak value is 4V to the maximum, and can adopt the DC coupling also can AC coupling.Native system adopts DC coupling, and adopt internal reference, the input voltage range of last MAX1425 be 0.25V to 4.25V, peak-to-peak value is 4V.Just enter into FPGA through the digital signal after the A/D conversion and carry out respective handling.

The square-wave signal of FPGA after in conjunction with control of outside time delay module and shaping before then again, control A/D sampling thief carries out equivalent sampling.As Fig. 5, the output of first delay chip links to each other with the input of second delay chip, provides enough time-delays to carry out the waveform demonstration to gather enough counting.Delay chip adopts DS1023.In a single day FPGA detects trigger pip and just controls a DS1023 generation time-delay (delay unit of DS1023 is 1ns), controls the A/D sampling thief simultaneously and once samples.Detect trigger pip next time and just control two time-delays of DS1023 generation.So go on,, just finished the process of equivalent sampling up to collecting enough counting for demonstration.

At last, under the control of single-chip microcomputer, FPGA handles sampled data, and storage is come out corresponding data by the LCD liquid crystal display displays, is convenient for measuring personnel's real-time analysis and differentiates.

Claims

1. the Equivalent Sample Oscilloscope based on outside delay technique is characterized in that, comprising:

Micro control system (101,102,103), metering circuit (104,105,106), outside time delay module (107), described micro control system (101,102,103) directly is electrically connected with metering circuit (104,105,106), and described micro control system (101,102,103) connects outside time delay module (107) simultaneously;

Described micro control system (101,102,103) comprises single-chip microcomputer (101), fpga chip (102), LCD LCD (103), single-chip microcomputer (101) links to each other with the two-way electricity of fpga chip (102), and fpga chip (102) connects LCD LCD (103) simultaneously;

Described metering circuit (104,105,106) comprises signal conditioning circuit (104), A/D sampling thief (105) and shaping circuit (106); The input end of described signal conditioning circuit (104) connects signal input port, and the output terminal of signal conditioning circuit (104) divides two-way, and one the tunnel connects A/D sampling thief (105), and one the tunnel connects shaping circuit (106); A/D sampling thief (105) and shaping circuit (106) are electrically connected with fpga chip (102) respectively.

2. the Equivalent Sample Oscilloscope based on outside delay technique according to claim 1 is characterized in that:

Described outside time delay module (107) adopts programmable Timer chip DS1023 to constitute.

3. the Equivalent Sample Oscilloscope based on outside delay technique according to claim 1 is characterized in that:

Described shaping circuit (106) is made up of amplifying circuit and comparator circuit, and wherein amplifying circuit adopts the automatic gain mode, uses chip AD603, and comparator circuit adopts the hysteresis manner of comparison, uses chip TL3116.

4. according to each described Equivalent Sample Oscilloscope in the claim 1,2,3, it is characterized in that based on outside delay technique:

Described A/D sampling thief (105) adopts high-speed sampling chip MAX1425 to constitute, and comprises input isolation circuit, filtering circuit and data bus.