CN105549453A - High-precision re-constructible digital delay line and time-delay method thereof - Google Patents
High-precision re-constructible digital delay line and time-delay method thereof Download PDFInfo
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- CN105549453A CN105549453A CN201410611609.2A CN201410611609A CN105549453A CN 105549453 A CN105549453 A CN 105549453A CN 201410611609 A CN201410611609 A CN 201410611609A CN 105549453 A CN105549453 A CN 105549453A
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Abstract
Provided in the invention is a high-precision re-constructible digital delay line comprising an A/D converter. The output terminal of the A/D converter is connected with an input terminal of a time delay unit; the input terminal of the time delay unit is connected with an output terminal of a control unit; an output terminal of the time delay unit is connected with a D/A converter. Besides, a time-delay method comprises: the A/D converter converts an inputted analog signal needing time delay into a digital signal and outputs the digital signal to a time delay unit of an FPGA; and the time delay unit sets delay time according to an instruction of the control unit and outputs the delayed digital signal to the D/A converter. The digital delay line and time-delay method have characteristics of long total delay time, high extension precision, good re-constructible performance, compact structure, and high universality.
Description
Technical field
The present invention relates to a kind of digital delay line, particularly a kind of high precision restructural digital delay line and time-delay method thereof.
Background technology
Digital delay line is used for the element of electric signal time delay a period of time or device.Digital delay line is widely used in each electron-like and communication system, as radar target echo signal simulation system, phased array radar system, time figure system and synchronous communication system etc.In general, delay cell is divided into special and general two large classes.Special lag line is as AD9501, and he adopts analog device to realize, and precision can reach 10ps level, but its dynamic range is less than 10us.Generally, there is total delay time short in dedicated delay line, postponing step-length can not adjust, and controls inflexible defect.General delay cell generally adopts programmable logic device (PLD) to realize, and has dynamic range large, the reliable advantage of simplicity of design, but it postpones the impact that precision is but subject to devices function clock, generally in ns rank.In radar target signal imitation system, phased array radar system system, require that the total delay time of delay line is much larger than 10us, and require that delay stepsize can accurate adjustment.
Summary of the invention
In order to overcome above-mentioned the deficiencies in the prior art, the object of the present invention is to provide a kind of high precision restructural digital delay line and time-delay method thereof, have total delay time long, extend that precision is high, the feature of restructural, compact conformation and highly versatile.
To achieve these goals, the technical solution used in the present invention is: a kind of high precision restructural digital delay line, include A/D converter, the output terminal of A/D converter is connected with the input end of delay unit, the input end of delay unit is connected with the output terminal of control module, and the output terminal of delay unit is connected with D/A converter.
A kind of high precision restructural digital delay method, comprises the following steps:
1) simulating signal of time delay that needs of input is converted to digital signal by A/D converter, and digital signal is exported to the delay unit in FPGA;
2) delay unit arranges delay time according to the instruction of control module, and the digital signal after time delay is exported to D/A converter;
3) digital signal after time delay is converted to analog signal output by D/A converter.
The present invention has the following advantages: owing to have employed High Performance FPGA, system can realize man-machine interaction, automatically can detect the key parameter of input simulating signal, the parameter of needs can be shown simultaneously, and carry out fault pre-diagnosing and fault real-time diagnosis according to these parameters.System changes the scheme of conventional digital delay line, adopts High Performance FPGA and two-forty, high-resolution AD and DA device, solves dedicated delay line generally, there is total delay time short, and postponing step-length can not adjust, and controls inflexible defect.Having 1) total delay time can reach more than 100ms; 2) high precision: postpone step-length precision at 5ns, the highest 380MHz of frequency input signal, input signal precision is 14bit; 3) restructural: the feature of reconstruction delay time under 5ns postpones step-length precision.This product has the feature of compact conformation, highly versatile simultaneously.
Accompanying drawing explanation
Fig. 1 is principle of the invention block diagram.
Embodiment
Below in conjunction with accompanying drawing, principle of work of the present invention is described in further detail.
See Fig. 1, a kind of high precision restructural digital delay line, include A/D converter 3, A/D converter 3 output terminal is connected with delay unit 2 input end, delay unit 2 input end is connected with control module 1 output terminal, and delay unit 2 output terminal is connected with D/A converter 4.
This digital delay wire system is based on two-forty, high-resolution AD and DA device; Adopt High Performance FPGA extensive, at a high speed.Ultimate principle as shown in Figure 1.
Described control module be responsible for delay time control and control information mutual; Delay unit is responsible for carrying out accurate time delay to data; The time delay simulating signal that needs of input is converted to digital signal by A/D converter; Digital signal after time delay is converted to analog signal output by D/A converter.
principle of work of the present invention is:
The simulating signal of time delay that needs of input is converted to digital signal by A/D converter, and delay unit digital signal exported in FPGA, delay unit arranges delay time according to the instruction of control module, digital signal after time delay is exported to D/A converter, thus completes the functional requirement will exported after the simulating signal time delay a period of time needing time delay.
A kind of high precision restructural digital delay method, comprises the following steps:
1) simulating signal of time delay that needs of input is converted to digital signal by A/D converter 3, and digital signal is exported to the delay unit 2 in FPGA;
2) delay unit 2 arranges delay time according to the instruction of control module, and the digital signal after time delay is exported to D/A converter;
3) digital signal after time delay is converted to analog signal output by D/A converter 4.
Claims (2)
1. a high precision restructural digital delay line, it is characterized in that, include A/D converter (3), the output terminal of A/D converter (3) is connected with the input end of delay unit (2), the input end of delay unit (2) is connected with the output terminal of control module (1), and the output terminal of delay unit (2) is connected with D/A converter (4).
2. a high precision restructural digital delay method, is characterized in that, comprise the following steps:
1) simulating signal of time delay that needs of input is converted to digital signal by A/D converter, and digital signal is exported to the delay unit in FPGA;
2) delay unit arranges delay time according to the instruction of control module, and the digital signal after time delay is exported to D/A converter;
3) digital signal after time delay is converted to analog signal output by D/A converter.
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Cited By (1)
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CN106200761A (en) * | 2016-07-25 | 2016-12-07 | 电子科技大学 | A kind of based on low sampling rate high-precision target range delay control method |
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CN102305928A (en) * | 2011-05-25 | 2012-01-04 | 中国电子科技集团公司第十研究所 | Dynamic target signal simulation method in transparent mode |
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Patent Citations (6)
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CN101178317A (en) * | 2007-12-04 | 2008-05-14 | 南京大学 | Adjustable sample-taking velocity high speed high-accuracy data collection card |
CN201654786U (en) * | 2009-12-31 | 2010-11-24 | 广东正业科技股份有限公司 | Programmable step delay time base and sampling system |
CN201654096U (en) * | 2010-04-16 | 2010-11-24 | 武汉大学 | Equivalent sampling oscilloscope based on external delay technology |
CN102468852A (en) * | 2010-11-09 | 2012-05-23 | 中国电子科技集团公司第五十四研究所 | High-speed analog/digital converter (AD) parallel sampling device |
CN102305928A (en) * | 2011-05-25 | 2012-01-04 | 中国电子科技集团公司第十研究所 | Dynamic target signal simulation method in transparent mode |
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CN106200761A (en) * | 2016-07-25 | 2016-12-07 | 电子科技大学 | A kind of based on low sampling rate high-precision target range delay control method |
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Application publication date: 20160504 |