CN203149029U - Overvoltage data acquisition storage system - Google Patents

Abstract

The utility model relates to an overvoltage data acquisition storage system, which comprises an operational amplifier, a filter, an analog-to-digital converter, a synchronous dynamic random access memory, a PCI interface, a clock chip, a FPGA chip and a power source; wherein, the operational amplifier, the filter, the analog-to-digital converter, the synchronous dynamic random access memory and the PCI interface are connected in order; the operational amplifier receives the overvoltage signal; the FPGA chip are respectively connected to the analog-to-digital converter and the synchronous dynamic random access memory; the power source is respectively connected to the operational amplifier, the filter and the FPGA; and the clock chip is connected to the FPGA chip. According to the utility model, the high sampling precision can be obtained on the basis of guarantee of acquisition rate, and errors such as data loss can be avoided when the outer and inner overvoltage are acquired.

Description

A kind of superpotential data acquisition storage system

Technical field

The utility model relates to a kind of superpotential data acquisition storage system.

Background technology

Transition effect shows as from a stable status excessively to the another one state.Hyper-Voltage of Power Systems is the transition effect that the abnormal voltage that surpasses normal working voltage that electric system occurs under given conditions raises, and with regard to its basic generation root, can be divided into two major types, i.e. exterior overvoltage and internal overvoltage.Exterior overvoltage claims lightning surge or atmospheric over-voltage again.Internal overvoltage is to be transformed or transmitted by the energy of electric system inside to cause.The generation of Hyper-Voltage of Power Systems is at random, and inside and outside superpotential has different characteristics: the internal overvoltage frequency spectrum is very wide, usually from tens hertz to several KHz, the exterior overvoltage wave head is steeper, amplitude is very high.Therefore, when inside and outside superpotential is gathered simultaneously, occur losing of data easily, must be in addition suitable control could improve the precision of sampling on the basis that does not influence picking rate.But existing data acquisition system (DAS) does not meet this standard.

Summary of the invention

The purpose of this utility model is to provide a kind of superpotential data acquisition storage system, by the sequential control of FPGA, on the basis that guarantees acquisition rate, making has a higher sampling precision, thereby when taking into account inside and outside superpotential and gather, avoid occurring mistakes such as losing of data.

The technical scheme that realizes above-mentioned purpose is:

A kind of superpotential data acquisition storage system, receive overvoltage signal, comprise operational amplifier, wave filter, analog to digital converter, synchronous DRAM (SDRAM), PCI(Peripheral Component Interconnect, the Peripheral Component Interconnect standard) interface, clock chip, FPGA(Field-Programmable Gate Array, field programmable gate array) chip and power supply, wherein:

Described operational amplifier, wave filter, analog to digital converter, synchronous DRAM and pci interface are connected successively;

Described operational amplifier receives described overvoltage signal;

Described fpga chip connects described analog to digital converter and synchronous DRAM respectively;

Described power supply connects described operational amplifier, wave filter and fpga chip respectively;

Described clock chip connects described fpga chip.

Above-mentioned superpotential data acquisition storage system, wherein, described power supply is accumulator.

Above-mentioned superpotential data acquisition storage system, wherein, described pci interface connects computing machine by pci bus.

The beneficial effects of the utility model are: the utility model is by the sequential control of FPGA, the digital signal of simulating signal after the analog to digital converter conversion, store in the SDRAM storer, and after the data in the SDRAM storer reach half-full state, produce look-at-me by FPGA, data are passed to computing machine by pci bus, on the basis that guarantees acquisition rate, obtain a higher sampling precision, thereby when taking into account inside and outside superpotential and gather, that avoids occurring data loses, transmits mistake such as delay.

Description of drawings

Fig. 1 is the structural representation of superpotential data acquisition storage system of the present utility model.

Embodiment

The utility model is described in further detail below in conjunction with accompanying drawing.

See also Fig. 1, the utility model superpotential data acquisition storage system comprises operational amplifier 1, wave filter 2, analog to digital converter 3, synchronous DRAM 4, pci interface 5, fpga chip 6, clock chip 7 and power supply 8, wherein:

Operational amplifier 1, wave filter 2, analog to digital converter 3, synchronous DRAM 4 and pci interface 5 are connected successively;

Operational amplifier 1 receives overvoltage signal, and this overvoltage signal is generally gathered by the high-voltage pulse voltage divider;

Fpga chip 6 is connection mode number converter 3 and synchronous DRAM 4 respectively;

Power supply 8 is concatenation operation amplifier 1, wave filter 2 and fpga chip 6 respectively, is used for power supply; In the present embodiment, power supply 8 is accumulator;

Clock chip 7 connects fpga chip 6, is used for providing clock;

Pci interface 5 connects computing machine 10 by pci bus 9.

The utility model principle of work: overvoltage signal successively through operational amplifier 1 amplify, wave filter 2 filtering and change into digital voltage signal through analog to digital converter 3, under the sequential control of fpga chip 6, digital voltage signal stored in the synchronous DRAM 4 in regular turn go, after the data in the synchronous DRAM 4 reach half-full state, fpga chip 6 produces look-at-me synchronous DRAM 4, and data are passed to computing machine 10 by pci bus 9.

In the present embodiment, the model that fpga chip 6 is selected for use is XC3S400AN; The model that clock chip 7 is selected for use is DS1302.

Above embodiment is only for the usefulness that the utility model is described, but not to restriction of the present utility model, person skilled in the relevant technique, under the situation that does not break away from spirit and scope of the present utility model, can also make various conversion or modification, therefore all technical schemes that are equal to also should belong to category of the present utility model, should be limited by each claim.

Claims (3)

1. a superpotential data acquisition storage system receives overvoltage signal, it is characterized in that, comprises operational amplifier, wave filter, analog to digital converter, synchronous DRAM, pci interface, clock chip, fpga chip and power supply, wherein:

Described operational amplifier, wave filter, analog to digital converter, synchronous DRAM and pci interface are connected successively;

Described operational amplifier receives described overvoltage signal;

Described fpga chip connects described analog to digital converter and synchronous DRAM respectively;

Described power supply connects described operational amplifier, wave filter and fpga chip respectively;

Described clock chip connects described fpga chip.

2. superpotential data acquisition storage system according to claim 1 is characterized in that, described power supply is accumulator.

3. superpotential data acquisition storage system according to claim 1 is characterized in that described pci interface connects computing machine by pci bus.