CN103809482A - High-precision data acquisition system - Google Patents
High-precision data acquisition system Download PDFInfo
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- CN103809482A CN103809482A CN201210440642.4A CN201210440642A CN103809482A CN 103809482 A CN103809482 A CN 103809482A CN 201210440642 A CN201210440642 A CN 201210440642A CN 103809482 A CN103809482 A CN 103809482A
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- data acquisition
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Abstract
The invention relates to the technical field of acquisition systems and particularly relates to a high-precision data acquisition system. The high-precision data acquisition system provided by the invention is high in sampling efficiency. The high-precision data acquisition system comprises a signal conditioning circuit, an AD chip, a level transition chip, a CPLD (Complex Programmable Logic Device) and a DSP (Digital Signal Processor). The structural key point is that the signal conditioning circuit, the AD chip, the level transition chip, the CPLD and the DSP are connected in sequence.
Description
Technical field
the invention belongs to acquisition system technical field, relate in particular to a kind of High Precise Data Acquisition System.
Background technology
in the control procedure of various high power switching power supplies, all be unable to do without the collection to simulating signal, and at present due to the appearance of various high-speed AD chips, and the improving constantly of DSP performance, how quick, high-precision sampled analog data just seems particularly important.The data acquisition system (DAS) of most based on DSP and CPLD all can be buffered in sampled data in CPLD, will cause like this data that DSP obtains may not be that current AD changes the latest data of coming, and in the system of multi-channel A/D sampling, can take in a large number the logical block in CPLD.
Summary of the invention
the present invention is exactly for the problems referred to above, and the High Precise Data Acquisition System that a kind of sampling efficiency is high is provided.
to achieve these goals, the present invention adopts following technical scheme, the present invention includes signal conditioning circuit, AD chip, level transferring chip, CPLD, DSP, its structural feature signal conditioning circuit, AD chip, level transferring chip, CPLD, DSP are connected successively.
as a kind of preferred version, AD chip of the present invention adopts MAX125.
as another kind of preferred version, DSP of the present invention adopts DSP2812.
beneficial effect of the present invention.
the application of the decoding formula data acquisition system (DAS) that the present invention adopts DSP and CPLD combination in power electronics control system, and fully verified the feasibility of the method by emulation and experiment.The method realizes state machine and FIR filtering algorithm by DSP, comes the AD of lower floor hardware to carry out and control by the instruction of CPLD decoding DSP, and data are placed directly in bus and are read for DSP.Through experimental verification, this programme can be saved the surge time of data in CPLD completely, directly reaches DSP from AD chip undelayed data, therefore can effectively improve the efficiency of sampling system.
Accompanying drawing explanation
in order to make technical matters solved by the invention, technical scheme and beneficial effect clearer, below in conjunction with the drawings and the specific embodiments, the present invention is further elaborated.Should be appreciated that embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
fig. 1 is schematic block circuit diagram of the present invention.
Embodiment
as shown in the figure, the present invention includes signal conditioning circuit, AD chip, level transferring chip, CPLD, DSP, signal conditioning circuit, AD chip, level transferring chip, CPLD, DSP are connected successively.
described AD chip adopts MAX125.
described DSP adopts DSP2812.
the present invention adopts the scheme of DSP2812 and CPLD device EPM7512 combination, and DSP2812, as the master controller of whole system, controls the work of the sampling of CPLD settling signal and digital filtering.CPLD carries out decoding to the address instruction of DSP, completes the logic control sequential of 14 AD device MAX125 by inner state machine.
xINTF interface is the exclusive peripheral hardware of TMS320281x series, it is responsible for the same storer of CPU reference-to storage logic control element, peripheral hardware and other interface to couple together, this interface comprises 19 bit address bus XA[18:0], 16 figure places 55 are according to bus XD[15:0], and various control signal (as reading and writing, sheet choosing etc.).The external interface (XINTF) of TMS320F2812 processor is mapped to 5 independently storage space: Zone0, Zone1, Zone2, Zone6 and Zone7, in the time of the corresponding storage space of access, can produce a chip selection signal; That each space can independently arrange is initial, active, the time of ending, for slow devices coupling, can also extend enlivening the time of peripheral hardware with XREADY signal simultaneously.
no matter use CPLD can well mate the control difference of injection time of DSP and peripheral AD device, be low speed AD or high-speed AD, can directly read with DSP the data that collect, and be highly susceptible to the expansion of multiple AD chips.Whole system is divided into master controller DSP, CPLD, AD chip, level transferring chip and signal conditioning circuit.
cPLD constantly monitors the address bus XA of DSP, and sheet selects XZCS and read-write, just can judge the residing state of DSP internal state machine, controls AD sampling A/D chip thereby CPLD sends corresponding control command.
be understandable that, above about specific descriptions of the present invention, only for being described, the present invention is not limited to the described technical scheme of the embodiment of the present invention, those of ordinary skill in the art is to be understood that, still can modify or be equal to replacement the present invention, to reach identical technique effect; Use needs as long as meet, all within protection scope of the present invention.
Claims (3)
1. High Precise Data Acquisition System, comprises signal conditioning circuit, AD chip, level transferring chip, CPLD, DSP, it is characterized in that signal conditioning circuit, AD chip, level transferring chip, CPLD, DSP are connected successively.
2. High Precise Data Acquisition System according to claim 1, is characterized in that described AD chip adopts MAX125.
3. High Precise Data Acquisition System according to claim 1, is characterized in that described DSP adopts DSP2812.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210440642.4A CN103809482A (en) | 2012-11-07 | 2012-11-07 | High-precision data acquisition system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210440642.4A CN103809482A (en) | 2012-11-07 | 2012-11-07 | High-precision data acquisition system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103809482A true CN103809482A (en) | 2014-05-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201210440642.4A Pending CN103809482A (en) | 2012-11-07 | 2012-11-07 | High-precision data acquisition system |
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| Country | Link |
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| CN (1) | CN103809482A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105005246A (en) * | 2015-08-12 | 2015-10-28 | 恒信大友（北京）科技有限公司 | Portable data acquisition terminal |
| CN105487439A (en) * | 2015-11-27 | 2016-04-13 | 湖北三江航天红峰控制有限公司 | Double isolation device and method for multipath AD acquisition |
-
2012
- 2012-11-07 CN CN201210440642.4A patent/CN103809482A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105005246A (en) * | 2015-08-12 | 2015-10-28 | 恒信大友（北京）科技有限公司 | Portable data acquisition terminal |
| CN105487439A (en) * | 2015-11-27 | 2016-04-13 | 湖北三江航天红峰控制有限公司 | Double isolation device and method for multipath AD acquisition |
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140521 |