CN209784983U - FPGA-based data acquisition and pulse generation system - Google Patents

Abstract

the utility model discloses a data acquisition and pulse produce system, can produce four ways synchronous pulse signal and four ways switching signal, and carry out data acquisition to microsecond signal and direct current monitoring signal, to the pulse production module, the repetition frequency of its four ways pulse, pulse quantity, pulse parameters such as relative delay time between pulse width and the four ways can be set up by the host computer, accessible software and external signal come the production of control pulse signal and stop, microsecond signal acquisition module can set up the collection point number, total four passageways, can carry out data acquisition to the pulse at the microsecond signal of 50us ~ 200us, direct current monitoring signal acquisition module has eight passageways, voltage signal can be gathered to four preceding passageways, current signal can be gathered to four back passageways, the real-time status parameter of pulse production module and the data of gathering pass through the UDP mode through the host computer through the ethernet.

Description

FPGA-based data acquisition and pulse generation system

Technical Field

the utility model relates to a data acquisition and industrial control field especially relate to a control high power microwave source work and carry out the device monitored to the operating condition of high power microwave source through the pulse.

Background

the high-power microwave source adopts a Tesla type pulse power driving source, a pulse generation module provides a trigger signal for the driving source of the high-power microwave source and controls the microwave source ~ start working, the high-power microwave source can generate three waveforms respectively including a main capacitor discharge waveform with the pulse width of about 150us and the amplitude of-3V ~ +6V, a line voltage waveform with the voltage amplitude of-5V ~ 0V and the pulse width of about 70us and a trigger secondary voltage waveform, and the high-power microwave source also changes in the peripheral magnetic field state, the main switch air pressure, the main capacitor voltage and the trigger primary voltage in the working process.

SUMMERY OF THE UTILITY MODEL

The utility model provides a data acquisition and pulse produce device based on FPGA, the device are regarded as main control chip by FPGA, can produce four ways synchronous pulse, can set up the relevant parameter of pulse by the host computer, can carry out data acquisition to microsecond level signal waveform and DC voltage, current signal.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

For the four-path synchronous pulse signal generation module, the repetition frequency, the number of pulses and the pulse width of the four-path pulse signals are adjustable by FPGA logic resources. The resolution of the relative delay time realized by FPGA logic resources is only 10ns, while the delay resolution of 0.25ns can be realized by the external delay wire core piece DS1124, and a scheme of combining the FPGA and the external delay wire core piece can be adopted, so that the high resolution is ensured, and meanwhile, the large dynamic range can be realized.

As a further description of the above technical solution:

the microsecond signal acquisition module selects an A/D chip as THS1206, the analog input voltage range of the microsecond signal acquisition module is +1.5V ~ +3.5V, the highest sampling rate is 6MSPS, in order ~ ensure that the sampling rate of each microsecond signal is 2MSPS, two THS1206 analog- ~ -digital conversion chips are selected, the amplitude of the microsecond signal is between-10V and +10V, when an analog signal conditioning circuit is designed, the microsecond signal conditioning circuit is firstly subjected ~ voltage following by using a high-voltage slew rate, a wide bandwidth and a high-speed operational amplifier AD8022, then is subjected ~ attenuation by using resistance voltage division, is attenuated ~ the amplitude of the signal ~ be between-1V ~ +1V, and finally, a voltage bias circuit is designed by using the operational amplifier AD8044 and AD8615, so that the amplitude of the signal can just meet the analog voltage input requirement of the THS 1206.

As a further description of the above technical solution:

the A/D chip selected by the direct current voltage and current monitoring signal acquisition module is AD7607 which is an 8-channel 14-bit analog- ~ -digital converter, the sampling rate of each channel is 200KSPS, the analog voltage input range is-10V ~ +10V, for voltage signals, voltage following is carried out by using an operational amplifier ADTL084, then the signals are input ~ the AD7607 for data acquisition, for 4 mA-20 mA current signals, the voltage signals are firstly converted into 1.5V-7.5V voltage through an instrument operational amplifier AD627, and then analog- ~ -digital conversion is carried out.

as a further description of the above technical solution:

and the Ethernet data transmission part adopts an Ethernet chip W5300 which integrates a TCP/IP protocol and 10/100M MAC and PHY. The W5300 is controlled by the NIOS II soft core, the IP core of the W5300 is customized in the Qsys according to the data manual of the W5300, corresponding address, data and read-write control lines are generated, and then the connection with the NIOS II soft core is carried out through an Avalon bus. And finally, writing a program into the NIOS II soft core, and controlling the W5300 to upload the state parameters of the pulse, microsecond signal acquisition data, direct-current voltage and current monitoring data to an upper computer in a UDP mode.

To sum up, owing to adopted above-mentioned technical scheme, the beneficial effects of the utility model are that:

The microsecond-level voltage signal, direct-current voltage and current signal data acquisition is realized, and the data is uploaded to an upper computer through the Ethernet. The pulse generating module has high precision, the number of output pulses is large, and the resolution of relative delay time among four paths of pulses can reach 0.25 ns. All modules are controlled by the FPGA, so that the cost is effectively reduced, and the flexibility of the system is improved.

Drawings

FIG. 1 is an index of the pulse in the present invention;

fig. 2 is a block diagram of a hardware circuit structure of the data acquisition and pulse generation system of the present invention;

fig. 3 is a block diagram of the FPGA logic structure of the data acquisition and pulse generation system of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

The hardware structure of the whole system is shown in fig. 2:

in the FPGA configuration, a main clock of the FPGA adopts a 50MHz active constant temperature crystal oscillator, an AS interface is removed, only a JTAG interface is reserved AS a debugging interface, a serial Flash memory EPCS64 is selected to store hardware logic and a soft core running program of the FPGA, an NIOS II soft core abnormal vector memory adopts two pieces of external DDR2 SDRAM, the capacity of each piece is 1Gbit, in the design of a power supply system, the +12V voltage and the-12V voltage are power supply for an operational amplifier AD8022, ADTL084 and AD627, +5V and a two-stage voltage reduction chip are adopted to realize in the design of the voltage of the operational amplifier AD8022, AD8615 and an analog-to-digital chip AD7607, the +3.3V voltage is obtained by reducing the +12V voltage through AOZ1016, the power supply voltage of the Ethernet chip W5300 and the analog-to-digital conversion chip THS1206, the operational amplifier AD8022, the AD8044 and the analog-to-digital conversion chip THS 635V voltage is selected to reduce the-10V +10V voltage of the Ethernet chip W and the analog signal of the Ethernet chip W3, the Ethernet chip W and the analog signal of the Ethernet chip PHY 3, the Ethernet chip is converted into a signal, the analog signal of the Ethernet chip, the Ethernet chip is transmitted by using the Ethernet chip AD 120, the Ethernet chip AD 35, the Ethernet chip, the.

As shown in fig. 3, the NIOS II soft core controls the W5300 to receive the burst control command, the microsecond signal acquisition control command, and the external trigger enable command from the upper computer through the UDP mode. The pulse control commands are embodied as the repetition frequency of the pulses, the number of pulses, the pulse width and the relative time delay between the four pulses. The microsecond signal acquisition control command mainly controls a trigger channel of the microsecond acquisition module and the number of sampling points before triggering. RX1 is the start signal, the control pulse module starts to generate pulses, RX2 is the stop signal, and the stop emergency control signal will force the pulse output to stop when the system has an emergency. RX1 and RX2 are all processed in the external trigger control module to prevent false triggering. The pulse generating system can be controlled to start outputting pulses by means of software triggering and hardware triggering. The state monitoring signals are direct-current voltage signals and direct-current signals, after AD7607 data are collected, data and real-time state parameters of pulses of the signals are framed, and the data and the real-time state parameters are uploaded to an upper computer through an Ethernet chip W5300 at the frequency of 50 Hz. For the microsecond signal acquisition module, before the trigger signal comes, the data acquired by the THS1206 is continuously written into the annular RAM. When the pulse module starts to output pulses, a trigger signal is generated, microsecond signal data acquired before triggering and microsecond signal data acquired after triggering are sequentially taken out of the annular RAM by the trigger signal and are framed to form complete microsecond waveform data, and the complete microsecond waveform data is uploaded to an upper computer through the Ethernet chip W5300. And the upper computer displays the state parameters of the pulse, the waveform of the microsecond signal and monitoring signal data in real time.

The above, only be the concrete implementation of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the utility model, the concept of which is equivalent to replace or change, should be covered within the protection scope of the present invention.

Claims (4)

1. A data acquisition and pulse generation system based on FPGA comprises a four-way synchronous pulse generation module, a four-way switch signal generation module, a microsecond signal acquisition module and a monitoring signal data acquisition module;

The four-path synchronous pulse generation module has pulse state control parameters which can be set by an upper computer, can control the generation and stop of pulses through two TTL external trigger signals and an upper computer program, has the priority higher than a program instruction, and uploads the state parameters of the pulses to the upper computer through the Ethernet at the frequency of 50 Hz;

The four-way switch signal generating module is used for controlling the four-way switch signal to be switched between a high level output state and a low level output state by the upper computer.

2. the FPGA-based data acquisition and pulse generation system as claimed in claim 1, wherein there are four acquisition channels, each channel has a sampling rate of 2MSPS and a precision of 12 bits, and can acquire microsecond signals with amplitudes between-10 ~ + 10V.

3. the FPGA-based data acquisition and pulse generation system of claim 1, wherein the waveform of each microsecond signal is acquired at 600 points, and the number of sampling points before and after the trigger time can be set, and the data is immediately uploaded to an upper computer through the Ethernet after one complete waveform is acquired.

4. the FPGA-based data acquisition and pulse generation system as claimed in claim 1, wherein the system comprises eight acquisition channels, the sampling rate of each channel is 1KSPS, the first four channels can acquire-10 ~ +10V voltage signals, the last four channels can acquire 4 ~ 20mA current signals, and the acquired monitoring signal data is transmitted ~ an upper computer through an Ethernet at a frequency of 50 Hz.