CN201576682U - 高压大功率运算放大器 - Google Patents

高压大功率运算放大器 Download PDF

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Publication number
CN201576682U
CN201576682U CN 201020150039 CN201020150039U CN201576682U CN 201576682 U CN201576682 U CN 201576682U CN 201020150039 CN201020150039 CN 201020150039 CN 201020150039 U CN201020150039 U CN 201020150039U CN 201576682 U CN201576682 U CN 201576682U
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China
Prior art keywords
ceramic substrate
operational amplifier
power transistor
film resistor
power
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Expired - Fee Related
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CN 201020150039
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English (en)
Inventor
薛晓东
任志伟
邱晓华
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JINZHOU 777 MICROELECTRONICS CO Ltd
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JINZHOU 777 MICROELECTRONICS CO Ltd
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Priority to CN 201020150039 priority Critical patent/CN201576682U/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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Abstract

一种高压大功率运算放大器，包括管壳，其特征是：在管壳上通过粘结膜粘接有陶瓷基片，在陶瓷基片上印制有金导带和厚膜电阻，在陶瓷基片上通过焊膏焊接有运算放大器表贴元件，在陶瓷基片上还粘接有大功率晶体管，所述的大功率晶体管和厚膜电阻构成扩流电路，位于陶瓷基片上各元件之间通过互连引线连接。优点是：占用空间小，方便使用，并且能保证良好的散热效果，可适用于-40℃～+85℃的工作环境。

Description

高压大功率运算放大器
技术领域
本实用新型涉及一种半导体混合集成电路器件，尤其涉及一种高压大功率运算放大器。
背景技术
由于运算放大器多为工作电压较低，输出功率较小。因而，无法直接应用于某些工作电压较高，负载较重的环境。目前，大多数是通过普通运算放大器、扩流电路组合使用来实现电路功能，且需要外加晶体管散热片，占用空间大，组装繁琐。尤其在一些恶劣环境下，例如超高温、超低温、高湿度、强振动等，普通元件无法工作。
实用新型内容
本实用新型要解决的技术问题是提供一种将运算放大器、构成扩流电路的大功率晶体管和电阻全部集成在一起，占用空间小，方便使用，并且能保证良好的散热效果，可适用于-40℃～+85℃的工作环境的高压大功率运算放大器。
本实用新型涉及的高压大功率运算放大器，包括管壳，其特征是：在管壳上通过粘结膜粘接有陶瓷基片，在陶瓷基片上印制有金导带和厚膜电阻，在陶瓷基片上通过焊膏焊接有运算放大器表贴元件，在陶瓷基片上还粘接有大功率晶体管，所述的大功率晶体管和厚膜电阻构成扩流电路，位于陶瓷基片上各元件之间通过互连引线连接。
上述的高压大功率运算放大器，所述的互连引线为金丝。
本实用新型将运算放大器表贴元件、大功率晶体管和电阻全部集成在陶瓷基片上，占用空间小，方便使用，并且能保证良好的散热效果，可适用于-40℃～+85℃的工作环境。
附图说明
图1是本实用新型的结构示意图；
图2是图1(去掉管帽)的俯视图。
图中：管壳1，陶瓷基片2，金导带201，厚膜电阻202，运算放大器表贴元件3，焊膏4，大功率晶体管5，导电环氧胶6，互连引线7，粘结膜8。
具体实施方式
如图所示，本实用新型有一个由管帽和管座构成的管壳1，在管壳1上通过粘结膜8粘接有厚度在0.4～0.8mm之间的陶瓷基片2，在陶瓷基片2表面采用丝网印刷技术印制金导带201和厚膜电阻202；陶瓷基片2采用二氧化硅、氮化铝、氧化铝、氧化铍中的一种作为基片材料。在陶瓷基片2上通过焊膏4焊接有运算放大器表贴元件3，在陶瓷基片2上采用导电环氧胶6粘接有大功率晶体管5，位于陶瓷基片2上各元件(运算放大器表贴元件3、大功率晶体管5和厚膜电阻202)之间通过互连引线7连接，所述的互连引线7采用金丝。

Claims (2)

1.一种高压大功率运算放大器，包括管壳，其特征是：在管壳上通过粘结膜粘接有陶瓷基片，在陶瓷基片上印制有金导带和厚膜电阻，在陶瓷基片上通过焊膏焊接有运算放大器表贴元件，在陶瓷基片上还粘接有大功率晶体管，所述的大功率晶体管和厚膜电阻构成扩流电路，位于陶瓷基片上各元件之间通过互连引线连接。
2.根据权利要求1所述的高压大功率运算放大器，其特征是：所述的互连引线为金丝。
CN 201020150039 2010-04-01 2010-04-01 高压大功率运算放大器 Expired - Fee Related CN201576682U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111489998A (zh) * 2020-04-15 2020-08-04 深圳市澜垣半导体有限公司 一种功率晶体管的芯片固定方法及功率晶体管与放大器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111489998A (zh) * 2020-04-15 2020-08-04 深圳市澜垣半导体有限公司 一种功率晶体管的芯片固定方法及功率晶体管与放大器

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