CN201392486Y - Instruction type-based CPU clock control circuit and digital television receiving terminal - Google Patents
Instruction type-based CPU clock control circuit and digital television receiving terminal Download PDFInfo
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- CN201392486Y CN201392486Y CN200920008238U CN200920008238U CN201392486Y CN 201392486 Y CN201392486 Y CN 201392486Y CN 200920008238 U CN200920008238 U CN 200920008238U CN 200920008238 U CN200920008238 U CN 200920008238U CN 201392486 Y CN201392486 Y CN 201392486Y
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- cpu
- control circuit
- clock control
- bus interface
- combinational logic
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Abstract
The utility model discloses an instruction type-based CPU clock control circuit, which comprises a CPU, a bus interface control circuit, a clock control unit and a combinational logic circuit, wherein the CPU is connected with the bus interface control circuit through a system bus, the clock control unit is connected with the CPU, the combinational logic circuit and the bus interface control circuit, and the combinational logic circuit is connected with the CPU, the bus interface control circuit and the clock control unit. The utility model also discloses a digital television receiving terminal using the instruction type-based CPU clock control circuit. The utility model has the advantage that the CPU clock control circuit can improve the system performance and save the hardware resource and the power consumption.
Description
Technical field
The utility model relates to control circuit and has the digital receiver of control circuit, particularly a kind of cpu clock control circuit and receiving terminal for digital television based on instruction type.
Background technology
At embedded system and system integrated chip (SoC, System on Chip) in, owing to adopt gate delay new technology less and less, the frequency that CPU frequency is higher than system bus is the way of using always, but the high primary frequency that CPU can reach is often relevant with operator scheme, such as: 1) some CPU has coprocessor, and is because these coprocessors will be used the resource of CPU and bus, therefore just slow than without coprocessor the time; 2) on VLIW (Very Long Instruction Word, very long instruction word) processor, if all instruction slots (SLOT) are full, so also similar problem may take place; 3) during some bus operation, the high primary frequency that can reach is fast during than inoperation.Usually, the highest frequency of CPU is to set to satisfy above every minimum, can not carry out down conversion process according to above-mentioned situation.
The utility model content
Technical problem to be solved in the utility model is: a kind of cpu clock control circuit based on instruction type that can carry out down conversion process according to different situations to clock frequency is provided, and adopt described control circuit can improve the performance of system, save the receiving terminal for digital television of hardware resource and power consumption.
For solving technical matters of the present utility model, the utility model discloses a kind of cpu clock control circuit based on instruction type, comprise by interconnective CPU of system bus and bus interface control circuit, also comprise clock control cell and combinational logic circuit, described clock control cell is connected with CPU, combinational logic circuit, bus interface control circuit, and described combinational logic circuit is connected with CPU, bus interface control circuit and clock control cell.
Wherein, described cpu clock control circuit based on instruction type also comprises a coprocessor, is connected with CPU, clock control cell, combinational logic circuit and system bus.
Wherein, described combinational logic circuit is used for sending the frequency reducing instruction according to the working condition of bus interface control circuit, CPU or coprocessor to clock control cell; Described clock control cell is used for when receiving the frequency reducing instruction that combinational logic circuit sends the clock signal of receiving being carried out down conversion process, and the clock signal after bus interface control circuit, CPU or coprocessor output are handled.
Wherein, the working condition of described bus interface control circuit, CPU and coprocessor comprises following situation: 1, bus interface control circuit is when operation or unusual busy operation; 2, a plurality of or whole command bits of CPU are not during vacancy; 3, when coprocessor or some processors be combined in operation or unusual busy operation the time.
Wherein, the frequency of the clock signal after the described processing is the branch several times of the highest frequency of original clock signal.
For solving technical matters of the present utility model, the utility model also discloses a kind of receiving terminal for digital television, comprise a cpu clock control circuit based on instruction type, this circuit comprises by interconnective CPU of system bus and bus interface control circuit, also comprise clock control cell and combinational logic circuit, described clock control cell is connected with CPU, combinational logic circuit, bus interface control circuit, and described combinational logic circuit is connected with CPU, bus interface control circuit and clock control cell.
Wherein, described cpu clock control circuit based on instruction type also comprises a coprocessor, is connected with CPU, clock control cell, combinational logic circuit and system bus.
Wherein, described combinational logic circuit is used for sending the frequency reducing instruction according to the working condition of bus interface control circuit, CPU or coprocessor to clock control cell; Described clock control cell is used for when receiving the frequency reducing instruction that combinational logic circuit sends the clock signal of receiving being carried out down conversion process, and the clock signal after bus interface control circuit, CPU or coprocessor output are handled.
Wherein, the working condition of described bus interface control circuit, CPU and coprocessor comprises following situation: 1, bus interface control circuit is when operation or unusual busy operation; 2, a plurality of or whole command bits of CPU are not during vacancy; 3, when coprocessor or some processors be combined in operation or unusual busy operation the time.
Wherein, the frequency of the clock signal after the described processing is the branch several times of the highest frequency of original clock signal.
Compared with prior art, the utlity model has following beneficial effect: the utility model passes through combinational logic circuit based on the cpu clock control circuit of instruction type, when detecting generation and needing situation to the clock signal down conversion process, the control clock control cell carries out down conversion process to clock signal.After the utility model receiving terminal for digital television adopts this circuit, the performance of system be can improve, hardware resource and power consumption saved.
Description of drawings
Fig. 1 is circuit theory diagrams of the present utility model.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in further detail.
Embodiment 1
As shown in Figure 1, be example with the cpu clock control circuit that has coprocessor based on instruction type, principle of work of the present utility model is described in detail in detail.
Present embodiment comprises the CPU that is connected to system bus, the coprocessor that matches with CPU and bus interface control circuit, and clock control cell and the combinational logic circuit that is connected clock control cell.Described clock control cell also is connected CPU and coprocessor respectively with combinational logic circuit, and by bus interface control circuit connecting system bus.
Combinational logic circuit is used for sending the frequency reducing instruction according to the working condition of bus interface control circuit, CPU or coprocessor to clock control cell; Described clock control cell is used for when receiving the frequency reducing instruction that combinational logic circuit sends the clock signal of receiving being carried out down conversion process, and the clock signal after bus interface control circuit, CPU or coprocessor output are handled.
The working condition of bus interface control circuit, CPU and coprocessor comprises following situation: 1, bus interface control circuit is when operation or unusual busy operation; 2, a plurality of or whole command bits of CPU are not during vacancy; 3, when coprocessor or some processors be combined in operation or unusual busy operation the time.
When above-mentioned situation 1 takes place, bus interface control circuit can send signal to combinational logic circuit, combinational logic circuit produces the frequency reducing instruction according to certain logic rules after receiving this signal, and send frequency reducing to clock control cell and instruct, after clock control cell is received, clock signal is carried out down conversion process, the original frequency (highest frequency) of clock signal can be dropped to the master clock frequency of CPU, this frequency can be the branch several times of highest frequency.
In like manner, when above-mentioned situation 2 or 3 takes place, CPU or coprocessor can send signal to combinational logic circuit, combinational logic circuit produces the frequency reducing instruction according to certain logic rules after receiving this signal, and send frequency reducing to clock control cell and instruct, thereby make clock control cell carry out down conversion process to clock signal.
Particularly, combinational logic circuit can be by constituting with logical circuits such as door or door, Sheffer stroke gates; Clock control cell can be made of clock down conversion process circuit of the prior art.
Embodiment 2
Present embodiment provides a kind of receiving terminal for digital television, comprises embodiment 1 described cpu clock control circuit based on instruction type, and the structure of its circuit and principle of work are identical with embodiment 1, do not repeat them here.
Adopt the utility model, can improve system performance, save hardware resource and power consumption; And existing systems or SoC system upgraded and can the increased bandwidth demand.
Claims (10)
1, a kind of cpu clock control circuit based on instruction type, comprise by interconnective CPU of system bus and bus interface control circuit, it is characterized in that, also comprise clock control cell and combinational logic circuit, described clock control cell is connected with CPU, combinational logic circuit, bus interface control circuit, and described combinational logic circuit is connected with CPU, bus interface control circuit and clock control cell.
2, the cpu clock control circuit based on instruction type as claimed in claim 1 is characterized in that, also comprises a coprocessor, is connected with CPU, clock control cell, combinational logic circuit and system bus.
3, the cpu clock control circuit based on instruction type as claimed in claim 1 or 2 is characterized in that, described combinational logic circuit is used for sending the frequency reducing instruction according to the working condition of bus interface control circuit, CPU or coprocessor to clock control cell; Described clock control cell is used for when receiving the frequency reducing instruction that combinational logic circuit sends the clock signal of receiving being carried out down conversion process, and the clock signal after bus interface control circuit, CPU or coprocessor output are handled.
4, the cpu clock control circuit based on instruction type as claimed in claim 3, it is characterized in that the working condition of described bus interface control circuit, CPU and coprocessor comprises following situation: 1, bus interface control circuit is when operation or unusual busy operation; 2, a plurality of or whole command bits of CPU are not during vacancy; 3, when coprocessor or some processors be combined in operation or unusual busy operation the time.
5, the cpu clock control circuit based on instruction type as claimed in claim 3 is characterized in that, the frequency of the clock signal after the described processing is the branch several times of the highest frequency of original clock signal.
6, a kind of receiving terminal for digital television, it is characterized in that, comprise a cpu clock control circuit based on instruction type, this circuit comprises by interconnective CPU of system bus and bus interface control circuit, also comprise clock control cell and combinational logic circuit, described clock control cell is connected with CPU, combinational logic circuit, bus interface control circuit, and described combinational logic circuit is connected with CPU, bus interface control circuit and clock control cell.
7, receiving terminal for digital television as claimed in claim 6 is characterized in that, described cpu clock control circuit based on instruction type also comprises a coprocessor, is connected with CPU, clock control cell, combinational logic circuit and system bus.
As claim 6 or 7 described receiving terminal for digital television, it is characterized in that 8, described combinational logic circuit is used for sending the frequency reducing instruction according to the working condition of bus interface control circuit, CPU or coprocessor to clock control cell; Described clock control cell is used for when receiving the frequency reducing instruction that combinational logic circuit sends the clock signal of receiving being carried out down conversion process, and the clock signal after bus interface control circuit, CPU or coprocessor output are handled.
9, receiving terminal for digital television as claimed in claim 8 is characterized in that, the working condition of described bus interface control circuit, CPU and coprocessor comprises following situation: 1, bus interface control circuit is when operation or unusual busy operation; 2, a plurality of or whole command bits of CPU are not during vacancy; 3, when coprocessor or some processors be combined in operation or unusual busy operation the time.
10, receiving terminal for digital television as claimed in claim 8 is characterized in that, the frequency of the clock signal after the described processing is the branch several times of the highest frequency of original clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200920008238U CN201392486Y (en) | 2008-12-12 | 2009-03-27 | Instruction type-based CPU clock control circuit and digital television receiving terminal |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810218319.6 | 2008-12-12 | ||
| CN200810218319 | 2008-12-12 | ||
| CN200920008238U CN201392486Y (en) | 2008-12-12 | 2009-03-27 | Instruction type-based CPU clock control circuit and digital television receiving terminal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201392486Y true CN201392486Y (en) | 2010-01-27 |
Family
ID=41599306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200920008238U Expired - Fee Related CN201392486Y (en) | 2008-12-12 | 2009-03-27 | Instruction type-based CPU clock control circuit and digital television receiving terminal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201392486Y (en) |
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2009
- 2009-03-27 CN CN200920008238U patent/CN201392486Y/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Beijing TongZhou era technology limited liability company Assignor: Shenzhen Tongzhou Electronic Co., Ltd. Contract record no.: 2010440020214 Denomination of utility model: Instruction type-based CPU clock control circuit and digital television receiving terminal Granted publication date: 20100127 License type: Exclusive License Record date: 20101122 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100127 Termination date: 20150327 |
|
| EXPY | Termination of patent right or utility model |