CN105045338B

CN105045338B - A kind of more peripheral hardware low energy consumption computer architectures and control method

Info

Publication number: CN105045338B
Application number: CN201510374898.3A
Authority: CN
Inventors: 李牧; 韩叔桓; 马新浩; 申威威; 李艳; 彭鹏; 晁阳; 田满静
Original assignee: Xian University of Technology
Current assignee: Xian University of Technology
Priority date: 2015-06-30
Filing date: 2015-06-30
Publication date: 2018-05-29
Anticipated expiration: 2035-06-30
Also published as: CN105045338A

Abstract

The invention discloses a kind of more peripheral hardware low energy consumption computer architectures, including CPU module, the periphery of CPU module is connected with several CLB modules being embedded in FPGA module, each CLB modules are connected to the memory in computer by interface, memory is connected with several peripheral hardware mouths by bus, the invention also discloses a kind of control methods of more peripheral hardware low energy consumption computer architectures, first determine whether external demand signal, according to the type of external demand signal, peripheral hardware is changed accordingly, it is slow that the present invention solves computer performance in the prior art, the problem of high energy consumption.

Description

A kind of more peripheral hardware low energy consumption computer architectures and control method

Technical field

The invention belongs to field of computer technology, and in particular to a kind of more peripheral hardware low energy consumption computer architectures, the present invention is also It is related to the control method of more peripheral hardware low energy consumption computer architectures.

Background technology

At present, the development of computer enters a bottleneck period, and major computer chip production commercial city simply carries merely Chip frequency is risen, increases the operational capability of processor to promote computer performance, but is so Yang soup ﹑ glasss of waterwheels of Zhi Fei Firewood, can only respite problem, cannot but tackle the problem at its root, so how fundamentally to promote the performance of computer is One urgent problem to be solved, in order to improve the performance of computer, people, which have done the various aspects of traditional computer, accordingly to be changed It is kind, many methods are also taken, for example remove some unnecessary She Bei ﹑ to improve some miscellaneous functions, such as occur now Super notebook, so-called ultrabook, simply compared with before-improvement thinning, advantage is the weight for alleviating computer, outside Hommization can be more considered in sight.Inferior position is that overall performance does not substantially get a promotion, and price remains high, and becomes style Attract consumer spending, it is so-called to control in table do not control.

It is to increase He Shuo ﹑ Xian Cheng Shuo ﹑ to improve cpu performances in terms of promoting computer performance, the advantages of this method is can be Performance boost in limited scope to computer.In future soon, requirement of the people to computer it is higher and higher, it is impossible to Increasing He Shuo ﹑ Xian Cheng Shuo ﹑ always improves cpu performances etc. to promote computer performance, and these methods have limitation very much, simultaneously Load power consumption is added, service life greatly shortens so that general effect declines, and practicability is gradually lost.

It is good that traditional computer has the advantages that preferably to stablize at present with it, by popular extensive use, but with It is comparable weak that this present information huge explosion era development trend will also meet consumer demand, is innovated in computer Aspect, it is preferred that emphasis is the performance of computer can also be significantly promoted while mitigating CPU burdens, avoids unwanted power consumption.

The content of the invention

The object of the present invention is to provide a kind of more peripheral hardware low energy consumption computer architectures, solve meter in the prior art The problem of calculation machine performance is slow, high energy consumption.

It is a further object of the present invention to provide a kind of control methods of more peripheral hardware low energy consumption computer architectures.

First technical solution of the present invention is a kind of more peripheral hardware low energy consumption computer architectures, including CPU module, The periphery of CPU module is connected with several CLB modules being embedded in FPGA module, and each CLB modules are connected to meter by interface Memory in calculation machine, memory are connected with several peripheral hardware mouths by bus.

The characteristics of first technical solution of the invention, also resides in,

Interface is IOB interfaces, one kind in USB interface, USB interface.

Second technical solution of the present invention is a kind of control method of more peripheral hardware low energy consumption computer architectures, tool Body is implemented according to following steps：

Step 1, when computer receives external demand signal, external demand signal is sent to internal hold by CPU module Row unit EU, then execution unit EU judges external demand signal, if the external demand signal being connected to is hardware life Order, then this command signal is sent to the CLB modules in FPGA module by execution unit EU, if the external demand signal being connected to is Software command, then CPU module traditionally handle；

Step 2, when CLB modules receive the hardware command that the step 1 transmits, to the peripheral hardware on corresponding computer Hardware is changed, and concrete operations are as follows：

2.1) instruction database is initially set up：Inside CPU module to the corresponding hardware commands of change situation of all peripheral hardwares into Row number, each peripheral hardware change situation and correspond to a coding；

2.2) corresponding rule base is established：In FPGA module, each coding in corresponding step 2.1) is set corresponding Control hardware operational order；

2.3) when CPU module receives external demand signal, according to the instruction database in step 2.1), external command is believed It number sits in the right seat, then FPGA module searches operational order corresponding with received number, this operational order is passed It send to internal CLB modules, CLB modules control corresponding peripheral hardware to be changed；

Step 3, when the hardware command received in step 2 is disconnects peripheral hardware order just in collecting work, CPU moulds Block first reads hardware command, then stores the data in corresponding peripheral hardware to memory, then performs disconnection to corresponding peripheral hardware Operation makes corresponding peripheral hardware exit operating circuit, so as to save power consumption.

The characteristics of second technical solution of the invention, also resides in,

The peripheral hardware hardware on corresponding computer is changed in step 2 and is specifically included：Peripheral hardware disconnects and peripheral hardware access.

The invention has the advantages that a kind of more peripheral hardware low energy consumption computer architectures, calculating is added to by the advantage of FPGA In machine system so that CLB modules are closely nested with CPU module so that not only energy consumption reduces, and greatly improves the work of computer Speed extends the service life of computer, it is often more important that, it improves the physics theory of computer so that same in synchronization When the components number that works be not restricted so that computer architecture is simpler, has very big practical value.

Description of the drawings

Fig. 1 is a kind of structure diagram of more peripheral hardware low energy consumption computer architectures of the present invention.

In figure, 1.CPU modules, 2.CLB modules, 3. interfaces, 4. memories, 5. peripheral hardwares.

Specific embodiment

The present invention is described in detail with reference to the accompanying drawings and detailed description.

A kind of more peripheral hardware low energy consumption computer architectures of the present invention, structure is as shown in Figure 1, including CPU module 1, CPU module 1 Periphery be connected with several CLB modules 2 being embedded in FPGA module, each CLB modules 2 are connected to computer by interface 3 Interior memory 4, memory 4 are connected with several peripheral hardwares 5 by bus, and interface 3 is IOB interfaces, in USB interface, USB interface It is a kind of.

The control method of the more peripheral hardware low energy consumption computer architectures of the present invention, specifically implements according to following steps：

Step 1, when computer receives external demand signal, external demand signal is sent to internal hold by CPU module 1 Row unit EU, then execution unit EU judges external demand signal, if the external demand signal being connected to is hardware life Order, then this command signal is sent to the CLB modules 2 in FPGA module by execution unit EU, if the external demand signal being connected to It is software command, then CPU module is traditionally handled, and only when CPU module 1 sends order, subsequent peripheral hardware is according to order Corresponding work only receives corresponding order and just works, not so continue to disconnect, avoids occupying resource, reduce power consumption；

Step 2, when CLB modules 2 receive the hardware command that step 1 transmits, to the peripheral hardware on corresponding computer into Row changes, and concrete operations are as follows：

2.1) instruction database is initially set up：Inside CPU module 1 to the corresponding hardware commands of change situation of all peripheral hardwares into Row number, each peripheral hardware 5 change situation and correspond to a coding；

2.3) when CPU module 1 receives external demand signal, according to the instruction database in step 2.1), to external command Signal is sat in the right seat, and then FPGA module searches operational order corresponding with received number, by this operational order Internal CLB modules 2 are sent to, CLB modules 2 control corresponding peripheral hardware to be changed, that is, control the disconnection of peripheral hardware 5 and control outer If 5 access；

Step 3, when the hardware command received in step 2 is disconnects peripheral hardware order just in collecting work, CPU moulds Block 1 first reads hardware command, then stores to memory 4 data in corresponding peripheral hardware, then corresponding peripheral hardware 5 is performed Opening operation makes corresponding peripheral hardware 5 exit operating circuit, so as to save power consumption.

More peripheral hardware low energy consumption computer architectures are by CPU module, the reasonable nesting of FPGA resource under computer system With utilization, a kind of more peripheral hardware low energy consumption computer architecture control methods are created, the occasion used according to computer provides simultaneously can The infinitesimal System on Chip/SoC of programmed logic, High Performance DSP and computer processor, using this monolithic device cause CPU and peripheral hardware it Between form one-to-many mode, then using the reasonable nested with application of FPGA resource, in terms of human-computer interaction, find most effective Executive mode so that avoid some unnecessary operations, it is intended to drop to the computer bus top number of packages under working condition It is minimum, realize that arithmetic speed reaches most fast.

Traditional computer architecture once be molded it is just immutable, and in the present invention so that Peripheral Interface then all of FPGA is realized, in this way, being temporarily not required to original paper to be used can directly disconnect, has both been reduced the working time of original paper, has been added Service life also improves service efficiency；In traditional computer, sleep pattern can be in by being temporarily not required to device to be used, But sleep pattern is also required to load energy consumption, and in the present invention, some unnecessary operations are avoided, while memory property is taken into account, Greatly reduce energy consumption；In traditional computer, interface can only one peripheral hardware of pipe, even if similar is multiple, it is also necessary to have Decoding circuit, and in the present invention, then using FPGA resource and the reasonable nested of CPU and application, so as in terms of human-computer interaction, look for To most effective executive mode, then an interface management whole peripheral hardware can be used, the peripheral hardware of work is not required to utilize CLB module controls System makes it directly disconnect.

Claims

1. a kind of control method of more peripheral hardware low energy consumption computer architectures, which is characterized in that including CPU module (1), CPU module (1) periphery is connected with several CLB modules (2) being embedded in FPGA module, and each CLB modules (2) are connected by interface (3) Memory (4) in computer, the memory (4) are connected with several peripheral hardwares (5) by bus；

Specifically implement according to following steps：

Step 1, when computer receives external demand signal, external demand signal is sent to internal execution by CPU module (1) Unit EU, then execution unit EU judges external demand signal, if the external demand signal being connected to is hardware command, Then this command signal is sent to the CLB modules (2) in FPGA module by execution unit EU, if the external demand signal being connected to is Software command, then CPU module traditionally handle；

Step 2, when CLB modules (2) receive the hardware command that the step 1 transmits, to the peripheral hardware on corresponding computer It is changed, concrete operations are as follows：

2.1) instruction database is initially set up：It is internal to the progress of the change situation of all peripheral hardwares corresponding hardware command in CPU module (1) Number, each peripheral hardware (5) change situation and correspond to a coding；

2.2) corresponding rule base is established：In FPGA module, each coding in the corresponding step 2.1) is set corresponding Control hardware operational order；

2.3) when CPU module (1) receives external demand signal, according to the instruction database in the step 2.1), outside is referred to Signal is made to sit in the right seat, then FPGA module searches operational order corresponding with received number, this operation is ordered Order is sent to internal CLB modules (2), and CLB modules (2) control corresponding peripheral hardware to be changed；

Step 3, when the hardware command received in the step 2 is disconnects peripheral hardware order just in collecting work, CPU moulds Block (1) first reads hardware command, then stores the data in corresponding peripheral hardware to memory (4), then to corresponding peripheral hardware (5) opening operation is performed, corresponding peripheral hardware (5) is made to exit operating circuit, so as to save power consumption.

2. the control method of a kind of more peripheral hardware low energy consumption computer architectures according to claim 1, which is characterized in that described Interface (3) is IOB interfaces, one kind in USB interface.

3. the control method of a kind of more peripheral hardware low energy consumption computer architectures according to claim 1, which is characterized in that described The peripheral hardware (5) on corresponding computer is changed in step 2 and is specifically included：Peripheral hardware (5) disconnects and peripheral hardware (5) access.