CN105045338A - Multiple-peripheral-equipment and low-energy-consumption computer architecture and control method - Google Patents
Multiple-peripheral-equipment and low-energy-consumption computer architecture and control method Download PDFInfo
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- CN105045338A CN105045338A CN201510374898.3A CN201510374898A CN105045338A CN 105045338 A CN105045338 A CN 105045338A CN 201510374898 A CN201510374898 A CN 201510374898A CN 105045338 A CN105045338 A CN 105045338A
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Abstract
The present invention discloses a multiple-peripheral-equipment and low-energy-consumption computer architecture, comprising a CPU module, wherein the periphery of the CPU module is connected with a plurality of CLB modules embedded in an FPGA module; each CLB module is connected to a storage in a computer by an interface; and the storage is connected with a plurality of peripheral ports by buses. The present invention further discloses a control method for the multiple-peripheral-equipment and low-energy-consumption computer architecture. The method comprises: firstly, judging an external command signal; and correspondingly changing peripheral equipment according to the type of the external command signal. According to the present invention, the problems of low performance and high energy consumption of a computer in the prior art are solved.
Description
Technical field
The invention belongs to field of computer technology, be specifically related to a kind of many peripheral hardwares low energy consumption computer architecture, the invention still further relates to the control method of many peripheral hardwares low energy consumption computer architecture.
Background technology
At present, the development of computing machine enters a bottleneck period, each large computer chip production commercial city just promotes chip frequency merely, the arithmetic capability increasing processor promotes computing power, but so just Yang soup Zhi Fei ﹑ an utterly inadequate amount, can only respite problem, but can not tackle the problem at its root, so the performance how fundamentally promoting computing machine is a problem demanding prompt solution, in order to improve the performance of computing machine, the various aspects of people to traditional computer have done corresponding improvement, also a lot of methods is taken, such as remove some unnecessary She Bei ﹑ and improve some subsidiary functions, such as there is super notebook now, so-called super, just compared with before-improvement thinning, advantage is the weight alleviating computing machine, more hommization can be considered in appearance.Inferior position is that overall performance does not obviously get a promotion, and price remains high, and becomes style and attracts consumer spending, and what is called is controlled in table do not control.
Promoting computing power aspect is increase He Shuo ﹑ Xian Cheng Shuo ﹑ to improve cpu performance, and the advantage of this method is can to the performance boost of computing machine in limited scope.In future soon, people are more and more higher to the requirement of computing machine, He Shuo ﹑ Xian Cheng Shuo ﹑ can not be increased improve cpu performance etc. and promote computing power always, and these methods have limitation very much, add load power consumption simultaneously, serviceable life shortens greatly, and general effect is declined, and practicality is lost gradually.
Traditional computing machine has with it advantage stablized preferably current, used widely by masses, but it is suitable weak also will to satisfy the demands of consumers with present this information big bang era development trend, in computing machine novel aspects, significantly can also promote the performance of computing machine while focusing on alleviating CPU burden, avoid unwanted power consumption.
Summary of the invention
The object of this invention is to provide a kind of many peripheral hardwares low energy consumption computer architecture, solve the problem that the computing power existed in prior art is slow, energy consumption is high.
Another object of the present invention is to provide a kind of control method of many peripheral hardwares low energy consumption computer architecture.
First technical scheme of the present invention is, a kind of many peripheral hardwares low energy consumption computer architecture, comprise CPU module, the periphery of CPU module is connected with some CLB modules be embedded in FPGA module, each CLB module is connected to the storer in computing machine by interface, storer is connected with some peripheral hardware mouths by bus.
The feature of the present invention first technical scheme is also,
Interface is the one in IOB interface, USB interface, USB interface.
Second technical scheme of the present invention is, a kind of control method of many peripheral hardwares low energy consumption computer architecture, specifically implements according to following steps:
Step 1, receive external demand signal when computing machine, external demand signal is sent to inner performance element EU by CPU module, then performance element EU judges external demand signal, if the external demand signal received is hardware command, then this command signal is sent to the CLB module in FPGA module by performance element EU, if the external demand signal received is software command, then CPU module traditionally processes;
Step 2, when CLB module receives the hardware command that described step 1 transmits, change the peripheral hardware hardware on the computing machine of correspondence, concrete operations are as follows:
2.1) first set up instruction database: be numbered at the inner hardware command corresponding to the change situation of all peripheral hardwares of CPU module, each peripheral hardware changes the corresponding coding of situation;
2.2) set up corresponding rule base: in FPGA module, corresponding step 2.1) in each coding, the operational order of corresponding control hardware is set;
2.3) when CPU module receives external demand signal, according to step 2.1) in instruction database, external demand signal is sat in the right seat, then FPGA module searches the operational order corresponding with received numbering, this operational order is sent to inner CLB module, CLB module controls corresponding peripheral hardware and changes;
Step 3, when the hardware command received in step 2 is off the peripheral hardware order just at collecting work, CPU module first reads hardware command, then the data in corresponding peripheral hardware are stored in storer, then opening operation is performed to corresponding peripheral hardware, corresponding peripheral hardware is deactivated circuit, thus saves power consumption.
The feature of the present invention second technical scheme is also,
In step 2, the peripheral hardware hardware on the computing machine of correspondence is changed and specifically comprise: peripheral hardware disconnects and peripheral hardware access.
The invention has the beneficial effects as follows, a kind of many peripheral hardwares low energy consumption computer architecture, joins in computer system by the advantage of FPGA, makes CLB module and CPU module closely nested, not only energy consumption is reduced, greatly improve the operating rate of computing machine, extend the life-span of computing machine, the more important thing is, which improve the physics theory of computing machine, the components number simultaneously worked at synchronization be not restricted, makes computer architecture more simple, there is very large practical value.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of many peripheral hardwares low energy consumption of the present invention computer architecture.
In figure, 1.CPU module, 2.CLB module, 3. interface, 4. storer, 5. peripheral hardware.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
A kind of many peripheral hardwares low energy consumption of the present invention computer architecture, structure as shown in Figure 1, comprise CPU module 1, the periphery of CPU module 1 is connected with some CLB modules 2 be embedded in FPGA module, each CLB module 2 is connected to the storer 4 in computing machine by interface 3, storer 4 is connected with some peripheral hardwares 5 by bus, and interface 3 is the one in IOB interface, USB interface, USB interface.
The control method of the present invention's many peripheral hardwares low energy consumption computer architecture, specifically implement according to following steps:
Step 1, when computing machine receives external demand signal, external demand signal is sent to inner performance element EU by CPU module 1, then performance element EU judges external demand signal, if the external demand signal received is hardware command, then this command signal is sent to the CLB module 2 in FPGA module by performance element EU, if the external demand signal received is software command, then CPU module traditionally processes, only have when CPU module 1 is given an order, follow-up peripheral hardware is according to the corresponding work of order, only receive corresponding order just to work, not so continue to disconnect, avoid taking resource, reduce power consumption,
Step 2, when CLB module 2 receives the hardware command that step 1 transmits, change the peripheral hardware on the computing machine of correspondence, concrete operations are as follows:
2.1) first set up instruction database: the hardware command corresponding to the change situation of all peripheral hardwares in CPU module 1 inside is numbered, each peripheral hardware 5 changes the corresponding coding of situation;
2.2) set up corresponding rule base: in FPGA module, corresponding step 2.1) in each coding, the operational order of corresponding control hardware is set;
2.3) when CPU module 1 receives external demand signal, according to step 2.1) in instruction database, external demand signal is sat in the right seat, then FPGA module searches the operational order corresponding with received numbering, this operational order is sent to inner CLB module 2, CLB module 2 controls corresponding peripheral hardware and changes, and namely controls the disconnection of peripheral hardware 5 and controls the access of peripheral hardware 5;
Step 3, when the hardware command received in step 2 is off the peripheral hardware order just at collecting work, CPU module 1 first reads hardware command, then the data in corresponding peripheral hardware are stored in storer 4, then opening operation is performed to the peripheral hardware 5 of correspondence, corresponding peripheral hardware 5 is deactivated circuit, thus saves power consumption.
Many peripheral hardwares low energy consumption computer architecture passes through CPU module under computer system, rationally nested and the utilization of FPGA resource, create a kind of many peripheral hardwares low energy consumption computer architecture control method, there is provided FPGA (Field Programmable Gate Array) according to the occasion that computing machine uses simultaneously, the infinitesimal System on Chip/SoC of High Performance DSP and computer processor, this monolithic device is utilized to make to be formed between CPU and peripheral hardware the mode of one-to-many, then the rationally nested of FPGA resource and application is utilized, in man-machine interaction, find the most effective executive mode, make the operation avoiding some unnecessary, the computer bus top number of packages under duty is intended to drop to minimum, realize arithmetic speed and reach the fastest.
Traditional computer architecture once shaping just immutable, and in the present invention, makes Peripheral Interface then all utilize FPGA to realize, like this, temporarily do not need the original paper used just can directly disconnect, both decreased the working time of original paper, add serviceable life, also improve service efficiency; In traditional computing machine, temporarily do not need the device used to be in sleep pattern, but sleep pattern also needs load to consume energy, and in the present invention, avoid the operation that some are unnecessary, take into account storer character simultaneously, greatly reduce energy consumption; In traditional computing machine, interface can only pipe peripheral hardware, even if similar is multiple, also must there is decoding scheme, and in the present invention, then utilize FPGA resource with the rationally nested of CPU and apply, thus in man-machine interaction, find the most effective executive mode, then can, with a whole peripheral hardware of interface management, not need the peripheral hardware of work to utilize CLB module to control to make it directly disconnect.
Claims (4)
1. the computer architecture of peripheral hardware low energy consumption more than a kind, it is characterized in that, comprise CPU module (1), the periphery of CPU module (1) is connected with some CLB modules (2) be embedded in FPGA module, each CLB module (2) is connected to the storer (4) in computing machine by interface (3), described storer (4) is connected with some peripheral hardwares (5) by bus.
2. one many peripheral hardwares low energy consumption computer architecture according to claim 1, is characterized in that, described interface (3) is the one in IOB interface, USB interface, USB interface.
3. a control method for the low energy consumption of peripheral hardware more than computer architecture, is characterized in that, specifically implement according to following steps:
Step 1, receive external demand signal when computing machine, external demand signal is sent to inner performance element EU by CPU module (1), then performance element EU judges external demand signal, if the external demand signal received is hardware command, then this command signal is sent to the CLB module (2) in FPGA module by performance element EU, if the external demand signal received is software command, then CPU module traditionally processes;
Step 2, when CLB module (2) receives the hardware command that described step 1 transmits, change the peripheral hardware on the computing machine of correspondence, concrete operations are as follows:
2.1) first set up instruction database: be numbered at the inner hardware command corresponding to the change situation of all peripheral hardwares of CPU module (1), each peripheral hardware (5) changes the corresponding coding of situation;
2.2) set up corresponding rule base: in FPGA module, corresponding described step 2.1) in each coding, the operational order of corresponding control hardware is set;
2.3) when CPU module (1) receives external demand signal, according to described step 2.1) in instruction database, external demand signal is sat in the right seat, then FPGA module searches the operational order corresponding with received numbering, this operational order is sent to inner CLB module (2), CLB module (2) controls corresponding peripheral hardware and changes;
Step 3, when the hardware command received in described step 2 is off the peripheral hardware order just at collecting work, CPU module (1) first reads hardware command, then the data in corresponding peripheral hardware are stored in storer (4), then opening operation is performed to the peripheral hardware (5) of correspondence, corresponding peripheral hardware (5) is deactivated circuit, thus saves power consumption.
4. the control method of a kind of many peripheral hardwares low energy consumption computer architecture according to claim 3, it is characterized in that, in described step 2, the peripheral hardware (5) on the computing machine of correspondence is changed and specifically comprise: peripheral hardware (5) disconnects and peripheral hardware (5) access.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109388541A (en) * | 2018-09-30 | 2019-02-26 | 联想(北京)有限公司 | A kind of control method and electronic equipment |
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| CN102929714A (en) * | 2012-10-19 | 2013-02-13 | 国电南京自动化股份有限公司 | uC/OS-II-based hardware task manager |
| CN103970058A (en) * | 2014-05-23 | 2014-08-06 | 哈尔滨工业大学 | Multifunctional modular circuit board |
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| EP1612656A2 (en) * | 2004-07-01 | 2006-01-04 | e-Storage Networks, Inc. | Data transmission device having the shape of a standard 3.5" disk |
| CN201673497U (en) * | 2010-05-28 | 2010-12-15 | 深圳华北工控股份有限公司 | Hot plug protection device of computer peripherals |
| CN102929714A (en) * | 2012-10-19 | 2013-02-13 | 国电南京自动化股份有限公司 | uC/OS-II-based hardware task manager |
| CN103970058A (en) * | 2014-05-23 | 2014-08-06 | 哈尔滨工业大学 | Multifunctional modular circuit board |
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| CN109388541A (en) * | 2018-09-30 | 2019-02-26 | 联想(北京)有限公司 | A kind of control method and electronic equipment |
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