CN201360219Y - Frequency converter I/O terminal and fault processing circuit - Google Patents

Abstract

The utility model relates to a frequency converter I/O terminal and a fault processing circuit. For the prior fault processing circuit, different functions are satisfied with more circuits and components, and the response speed is slow. The utility model comprises a plurality of fault detection circuits for outputting a fault detection signal, a digital signal processor and an ispMACH031 integrated circuit, and also comprises a plurality of external input terminals which are connected with the external I/O terminals and used for receiving the external input signal, a plurality of fault signal receiving terminals which are connected with the fault detection circuits and used for receiving the fault detection signal, a DSP terminal which is connected with the digital signal processor and used for receiving the defined signal of the input signal of the external terminal output by the digital signal processor and the input signal of the fault signal receiving terminals, and a signal input terminal which is connected with the digital signal processor and used for supplying signal for the digital signal processor. The utility model has the advantages of simple circuit structure and fast response speed.

Description

A kind of frequency converter I/O terminal and fault logic circuits

Technical field

The utility model relates to AC converter, relates in particular to frequency converter I/O terminal and fault logic circuits.

Background technology

AC converter is widely used in controlling asynchronous motor, and it is transformed to voltage, frequency with power frequency supply and becomes certain ratio to change, thereby realizes asynchronous motor is carried out accurately speed regulating control.

In the structure of AC converter, DSP (digital signal controller) can receive the signal of exterior I/O terminal input, also can receive the fault-signal of each testing circuit output, DSP to these signal processing after, output drives and control signal, so that asynchronous motor is carried out suitable control.

In the design of existing frequency converter I/O terminal input and fault logic circuits, need to satisfy different functions, and exist the slow problem of response speed with more circuit and components and parts.

Practical content

The purpose of this utility model is to provide a kind of frequency converter I/O terminal and fault logic circuits, to solve the slow problem of complex structure, response speed that exists in the traditional circuit.

According to above-mentioned purpose, frequency converter I/O terminal of the present utility model and fault logic circuits comprise:

A plurality of failure detector circuits, the output fault detection signal;

Digital signal processor (DSP); And

The ispMACH4032V integrated circuit comprises:

A plurality of external input terminals (X1-X6) link to each other with the I/O terminal of outside, are used to receive external input signal;

A plurality of fault-signals receive terminal, link to each other with above-mentioned a plurality of failure detector circuits, are used to receive fault detection signal;

DSP terminal (S1-S4) links to each other with this digital signal processor, receives the outside terminal of this digital signal processor output and the definition signal that fault-signal receives the input signal of terminal;

Signal output terminal (S5) links to each other with this digital signal processor, is used for providing output signal to this digital signal processor.

As mentioned above, the utility model has adopted the ispMACH4032V integrated circuit, utilizes its programmable functions, can define each port flexibly, has simplified circuit structure greatly, has improved response speed simultaneously, has improved protective value.

Description of drawings

Fig. 1 shows the schematic diagram of frequency converter I/O terminal of the present utility model and fault logic circuits.

Embodiment

As shown in Figure 1, the main body of frequency converter I/O terminal of the present utility model and fault logic circuits is: the integrated circuit (IC) 1 that model is ispMACH4032V, this integrated circuit has programmable functions.

The periphery of this integrated circuit (IC) 1 auxiliary element conventional, also include a plurality of failure detector circuit D1-D4 except some.These failure detector circuits D1-D4 is used to detect the various abnormal conditions of motor work, in case unusual circumstance, these failure detector circuits D1-D4 then can export corresponding fault-signal.In the utility model, these failure detector circuits can adopt traditional mode to design, and are not to be key point of the present utility model, so discuss no longer in detail here.And, though in the present embodiment, show four failure detector circuits, should be appreciated that how much can being decided according to the actual requirements of testing circuit quantity, present embodiment is not to be to restriction of the present utility model.

The utility model also comprises digital signal processor DSP, digital signal processor DSP is the vitals of frequency converter, it coordinates and is controlling the work of whole frequency converter, in the utility model, its main effect is each outside terminal of definition integrated circuit (IC) 1 and the character that fault-signal receives terminal (below will specifically describe).On the other hand, the digital signal processor DSP output signal of receiving integrate circuit IC1 also.

See also Fig. 1 again, integrated circuit (IC) 1 includes the sub-X1-X6 of a plurality of external input terminals.The sub-X1-X6 of these external input terminals (not shown) that links to each other with the I/O terminal of outside is used to receive outside input signal.Equally, it will be appreciated by those skilled in the art that in the present embodiment that the quantity of external input terminals can increase and decrease according to actual needs, should not be limited to 6 of present embodiment.

Integrated circuit (IC) 1 comprises that also a plurality of fault-signals receive terminal OC, OC*, OU, PL.These fault-signals reception terminals OC, OC*, OU, PL link to each other with failure detector circuit D1-D4, receive the fault detection signal of failure detector circuit D1-D4 output.The quantity of fault-signal reception terminal is general corresponding with the quantity of failure detector circuit.

Integrated circuit (IC) 1 also comprises a plurality of DSP terminal S1-S4, and these terminals link to each other with digital signal processor DSP.Digital signal processor DSP is used to define each outside terminal X1-X6 of integrated circuit (IC) 1 and the definition signal that fault-signal receives the input signal of terminal OC, OC*, OU, PL with generation, to define the content of the input signal that each terminal receives.Its definition signal can adopt the binary number signal of various combination.

Integrated circuit (IC) 1 also comprises a signal output terminal S5.During operate as normal, digital signal processor DSP at regular intervals, 2ms for example scans the outside port by the definition signal definition, when wherein the ports having state changes, the d type flip flop of integrated circuit (IC) 1 inside with this signal latch at lead-out terminal S5.Digital signal processor DSP then reads this signal by lead-out terminal S5, and in a conventional way, sends action command according to preprogram.

As mentioned above, in the utility model, made full use of the programmable functions of ispMACH4032V integrated circuit, defined exterior I/O port neatly, utilize the multiple gate circuit of IC interior simultaneously, input signal is carried out logical transition, satisfied the needs of difference in functionality.And utilize its inner latch that external fault is deciphered processing, the segmentation failure code has improved response speed, has improved protective value, makes whole system succinctly reliable.

Claims (1)

1, a kind of frequency converter I/O terminal and fault logic circuits is characterized in that, comprising:

A plurality of failure detector circuits, the output fault detection signal;

Digital signal processor (DSP); And

The ispMACH4032V integrated circuit comprises:

A plurality of external input terminals (X1-X6) link to each other with the I/O terminal of outside, are used to receive external input signal;

A plurality of fault-signals receive terminal, link to each other with above-mentioned a plurality of failure detector circuits, are used to receive fault detection signal;

DSP terminal (S1-S4) links to each other with this digital signal processor, receives the outside terminal of this digital signal processor output and the definition signal that fault-signal receives the input signal of terminal;

Signal output terminal (S5) links to each other with this digital signal processor, is used for providing output signal to this digital signal processor.

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