CN106896892A - One kind can eliminate metastable multi-power system power on detection circuit - Google Patents
One kind can eliminate metastable multi-power system power on detection circuit Download PDFInfo
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- CN106896892A CN106896892A CN201710017245.9A CN201710017245A CN106896892A CN 106896892 A CN106896892 A CN 106896892A CN 201710017245 A CN201710017245 A CN 201710017245A CN 106896892 A CN106896892 A CN 106896892A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
- G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
Abstract
The present invention proposes one kind and can eliminate metastable multi-power system power on detection circuit.The main nor gate being input into by external power source, external power source level detection unit, N number of internal electric source, the detection of N number of internal power level and level conversion unit and N+1 of the power on detection circuit, the output of the external power source level detection unit and the detection of N number of internal power level and the output of level conversion unit are collectively forming the N+1 inputs of the nor gate；The output of the nor gate is the final output of power on detection circuit；In the detection of each internal power level and level conversion unit, by increasing initial state latch, it is used to set the initial value of internal power level conversion signal (nor gate input signal corresponding with internal electric source), and latched, until internal power source voltage is just discharged after reaching the internal electric source detection threshold value of setting, there is metastable state so as to eliminate in upper electro-detection.
Description
Technical field
The present invention relates to a kind of multi-power system power on detection circuit.
Background technology
In current in large-scale circuit system, in order to reduce power consumption, performance is improved, majority uses multi-power system.It is more electric
The circuit system that source powers will detect each power supply electrifying situation except strictly to control electric sequence, also, according to actually electricity
Situation determines unlatching etc. of internal module, and no matter electric sequence or detection control go wrong, and can all cause serious consequence, example
Such as bolt-lock effect (latch up).
It is as shown in Figure 1 a typical double power-supply system power on detection circuit.Assuming that external power source VDD is equal to 3.3V,
Internal electric source VINT is equal to 1.8V, is produced by inner linear voltage-stablizer (LDO).LDO is powered by VDD.First to electricity on VDD；VDD
VDD_READY signals upset after detection threshold value is reached, LDO is opened, VINT is produced；VINT is then turned on after reaching detection threshold value
The logic module that inside is powered by VINT.
Wherein VDD_READY follows VDD, VDD to reach VDD_ after detection threshold value (target) in VDD uphill process
READY step-downs；
LDO is opened after VDD_READY step-downs, VINT is produced；Before LDO unlatchings, VINT values are not in relatively low true
Definite value, VINT is raised after LDO unlatchings；
Before VINT is raised to detection threshold value, VINT_READY follows VINT to change；
Because VINT_READY is the signal of VINT level ranges, it is necessary to a level translator converts the signal into VDD
The signal of voltage range；But before due to the logic level needed for reaching Digital Logical Circuits normal work in VINT level,
Level conversion unit cannot the output (VINT_READY_H) of normal work, i.e. level conversion unit be a uncertain value；
POWER_READY is the final output of voltage detecting circuit, and the signal all reaches respective detection in VDD and VINT
Before threshold value, POWER_READY need to always remain as low；
But reach detection threshold value in VDD, VINT level also very low (being less than logic working level) when (a stages in Fig. 2),
VINT_READY_H does not know；That is VINT_READY_H is possible to as low, and POWER_READY is in this case
Height, this will result in logic error, and the module for causing POWER_READY to control is opened in advance, causes VINT to be set up because of power consumption
Slowly, vibrate, or even cannot set up.
The content of the invention
In order to avoid occurring metastable state in upper electro-detection, the present invention proposes electro-detection on a kind of improved multi-power system
Circuit structure.
The power on detection circuit is mainly constituted by with lower unit：
External power source；
External power source level detection unit, when external power source level is less than sets target value, unit output follows outer
Portion's power supply, after external power source level is higher than sets target value, is output as low；
Receive N number of internal electric source that the external power source is powered, each internal electric source individually sets its detection threshold value；
N number of internal power level detection and level conversion unit；And
N+1 input nor gate, the output of the external power source level detection unit and N number of internal power level detection and
The output of level conversion unit is collectively forming the N+1 inputs of the nor gate；The output of the nor gate is power on detection circuit
Final output；
Each internal power level is detected and level conversion unit includes a level sensitive circuit, a level translator and
Initial state latch；Wherein,
Level sensitive circuit is used to detect corresponding internal power level, when phase of certain internal power level less than setting
When answering detection threshold value, level sensitive circuit output follows corresponding internal electric source, phase of the internal power level higher than setting
Answer after detection threshold value, the level detection exports low level；
Level translator is used to by internal electric source scope be converted to the output logic level of internal electric source detection unit outward
Portion's power range；
Initial state latch, is used to set respectively the initial value of certain level translator, and is locked, until accordingly
Internal power level is discharged again after reaching the detection threshold value of the internal electric source of setting；The input of initial state latch takes
The output signal of the respective inner power detecting unit and corresponding level translator, the output of the initial state latch is and institute
State the corresponding nor gate input signal of internal electric source.
Based on above technical scheme, the present invention has also further made following optimization：
Each internal electric source can be produced by the external power source by single inner linear voltage-stablizer LDO.
The particular circuit configurations of initial state latch include：
One phase inverter for working in external power source level range, is used to the VDD_ for exporting external power source level detection unit
READY signal is negated；
One PMOS transistor, is driven by the signal that negates of VDD_READY, is used to set the first of the initial state latch
Value；
One phase inverter for working in internal power level scope, is used to the VINT_READY letters for exporting level sensitive circuit
Number negate；
One nmos pass transistor, the pre-driver as the initial state latch is driven by the signal that negates of VINT_READY
It is dynamic, when VINT_READY is after negating signal for height, discharge latch state；
One nmos pass transistor, as switch, is used to prevent electric leakage occur during the initial state latch initialization；
One nor gate, input is respectively the output of initial value and level translator, is after output signal is inverted
VINT_READY_LATCH；
One phase inverter is connected between the input of nor gate and output, and the feedback as the initial state latch is anti-phase
Device；
The output signal of nor gate is overturn and does logic with VDD_READY and produces power on detection circuit most by one phase inverter
POWER_READY is exported eventually.
The invention has the advantages that：
By increasing initial state latch, be used to set internal power level conversion signal (it is corresponding with internal electric source or
Non- gate input signal) initial value, and latched, until internal power source voltage reach setting internal electric source detection threshold value it
Just discharged afterwards.Therefore, when latch discharges, the output of level translator has generally had the value of determination (usually high
Level), there is metastable state so as to eliminate in upper electro-detection.
Brief description of the drawings
Fig. 1 is existing power on detection circuit.
Fig. 2 is existing upper electro-detection sequential.
Fig. 3 is the basic structure of power on detection circuit of the invention.
Fig. 4 is the initial state latch circuit in the present invention.
Fig. 5 is the upper electro-detection sequential of embodiment illustrated in fig. 3.
Fig. 6 is power on detection circuit example of the invention.
Specific embodiment
Such as Fig. 3, shown in Fig. 4, the present embodiment is the example of double power-supply system, respectively external power source VDD, by external power source
The internal electric source VINT that the LDO of power supply is produced.By increasing initial state latch, it is used to set VINT_READY_LATCH initial
Value, and is latched, until VINT voltages are just discharged after reaching the VINT detection threshold values of setting.Therefore, latch is worked as
During release, the output VINT_READY_H of level translator has generally had the value (usually high level) of determination, so as to avoid
The abnormal logic that VINT_READY_LATCH and POWER_READY occurs.Concrete structure includes：
One external power source VDD, is that inner linear voltage-stablizer (LDO) and partial interior circuit provide supply voltage；
One inner linear voltage-stablizer (LDO), for partial interior circuit provides power supply；
One VDD detection units, are used to detect VDD level, when VDD level be less than sets target value when, the unit output with
With VDD, VDD is output as low higher than after sets target value；
One VINT detection units, are used to detect VINT level, when VINT level is less than sets target value, unit output
VINT, VINT is followed to be output as low higher than after sets target value；
One level translator, is used to for the output logic level of VINT detection units to be converted to VDD scopes by VINT scopes；
When VINT level is too low, level translator output is uncertain；
One initial state latch, is used to set VINT_READY_LATCH initial values, and is latched, until VINT voltages
Reach and can just discharge after the detection threshold value of setting；
One or two input nor gate.
Wherein, the particular circuit configurations of initial state latch include：
One phase inverter for working in VDD level scope, is used to negate VDD_READY signals；
One PMOS transistor, is driven by the signal that negates of VDD_READY, is used to set the initial value of latch；
One phase inverter for working in VINT level ranges, is used to negate VINT_READY signals；
One nmos pass transistor, is used as the pre-driver of latch, is driven by the signal that negates of VINT_READY, works as VINT_
READY negate signal for height after, discharge latch state；
One nmos pass transistor, as switch, is used to prevent electric leakage occur during latch initialization；
One nor gate, input is respectively the output of initial value and level translator, is after output signal is inverted
VINT_READY_LATCH；
One phase inverter is connected between the input of nor gate and output, the feedback inverter as latch；
The output signal of nor gate is overturn and does logic with VDD_READY and produces POWER_READY by one phase inverter.
Assuming that VDD value is 3.3V, VDD detection threshold values voltage is 2.7V；Assuming that VINT voltages are 1.8V, VINT detection threshold values
Voltage is 1.5V；Assuming that the minimum VINT operating voltages of level translator are 0.7V.The upper electro-detection process of the present embodiment is specific
It is as follows：
1.VDD is begun to ramp up by 0V, and VDD_READY signals follow VDD to rise.
2.c point voltages are maintained low, and P1 pipes are opened, and N2 pipes shut-off, a level points are uprised with VDD, and b level points are drawn by NOR1
Low, VINT_READY_LATCH is height, and the setting of VINT_READY_LATCH initial states is completed.
When 3.VDD rises to 2.7V, VDD_READY step-downs.
4. now c points are uprised, P1 pipes shut-off, N2 pipes open, now latch state by N1 pipes Determines；
5. simultaneously, LDO starts working, and produces VINT, and VINT voltages are from low toward High variation；
6. VINT be less than 0.7V when, level translator cannot normal work, output voltage VINT_READY_H do not know；
7. when VINT is less than 0.7, the shut-off of N1 pipes, by INV1 clampers in high level, therefore NOR1 outputs will not for a level points
Influenceed by VINT_READY_H, i.e. b is low, and VINT_READY_LATCH is height, and POWER_READY remains low；
8., when VINT is higher than 0.7V, during less than 1.5V, level translator normal work, VINT_READY is height, ON_
VINT_H is height, and b points are low, and VINT_READY_LATCH is height, and POWER_READY is low；
9. after VINT rises above 1.5V, VINT_READY step-downs；
10. now, INV4 upsets, d points are uprised, and N pipes drag down a points；
11. simultaneously, level translator output switching activity, VINT_READY_H step-downs, and NOR1 states upset, b points are uprised,
VINT_READY_LATCH step-downs；
12. due to the step-down of ON_VDD before, and after VINT_READY_LATCH step-downs, NOR2 states are turned over
Turn, POWER_READY is uprised, upper electric and upper electro-detection is completed.
13. when VINT is due to internal power consumption or other reasonses reduction, and during less than 1.5V, the output of VINT electrical measurements unit by
Low to be changed into height, now a dotted states remain low constant, and VINT_READY_H is uprised, and VINT_READY_LATCH is uprised, POWER_
READY step-downs, represent that power-supply system occurs abnormal.
Fig. 6 is the example of electro-detection on multi-power system, N number of to be supplied by VDD comprising an external power source VDD in this example
The internal electric source VINT1 ... VINTN that the LDO of electricity is produced, N number of internal power level detection and level conversion unit, are used to detect
Output is simultaneously transformed into VDD logic levels, and level detection and level conversion unit all with just by respective inner power level
Primary state sets and latch function, to eliminate the metastable state in power up.Wherein, N is the integer more than or equal to 1.
Claims (3)
1. one kind can eliminate metastable multi-power system power on detection circuit, it is characterised in that including
External power source；
External power source level detection unit, when external power source level is less than sets target value, unit output follows external electrical
Source, after external power source level is higher than sets target value, is output as low；
Receive N number of internal electric source that the external power source is powered, each internal electric source individually sets its detection threshold value；
N number of internal power level detection and level conversion unit；And
The nor gate of N+1 inputs, the output of the external power source level detection unit and the detection of N number of internal power level and level
The output of converting unit is collectively forming the N+1 inputs of the nor gate；The output of the nor gate is the final of power on detection circuit
Output；
Each internal power level is detected and level conversion unit includes that a level sensitive circuit, a level translator and one are initial
State latch；Wherein,
Level sensitive circuit is used to detect corresponding internal power level, when corresponding inspection of certain internal power level less than setting
When surveying threshold value, level sensitive circuit output follows corresponding internal electric source, corresponding inspection of the internal power level higher than setting
Survey after threshold value, level detection output low level；
Level translator is used to for the output logic level of internal electric source detection unit to be converted to external electrical by internal electric source scope
Source range；
Initial state latch, is used to set respectively the initial value of certain level translator, and is locked, until corresponding internal
Power level is discharged again after reaching the detection threshold value of the internal electric source of setting；The input of initial state latch takes described
The output signal of respective inner power detecting unit and corresponding level translator, the output of the initial state latch is interior with described
The corresponding nor gate input signal of portion's power supply.
It is 2. according to claim 1 can to eliminate metastable multi-power system power on detection circuit, it is characterised in that：Often
Individual internal electric source is produced by the external power source by single inner linear voltage-stablizer LDO.
It is 3. according to claim 1 can to eliminate metastable multi-power system power on detection circuit, it is characterised in that：Institute
The particular circuit configurations for stating initial state latch include：
One phase inverter for working in external power source level range, is used to the VDD_ for exporting external power source level detection unit
READY signal is negated；
One PMOS transistor, is driven by the signal that negates of VDD_READY, is used to set the initial value of the initial state latch；
One phase inverter for working in internal power level scope, is used to take the VINT_READY signals that level sensitive circuit is exported
Instead；
One nmos pass transistor, the pre-driver as the initial state latch is driven by the signal that negates of VINT_READY, when
VINT_READY negate signal for height after, discharge latch state；
One nmos pass transistor, as switch, is used to prevent electric leakage occur during the initial state latch initialization；
One nor gate, input is respectively the output of initial value and level translator, and VINT_ is after output signal is inverted
READY_LATCH；
One phase inverter is connected between the input of nor gate and output, the feedback inverter as the initial state latch；
The output signal of nor gate is overturn and does logic with VDD_READY and produces the final defeated of power on detection circuit by one phase inverter
Go out POWER_READY.
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| CN201710017245.9A CN106896892B (en) | 2017-01-10 | 2017-01-10 | One kind can eliminate metastable multi-power system power on detection circuit |
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| CN201710017245.9A CN106896892B (en) | 2017-01-10 | 2017-01-10 | One kind can eliminate metastable multi-power system power on detection circuit |
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| CN106896892B CN106896892B (en) | 2019-07-05 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112800000A (en) * | 2019-11-14 | 2021-05-14 | 海思光电子有限公司 | Circuit and electronic equipment |
| CN114387932A (en) * | 2022-01-18 | 2022-04-22 | 北京奕斯伟计算技术有限公司 | Protection circuit and protection method, output unit, source driver and display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4716322A (en) * | 1986-03-25 | 1987-12-29 | Texas Instruments Incorporated | Power-up control circuit including a comparator, Schmitt trigger, and latch |
| CN107430412A (en) * | 2015-04-10 | 2017-12-01 | 高通股份有限公司 | The daisy chained voltage stability of consumer is interdependent staggeredly to be powered up |
-
2017
- 2017-01-10 CN CN201710017245.9A patent/CN106896892B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4716322A (en) * | 1986-03-25 | 1987-12-29 | Texas Instruments Incorporated | Power-up control circuit including a comparator, Schmitt trigger, and latch |
| CN107430412A (en) * | 2015-04-10 | 2017-12-01 | 高通股份有限公司 | The daisy chained voltage stability of consumer is interdependent staggeredly to be powered up |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112800000A (en) * | 2019-11-14 | 2021-05-14 | 海思光电子有限公司 | Circuit and electronic equipment |
| CN112800000B (en) * | 2019-11-14 | 2023-07-18 | 海思光电子有限公司 | Circuit and electronic equipment |
| CN114387932A (en) * | 2022-01-18 | 2022-04-22 | 北京奕斯伟计算技术有限公司 | Protection circuit and protection method, output unit, source driver and display device |
| CN114387932B (en) * | 2022-01-18 | 2022-12-16 | 北京奕斯伟计算技术股份有限公司 | Protection circuit and protection method, output unit, source driver and display device |
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| CN106896892B (en) | 2019-07-05 |
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