CN201177652Y - Test system for circuit board - Google Patents
Test system for circuit board Download PDFInfo
- Publication number
- CN201177652Y CN201177652Y CNU2008200930744U CN200820093074U CN201177652Y CN 201177652 Y CN201177652 Y CN 201177652Y CN U2008200930744 U CNU2008200930744 U CN U2008200930744U CN 200820093074 U CN200820093074 U CN 200820093074U CN 201177652 Y CN201177652 Y CN 201177652Y
- Authority
- CN
- China
- Prior art keywords
- test
- circuit board
- testing
- board under
- under test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The utility model discloses a circuit board test system, which comprises a test fixture, a test circuit board and a display terminal, wherein the test fixture is used for fixing a circuit board to be tested and includes test pins contacting each test point in the test item of the circuit board to be tested; and a microcontroller is arranged on the test circuit board for controlling the test circuit board to provide a test signal to the circuit board to be tested through the test pins on the test fixture, acquiring the returned test data, analyzing the test result, and providing the result on a display terminal for displaying the result. By establishing an intelligent test platform, the test system can rapidly test the circuit board to locate the hardware problem, thereby improving the test board test efficiency.
Description
Technical field
The utility model relates to a kind of test macro of circuit board.
Background technology
Develop rapidly along with electron trade, increasing device trends towards the integrated level height, direction that volume is little develops, this has proposed very high requirement to extensive paster solder technology, this high request of solder technology makes the phenomenon that occurs rosin joint, short circuit in the welding process unavoidably, thereby this detects with regard to the circuit board that requires butt welding to connect to finish.Yet, for circuit board, depend merely on that the technician is Pork-pieces by rule of thumb to come the investigation problem with thousands of components and parts, be the very difficult thing of part.Especially produce in enormous quantities in the circuit boards, the testing of circuit board is very careful, loaded down with trivial details especially, this manual detection mode more inefficiency that seems.
The utility model content
Technical problem to be solved in the utility model is: a kind of test macro of circuit board is provided, can tests circuit board all sidedly fast, location hardware problem place, the work efficiency of raising maintenance, testing circuit plate hardware.
In order to solve the problems of the technologies described above, the utility model adopts following technical scheme:
A kind of test macro of circuit board, comprise test fixture, testing circuit board and display terminal, described test fixture is used for fixing circuit board under test, and has the testing needle that each test point in the test item with described circuit board under test is joined, described testing circuit board is provided with microcontroller, described microcontroller is used to control testing circuit board provides the testing needle of test signal on described test fixture to circuit board under test, obtain the test data of returning and analyze test result, be provided to described display terminal and show.
The test item of described circuit board under test comprises the interface testing of circuit board under test, described interface testing comprises pairing interface testing and non-matching interface testing, pairing interface in the described pairing interface testing is connected to form by the relay that is provided with on the described circuit board under test by the two-way I/O port on the circuit board under test is matched.
Described non-matching interface testing is self-looped testing.
In described pairing interface testing, described relay is the double-throw relay, is used for that two two-way I/O ports of a two-way I/O port and other are carried out switchable pairing and is connected.
The test item of described circuit board under test also comprises the chip testing of circuit board under test, and described chip testing comprises programmable chip test and non-programmable chip testing.
The test item of described circuit board under test also comprises the peripheral circuit test of circuit board under test.
The utility model is according to self functional characteristics of circuit board, built an intelligence test platform, the customized test fixture that cooperates with circuit board under test, provide test signal that circuit board under test is tested by microcontroller, and test result shown by display terminal, thereby can test the location hardware problem apace to circuit board.
Especially the utility model docking port in interface testing is distinguished, and adopts the mode of pairing test and self-looped testing respectively, has further improved testing efficiency.
Test of the present utility model has comprised the test of interface, chip and peripheral circuit to circuit board under test all sidedly, thereby more comprehensive.
Description of drawings
Fig. 1 is the test macro block diagram of the utility model embodiment;
Fig. 2 is the interface testing connection layout of the utility model embodiment;
Fig. 3 is the micro controller module figure of the utility model embodiment;
Fig. 4 is the microcontroller initialization flowchart of the utility model embodiment;
Fig. 5 is the microcontroller test flow chart of the utility model embodiment.
Embodiment
Below in conjunction with the drawings and the specific embodiments the utility model is described in further detail.
As shown in Figure 1, the utility model test clamp is fixed circuit board to be measured, test fixture comprises test bench and testing needle, test bench is used to carry circuit board under test, the quantity of testing needle and the position of distribution are then carried out customized according to the circuit board unique characteristics of circuit board under test, for example confirm that the hardware interface to be measured on the circuit board to be measured comprises external interface, program download interface, power interface, reseting interface etc.The customization test fixture makes that the pin of testing needle and each interface is corresponding one by one also can contact fully when testing, thereby can avoid the damage of interface pin.Test fixture can also add reometer, power switch, button, pilot lamp etc. according to the needs of self.
Testing circuit board is used to provide test signal to circuit board under test, by the microcontroller on the testing circuit board (MCU), can control carrying out which kind of test.Testing circuit board then provides various application circuits so that according to the control of microcontroller, produce various test signals.For example testing circuit board can be according to circuit board hardware interface feature, and increasing simulation provides peripheral circuit required translation interface, so that can test the peripheral circuit of circuit board under test.Or, then on testing circuit board, add booster circuit or reduction voltage circuit as needing digital-to-analogue (DA) sampled value on the circuit board under test, and switch different voltage by relay, reach the effect of analog sampling value.The analog sampling value is by the control of microcontroller, be applied on the testing needle of test fixture, be delivered to corresponding test point by testing needle, by reading sampled value, just can determine whether the voltage on the test point is correct, thereby can investigate the peripheral circuit of circuit board, detect hardware problems such as the resistance size is whether correct.
Testing circuit board links to each other with display terminal, display terminal for example can be a personal computer (PC), testing circuit board is connected with PC by serial ports, MCU obtains the test data that circuit board under test returns, analysis obtains test result, can show by the display of PC then, thereby reach the purpose of automatic test, testing efficiency is provided.
For the test item of circuit board under test, can be divided into interface testing, chip testing and peripheral circuit test usually, respectively these several test items are described below.
Interface testing comprises pairing interface testing and non-matching interface testing.Generally, can adopt the pairing interface testing for two-way I/O (I/O) mouth.Other interfaces then can adopt self-looped testing.
The pairing interface testing adopts detection height state to determine whether pin is correct.At first the I/O mouth is matched, match connection by the relay that is provided with on the testing circuit board.Usually adopt I/O mouth mutual connection pairing in twos, this quantity that requires the I/O mouth is even number, therefore do not satisfying this requirement or for the purpose that reduces relay, can use the double-throw relay to switch pairing connects, promptly realize that by the double-throw relay I/O mouth can match with two I/O mouths, a test constantly, the I/O mouth with link to each other with one of I/O mouth of its pairing, in another test constantly, by the switching of double-throw relay, the I/O mouth with link to each other with another I/O mouth of its pairing.After pairing connects, by MCU, being provided with wherein one the tunnel is the way of output, and another road is an input mode, according to being output as 1,0 state, judge whether input is corresponding 1,0 state, allows its both sides' state change mutually conversely, and whether test mode is correct again, as the state that reads is correct, can judge that this a pair of I/O mouth is normal, errors excepted, can conclude that device goes wrong on pin short circuit, rosin joint or this link.For the non-matching interface, can adopt from ring and detect, promptly send test massage by input interface, obtain corresponding test signal to determine whether the non-matching interface is normal from corresponding output interface.
As shown in Figure 2, be example with the MODEM interface, the function pin of MODEM interface comprises CTS, RTS, DTR, CD, RI, DSR, RX, TX, this wherein, except that these two pins of RX, TX, other 6 pins all are the I/O pin, and can match one by one becomes the pairing interface; RX, TX then are the non-matching interface.According to the feature of circuit, 6 pin TX and 8 pin RX detect by encircling certainly, send data by TX, and RX receives data, and whether correct, thereby judge whether two pins is normal if detecting transceive data.Other I/O pin then judges whether correct by the pairing test.In order to reduce the use of relay, do not adopt matching method one to one in this example, and all adopted a pair of two matching method, finish the mutual connection of pairing interface by the double-throw relay.Wherein, 7 pin DTR are connected with 2 pin RI, 4 pin DSR by the double-throw relay, by pilot relay, can switch DTR and test with RI, DSR pairing respectively; Same mode, 5 pin RTS are connected with 10 pin GD, 3 pin CTS by the double-throw relay, by pilot relay, reach the purpose of pairing test 5,10,3 pin.
For the RS232 interface on the circuit board, the RS485 interface can by certainly the ring judge whether transceive data correct, thereby judge whether hardware normal.Same, for other I/O pins that can match on the circuit board, adopt the mode of pairing test.
For the chip testing of circuit board under test, be programmable integrated circuit (IC) as fruit chip, can judge whether IC is working properly by chip is read and write.For example the DS1302 clock chip by IC being write the clock of reading chip, can confirm whether IC is normal.And for non-programmable chip, can carry out functional logic to it by testing circuit board to judge that aanalogvoltage that for example can the detection chip pin is to judge whether it is normal.
The peripheral circuit test of circuit board under test, for example power circuit of circuit board under test or the like can judge whether the voltage of test point or electric current be normal by the test point of choosing in the peripheral circuit is tested, thereby determines whether peripheral circuit is normal.
Circuit board testing of the present utility model system, cooperation by MCU and testing circuit board, finish test to circuit board under test, and testing result passed through serial ports, for example the RS232 serial ports offers the PC terminal and shows, thereby energy is quick, the reason of location hardware problem accurate, directly perceived, has improved the efficient of investigation circuit board hardware problem.
Again an explanation is done in the test of MCU below, MCU is divided into two parts: actuating section and part of detecting.Be startup module and test module shown in Figure 3.Actuating section wherein is Synchronous Dynamic Random Access Memory (SDRAM) lining that operates in MCU inside, and its effect is main to be necessary hardware setting and detection, starts guiding and starts part of detecting; And part of detecting is to operate in the outside SDRAM, and tested unit is carried out hardware testing, and part of detecting is made up of bottom layer driving, and bottom layer driving is used modular design, and the access interface of necessity is provided for the design of upper layer application layer.Wherein the bottom hardware driver comprises: interfaces such as I/O driving, Serial Peripheral Interface (SPI) driving, universal serial bus (I2C) driving, Sheffer stroke gate type flash memory (NANDFLASH) driving, RS232 driving, RS485 driving, CPU interruption drive.As shown in Figure 4, the initialization flow process of MCU comprises:
Startup-program code comprises the setting of the necessary register of setting, storehouse setting, aborted initialization, CPU of vector table;
Initialization clock, debug serial port, outside SDRAM are test for external SDRAM then, start XMODEM and receive agreement, duplicate test module in outside SDRAM, guide test module at last.
As shown in Figure 5, the testing process of MCU comprises the setting of the interrupt vector of resetting storehouse size, necessity, is the short circuit of test CPU pin, test LED etc., MODEM power interface, external alarm interface, control interface, data type flash memory (DATAFLASH), analog to digital converter (ADC), NANDFLASH, RS232 serial ports, RS485 serial ports etc. then.
Test macro of the present utility model has been built an intelligence test platform, not only can finish circuit board testing fast, and test simultaneously comprehensively.
Above content be in conjunction with concrete preferred implementation to further describing that the utility model is done, can not assert that concrete enforcement of the present utility model is confined to these explanations.For the utility model person of an ordinary skill in the technical field, under the prerequisite that does not break away from the utility model design, can also make some simple deduction or replace, all should be considered as belonging to protection domain of the present utility model.
Claims (7)
1. the test macro of a circuit board, it is characterized in that, comprise test fixture, testing circuit board and display terminal, described test fixture is used for fixing circuit board under test, and has the testing needle that each test point in the test item with described circuit board under test is joined, described testing circuit board is provided with microcontroller, described microcontroller is used to control testing circuit board provides the testing needle of test signal on described test fixture to circuit board under test, obtain the test data of returning and analyze test result, be provided to described display terminal and show.
2. test macro as claimed in claim 1, it is characterized in that, the test item of described circuit board under test comprises the interface testing of circuit board under test, described interface testing comprises pairing interface testing and non-matching interface testing, pairing interface in the described pairing interface testing is connected to form by the relay that is provided with on the described circuit board under test by the two-way I/O port on the circuit board under test is matched.
3. test macro as claimed in claim 2 is characterized in that, described non-matching interface testing is self-looped testing.
4. test macro as claimed in claim 2 is characterized in that, in described pairing interface testing, described relay is the double-throw relay, is used for that two two-way I/O ports of a two-way I/O port and other are carried out switchable pairing and is connected.
5. as the arbitrary described test macro of claim 1 to 4, it is characterized in that the test item of described circuit board under test also comprises the chip testing of circuit board under test, described chip testing comprises programmable chip test and non-programmable chip testing.
6. as the arbitrary described test macro of claim 1 to 4, it is characterized in that the test item of described circuit board under test also comprises the peripheral circuit test of circuit board under test.
7. as the arbitrary described test macro of claim 5, it is characterized in that the test item of described circuit board under test also comprises the peripheral circuit test of circuit board under test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200930744U CN201177652Y (en) | 2008-04-02 | 2008-04-02 | Test system for circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200930744U CN201177652Y (en) | 2008-04-02 | 2008-04-02 | Test system for circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201177652Y true CN201177652Y (en) | 2009-01-07 |
Family
ID=40217675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2008200930744U Expired - Fee Related CN201177652Y (en) | 2008-04-02 | 2008-04-02 | Test system for circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201177652Y (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102401877A (en) * | 2010-09-16 | 2012-04-04 | 南亚科技股份有限公司 | Test system |
| CN103165203A (en) * | 2011-12-14 | 2013-06-19 | 中国广东核电集团有限公司 | Detection method for nuclear power station circuit board component |
| CN103454575A (en) * | 2013-09-06 | 2013-12-18 | 福州瑞芯微电子有限公司 | System, PCBA board and method for achieving PCBA board testing |
| CN103727981A (en) * | 2013-12-27 | 2014-04-16 | 上海欣丰电子有限公司 | Testing device for fan disk mainboard |
| CN105510802A (en) * | 2015-12-04 | 2016-04-20 | 浙江佳乐科仪股份有限公司 | DSP control-based single board test system |
| CN106970318A (en) * | 2017-04-25 | 2017-07-21 | 金卡智能集团股份有限公司 | Measuring instrument circuit board intelligent test system and intelligent test method |
| CN108594106A (en) * | 2018-04-12 | 2018-09-28 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | System level chip assessment device and method |
| CN108776297A (en) * | 2018-07-26 | 2018-11-09 | 四川长虹网络科技有限责任公司 | Circuit board detection device and method |
| CN111474463A (en) * | 2020-04-27 | 2020-07-31 | Oppo（重庆）智能科技有限公司 | Circuit board test system, circuit board test host and circuit board test method |
| CN111999640A (en) * | 2020-07-22 | 2020-11-27 | 国营芜湖机械厂 | Circuit board testing system based on cabinet and testing method thereof |
-
2008
- 2008-04-02 CN CNU2008200930744U patent/CN201177652Y/en not_active Expired - Fee Related
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102401877B (en) * | 2010-09-16 | 2014-01-29 | 南亚科技股份有限公司 | Test system |
| CN102401877A (en) * | 2010-09-16 | 2012-04-04 | 南亚科技股份有限公司 | Test system |
| CN103165203B (en) * | 2011-12-14 | 2016-04-13 | 中国广核集团有限公司 | Detection method for nuclear power station circuit board component |
| CN103165203A (en) * | 2011-12-14 | 2013-06-19 | 中国广东核电集团有限公司 | Detection method for nuclear power station circuit board component |
| CN103454575A (en) * | 2013-09-06 | 2013-12-18 | 福州瑞芯微电子有限公司 | System, PCBA board and method for achieving PCBA board testing |
| CN103454575B (en) * | 2013-09-06 | 2016-03-09 | 福州瑞芯微电子股份有限公司 | For realizing system, PCBA board and method that PCBA board is tested |
| CN103727981A (en) * | 2013-12-27 | 2014-04-16 | 上海欣丰电子有限公司 | Testing device for fan disk mainboard |
| CN105510802A (en) * | 2015-12-04 | 2016-04-20 | 浙江佳乐科仪股份有限公司 | DSP control-based single board test system |
| CN106970318A (en) * | 2017-04-25 | 2017-07-21 | 金卡智能集团股份有限公司 | Measuring instrument circuit board intelligent test system and intelligent test method |
| CN108594106A (en) * | 2018-04-12 | 2018-09-28 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | System level chip assessment device and method |
| CN108776297A (en) * | 2018-07-26 | 2018-11-09 | 四川长虹网络科技有限责任公司 | Circuit board detection device and method |
| CN111474463A (en) * | 2020-04-27 | 2020-07-31 | Oppo（重庆）智能科技有限公司 | Circuit board test system, circuit board test host and circuit board test method |
| CN111999640A (en) * | 2020-07-22 | 2020-11-27 | 国营芜湖机械厂 | Circuit board testing system based on cabinet and testing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN201177652Y (en) | Test system for circuit board | |
| CN101226224A (en) | Test system and method for circuit board | |
| CN109425824B (en) | Combined serial and parallel test access port selection in JTAG interfaces | |
| CN109144036B (en) | Manipulator simulation test system and test method based on FPGA chip | |
| CN101102566B (en) | A design method and debugging method for mobile phone JTAG debugging interface signals | |
| CN104133171A (en) | Simple boundary scan test system and method based on single-chip microcomputer | |
| CN106094804A (en) | A kind of cross-platform PLC plate level frock based on QT test system and method for testing thereof | |
| CN101799517B (en) | Sealing chip and sealing chip testing system | |
| CN103699014A (en) | Semi-physical simulation platform and semi-physical simulation control method of electromobile | |
| CN103105578A (en) | Testing system of universal chip | |
| CN110907798A (en) | Test verification board, test device and method for exchange chip of integrated SoC (System on chip) | |
| CN108761328A (en) | Electric tool switch test device and system | |
| WO2019227731A1 (en) | Display screen lighting-up test device and method | |
| CN101582688A (en) | Dynamic configuration circuit with FPGA loading mode | |
| CN202815143U (en) | Short/open-circuit testing circuit for flexible circuit board touch screen IC channel | |
| CN101184310A (en) | Test device for mobile phone | |
| CN219456850U (en) | PCIe Tx signal test code type switching device | |
| WO2021109049A1 (en) | Pcba intelligent automatic test method and system | |
| CN102955724A (en) | BIOS (basic input output system) test fixture and method using same for BIOS test | |
| CN202453478U (en) | Laptop battery monitoring system | |
| US20150285855A1 (en) | System with dual function load board | |
| CN102043695A (en) | Printed circuit board (PCB) supporting external automatic test equipment (ATE) and method for externally controlling same | |
| CN201025532Y (en) | Computer testing device | |
| CN201196777Y (en) | External connection interface test card | |
| CN203930004U (en) | A kind of intelligent digital integrated circuit fault detection system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| DD01 | Delivery of document by public notice |
Addressee: Guoren Communication Co., Ltd., Shenzhen Document name: Notification of Termination of Patent Right |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090107 Termination date: 20110402 |