CN201163624Y - Labeling type insulation packaging structure - Google Patents

Labeling type insulation packaging structure Download PDF

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Publication number
CN201163624Y
CN201163624Y CN 200820055351 CN200820055351U CN201163624Y CN 201163624 Y CN201163624 Y CN 201163624Y CN 200820055351 CN200820055351 CN 200820055351 CN 200820055351 U CN200820055351 U CN 200820055351U CN 201163624 Y CN201163624 Y CN 201163624Y
Authority
CN
China
Prior art keywords
metal
pin
insulation
smd
silica gel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN 200820055351
Other languages
Chinese (zh)
Inventor
牛志强
王兵
杨云康
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Seefull Electronic Co Ltd
Original Assignee
Shanghai Seefull Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Seefull Electronic Co Ltd filed Critical Shanghai Seefull Electronic Co Ltd
Priority to CN 200820055351 priority Critical patent/CN201163624Y/en
Application granted granted Critical
Publication of CN201163624Y publication Critical patent/CN201163624Y/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

The utility model provides a patch type insulated package structure, having four layers. An insulating medium is connected with a metal radiating rib through solder or silica gel; a metal pin support is connected with the insulating medium through the solder or the silica gel; a pin mounting surface of the metal pin support and a pin mounting surface of the metal radiating rib are in the same horizontal plane; one or a plurality of chips are welded in a welding zone of the metal pin support, and are connected with the metal pin support through one or a plurality of leads; and each surface of formed components is packaged by plastic cement in embedded state except that an exposed face of the metal radiating rib and the pin are exposed outside. The patch type insulated package structure has the advantages that: the degree of production automation for a high power insulating rectifier part is improved; the problem of insufficient radiation of patch type package is solved; the insulativity of the patch type package is reinforced; and a packageframe adopts high-density multi-row design with low cost.

Description

A kind of SMD insulation-encapsulated structure
Technical field
The utility model relates to a kind of insulation-encapsulated structure of chip, particularly a kind of SMD insulation-encapsulated structure that is used for the pin counter-rotating of power rectifier device.
Background technology
Electric tool and household electrical appliances adopt the power rectifier device more at present, owing to produce a large amount of heats during these device work, need the encapsulation of heat dispersion excellence that heat energy is derived, so thin outer rim (Thin outline) the pins type encapsulation of insulation is adopted in the encapsulation of these devices more, this encapsulating structure hot property excellence can satisfy the high-power chip instructions for use, but need manually cut the pin clubfoot when using, be unfavorable for the automation of producing having increased human cost; And this package dimensions is bigger, and heat directly exports on the pcb board during work, causes the pcb board integral layout to dwindle.For head it off, someone selects SMD thin outer rim encapsulation, but this encapsulating structure can not insulate, need be installed on the ceramic base, and automaticity is still not high, this encapsulating structure hot property is relatively poor, can not solve the heat dissipation problem of high-power chip effectively, can only be applied to low power rectifying device.
The utility model content
Technical problem of the present utility model is that a kind of packaging frame (leadframe) pin counter-rotating will be provided, and the back metal fin exposes high power device encapsulation production automation degree high SMD insulation-encapsulated structure.
In order to solve above technical problem, the utility model provides a kind of SMD insulation-encapsulated structure, this encapsulating structure is four layers, one dielectric is connected on the metal fin by scolder or silica gel, one metal pins support is connected with dielectric by scolder or silica gel, metal pins support pin installed surface and metal fin pin installed surface are in same horizontal plane, one chip or multiple chips are welded in the weld zone of metal pins support, chip is connected with the metal pins support by one or more lead-in wire, forming assembly removes the metal fin exposed face and pin is exposed outside, and all the other each faces are the embedding shape by the plastic cement encapsulation.
Described dielectric is a potsherd, or the macromolecule insulating trip.
Described metal fin, its end that exposes is one or more rectangular pins, pin is to the bending of encapsulation main body direction.
Described metal pins support, its pin is to the bending of encapsulation main body direction.
Superior effect of the present utility model is:
1) improved the degree of the high-power insulation rectifying device production automation;
2) solve the sufficient inadequately problem of SMD package cooling, and strengthened insulating properties;
3) packaging frame of the present utility model can adopt high density to arrange design more, and cost is low.
Description of drawings
Fig. 1 is a structural representation of the present utility model;
Fig. 2 is the front view of Fig. 1;
Fig. 3 is the rearview of Fig. 2;
Fig. 4 is the right view of Fig. 2;
Fig. 5 is the structural representation of the specific embodiment of the utility model pin;
Fig. 6 is the end view of Fig. 5;
Fig. 7 is the structural representation of another specific embodiment of the utility model pin;
Fig. 8 is the end view of Fig. 7;
Fig. 9 is the structural representation of another specific embodiment of the utility model pin;
Figure 10 is the end view of Fig. 9;
The number in the figure explanation:
The 1-fin;
101-fin pin; 102-fin exposed face;
103-fin pin installed surface;
The 2-dielectric;
3-pin support 301-pin;
302-pin installed surface;
The 4-chip;
5-lead-in wire 6-plastic cement;
Embodiment
See also shown in the accompanying drawing, the utility model will be further described.
As Fig. 1, Fig. 2 and shown in Figure 3, the utility model provides a kind of SMD insulation-encapsulated structure, this encapsulating structure is four layers, one dielectric 2 is connected on the metal fin 1 by scolder or silica gel, one metal pins support 3 is connected with dielectric 2 by scolder or silica gel, metal pins support installed surface 302 is in same horizontal plane with metal fin pin installed surface 103, one chip 4 or multiple chips 4 are welded in the weld zone of metal pins support 3, chip 4 is connected with metal pins support 3 by one or more lead-in wire 5, forming assembly removes metal fin exposed face 102 and pin 301 exposes outside, all the other each faces are the embedding shape by plastic cement 6 encapsulation, and metal fin exposed face 102 directly dispels the heat.
Described dielectric 2 is potsherds, or the macromolecule insulating trip.
As shown in Figure 1 and Figure 4, described metal fin 1, its end that exposes is one or more rectangular pins 101, pin 101 is to the bending of encapsulation main body direction.
As illustrated in fig. 4, described metal pins support 3, its pin 301 is to the bending of encapsulation main body direction.
This encapsulating structure is looked pin form difference multiple specific embodiment, as shown in Figure 5 and Figure 6, the end that described metal fin 1 exposes is a rectangular pins 101, pin 101 is to the bending of encapsulation main body direction, and it is at regular intervals apart from encapsulation main body, the pin 301 of metal pins support 3 is learnt from Fig. 6 also to the bending of encapsulation main body direction simultaneously, and metal pins support installed surface 301 is in same horizontal plane with metal fin pin installed surface 103.
As shown in Figure 7 and Figure 8, the end that described metal fin 1 exposes is a rectangular pins 101, pin 101 is to the bending of encapsulation main body direction, and be close to encapsulation main body on one side, the pin 301 of metal pins support 3 is also to the bending of encapsulation main body direction simultaneously, learn that from Fig. 8 metal pins support installed surface 301 is in same horizontal plane with metal fin pin installed surface 103.
As Fig. 9 and shown in Figure 10, the end that described metal fin 1 exposes is a fluking type rectangular pins 101, pin 101 is to the bending of encapsulation main body direction, the pin 301 of metal pins support 3 also is the fluking type pin simultaneously, and, learn that metal pins support installed surface 301 is in same horizontal plane with metal fin pin installed surface 103 to the bending of encapsulation main body direction from Figure 10.

Claims (4)

1, a kind of SMD insulation-encapsulated structure is characterized in that:
This encapsulating structure is four layers, one dielectric is connected on the metal fin by scolder or silica gel, one metal pins support is connected with dielectric by scolder or silica gel, metal pins support pin installed surface and metal fin pin installed surface are in same horizontal plane, one chip or multiple chips are welded in the weld zone of metal pins support, chip is connected with the metal pins support by one or more lead-in wire, forming assembly removes the metal fin exposed face and pin is exposed outside, and all the other each faces are the embedding shape by the plastic cement encapsulation.
2, by the described a kind of SMD insulation-encapsulated structure of claim 1, it is characterized in that:
Described dielectric is a potsherd, or the macromolecule insulating trip.
3, by the described a kind of SMD insulation-encapsulated structure of claim 1, it is characterized in that:
Described metal fin, its end that exposes is one or more rectangular pins, pin is to the bending of encapsulation main body direction.
4, by the described a kind of SMD insulation-encapsulated structure of claim 1, it is characterized in that:
Described metal pins support, its pin is to the bending of encapsulation main body direction.
CN 200820055351 2008-02-02 2008-02-02 Labeling type insulation packaging structure Expired - Lifetime CN201163624Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200820055351 CN201163624Y (en) 2008-02-02 2008-02-02 Labeling type insulation packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200820055351 CN201163624Y (en) 2008-02-02 2008-02-02 Labeling type insulation packaging structure

Publications (1)

Publication Number Publication Date
CN201163624Y true CN201163624Y (en) 2008-12-10

Family

ID=40184553

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200820055351 Expired - Lifetime CN201163624Y (en) 2008-02-02 2008-02-02 Labeling type insulation packaging structure

Country Status (1)

Country Link
CN (1) CN201163624Y (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339808A (en) * 2011-10-28 2012-02-01 无锡红光微电子有限公司 Packaging lead frame structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339808A (en) * 2011-10-28 2012-02-01 无锡红光微电子有限公司 Packaging lead frame structure

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CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20081210