CN201145897Y

CN201145897Y - Microcontroller

Info

Publication number: CN201145897Y
Application number: CNU200820054709XU
Authority: CN
Inventors: 岳卫杰; 张继文; 沈振杰; 潘松; 袁俊
Original assignee: Shanghai Hair Group Integated Circuit Co Ltd
Current assignee: Shanghai Hair Group Integated Circuit Co Ltd; Shanghai Haier Integrated Circuit Co Ltd
Priority date: 2008-01-15
Filing date: 2008-01-15
Publication date: 2008-11-05
Anticipated expiration: 2018-01-15

Abstract

The utility model relates to a microcontroller comprising a kernel component. The utility model also comprises the following parts: communication interface components used for giving off communication strobe signals and unified state machine signals according to the controlling instruction from the kernel component, peripherally-arranged components used for sending out or receiving data signals and address signals according to the unified state machine signals, a first multiple selector used for sending the data signals and the address signals to the peripherally-arranged components according to the communication strobe signals from the communication interface components, a second multiple selector used for sending the data signals and the address signals from the peripherally-arranged components to the kernel component according to the communication strobe signals. Since the microcontroller of the utility model adopts the communication interface components to proceed coordination to the communication of all the peripherally-arranged components, thereby avoiding the bus contention produced in adopting a bus addressing style and raising the reliability and whole property of the microcontroller.

Description

Microcontroller

Technical field

The utility model relates to a kind of microcontroller, relates in particular to a kind of microcontroller that can avoid the bus collision of external components.

Background technology

External components in the existing microcontroller mainly comprises: (UniversalAsynchronous Receiver/Transmitter is called for short: UART) parts, I universal asynchronous receiving-transmitting ²(Serial Peripheral Interface is called for short: SPI) multiple external components such as parts for C bus parts, Serial Peripheral Interface (SPI).Core component in the existing microcontroller mainly adopts the bus addressing mode to the mode that above-mentioned various devices carry out addressing.As shown in Figure 1, core component is by bus and UART parts, I ²Each external components such as C bus parts and SPI parts link to each other, and by the bus addressing mode external components are carried out addressing.

The defective of prior art is: adopt the bus addressing mode, when a plurality of external components just are easy to generate bus collision during simultaneously to bus transfer data.For example, when two interrupt instructions arrive simultaneously, prior art can only adopt artificial setting successively smoothly mode transmit interrupt instruction respectively.But this mode has increased the difficulty of design.

The utility model content

Problem to be solved in the utility model is: existing microcontroller is easy to generate bus collision at the bus addressing mode that external components adopts.

For achieving the above object, the utility model provides a kind of microcontroller, comprises core component, wherein also comprises:

Communications Interface Assembly links to each other with described core component, is used for sending communication gating signal and unified state machine signal according to the steering order that comes from described core component;

External components links to each other with described Communications Interface Assembly, is used for according to the described unified state machine signal that comes from Communications Interface Assembly, sends or receive data-signal and address signal;

First MUX links to each other with address wire with the data line of described core component, is used for according to the described communication gating signal that comes from Communications Interface Assembly, and the data-signal and the address signal that will come from described core component send to described external components;

Second MUX links to each other with address wire with the data line of described external components, is used for according to the described communication gating signal that comes from Communications Interface Assembly, and the data-signal and the address signal that will come from external components send to described core component.

By the described microcontroller of present embodiment, owing to adopted Communications Interface Assembly that the communication of each external components is coordinated, therefore, the bus collision that produces in the time of can avoiding adopting the bus addressing mode has improved the reliability and the overall performance of microcontroller.

Description of drawings

Fig. 1 is the structural representation of existing microcontroller;

Fig. 2 is the structural representation of the utility model embodiment 1 described microcontroller;

Fig. 3 is the structural representation of the utility model embodiment 2 described microcontrollers.

Below by drawings and Examples, the technical solution of the utility model is described in further detail.

Embodiment

Embodiment 1

Present embodiment provides a kind of microcontroller, as shown in Figure 2, comprises core component 10, Communications Interface Assembly 20, external components 40, first MUX 31 and second MUX 32.

Particularly, Communications Interface Assembly 20 links to each other with core component 10, is used for sending the communication gating signal according to the steering order that comes from core component 10 to first MUX 31 or second MUX 32, and sends unified state machine signal to external components 40.

Wherein, external components 40 can be UART parts, I ²Various existing external components such as C bus parts or SPI parts.Steering order is that core component 10 is sent according to the waiting status of external components 40, when a plurality of external components 40 will be to core component 10 simultaneously during transmitt or receive signal, core component 10 can steering order be coordinated it, to allow the signal transmission of one of them external components 40.

External components 40 is used for according to the unified state machine signal that comes from Communications Interface Assembly 20, sends or receive data-signal and address signal.Wherein, unified state machine signal is the control signal that Communications Interface Assembly 20 sends to external components 40 according to the steering order of core component 10, whether can carry out the transmission of signal with notice external components 40.

First MUX 31 links to each other with address wire with the data line of core component 10, be used for according to the communication gating signal that comes from Communications Interface Assembly 20, the data-signal and the address signal that will come from core component 10 send to corresponding external components 40, make core component 10 data-signal and address signal can be sent to external components 40; Second MUX 32 links to each other with address wire with the data line of external components 40, be used for according to the communication gating signal that comes from Communications Interface Assembly 20, the data-signal and the address signal that will come from external components 40 send to core component 10, make external components 40 data-signal and address signal can be sent to core component 10.

Embodiment 2

Present embodiment provides another kind of microcontroller, as shown in Figure 3, also further comprises on the basis of microcontroller shown in the embodiment 1: memory interface parts 70, the 3rd MUX 50, data-carrier store 61 and program storage 62.Particularly, memory interface parts 70 link to each other with core component 10, and when core component 10 will be when data-carrier store 61 or program storage 62 read information, its course of work is as follows:

Core component 10 sends data address or the program address that will carry out addressing to memory interface parts 70; Data address or program address that memory interface parts 70 will come from core component 10 are converted to unified address, and send memory strobe signals.Wherein, data address is meant that core component 10 wants the data message of addressing to be arranged in the address of data-carrier store 62, and the program address is meant that core component 10 wants the program information of addressing to be arranged in the address of program storage 61.In the prior art, data address and program address are not based on that corresponding memory works out respectively, and be between these two kinds of addresses directly related.And by after the conversion of memory interface parts 70, data address and program address are converted into unified address, be about to data-carrier store 62 and program storage 61 and carry out addressing as an independent storer, in this independent storer, different data messages or address information all have unique unified address.

Particularly, the conversion regime of unifying the address can adopt the mode that increases side-play amount to carry out.For example, a data address is 0011H, and a program address also is 0011H.Unified for the two is carried out, can be with a kind of address wherein, become 0111H after supposing the program address added a side-play amount 0100H.Make when carrying out addressing, do not have identical address.The size of side-play amount can be carried out respective settings according to the capacity of storer.

The 3rd MUX 50 will be sent to data-carrier store 62 or program storage 61 by the unified address that memory interface parts 70 convert to according to the memory strobe signals that comes from memory interface parts 70; Data-carrier store 62 or program storage 61 search corresponding data information or program information, and the corresponding information that will find send to core component 10 according to the unified address that comes from the 3rd MUX 50.

By the described microcontroller of present embodiment, because data-carrier store and program storage data address and program address have separately been carried out unified organizational system, become unified address, be about to storage space and carried out linearization, therefore simplify the addressing process of storer, and also reduced the complexity of address bus.

Need to prove that in addition for the ease of drawing, Fig. 3 has only shown present embodiment and other part-structure of embodiment 1 phase region, other parts that do not show are identical with embodiment 1, repeat no more herein.

It should be noted last that, above embodiment is only unrestricted in order to the explanation the technical solution of the utility model, although the utility model is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement the technical solution of the utility model, and not break away from the spirit and scope of technical solutions of the utility model.

Claims

1, a kind of microcontroller comprises core component, it is characterized in that also comprising:

2, microcontroller according to claim 1 is characterized in that also comprising:

The memory interface parts link to each other with described core component, and the data address and the program address that are used for coming from described core component are converted to unified address, and send read strobe signal;

The 3rd MUX links to each other with described memory interface parts, is used for will sending to data-carrier store and program storage by the unified address that the memory interface parts convert to according to the read strobe signal that comes from described memory interface parts;

Data-carrier store links to each other with described the 3rd MUX, is used for searching corresponding data information and sending to described core component according to the unified address that comes from described the 3rd MUX;

Program storage links to each other with described the 3rd MUX, is used for searching corresponding program information and sending to described core component according to the unified address that comes from described the 3rd MUX.