CN200972500Y - Integral automatic integrated tester - Google Patents
Integral automatic integrated tester Download PDFInfo
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- CN200972500Y CN200972500Y CN 200620140566 CN200620140566U CN200972500Y CN 200972500 Y CN200972500 Y CN 200972500Y CN 200620140566 CN200620140566 CN 200620140566 CN 200620140566 U CN200620140566 U CN 200620140566U CN 200972500 Y CN200972500 Y CN 200972500Y
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- 238000012360 testing method Methods 0.000 claims abstract description 75
- 238000013500 data storage Methods 0.000 claims abstract description 22
- 230000004044 response Effects 0.000 claims abstract description 21
- 238000004891 communication Methods 0.000 claims abstract description 17
- 210000000352 storage cell Anatomy 0.000 claims description 18
- 230000010354 integration Effects 0.000 claims description 12
- 238000005070 sampling Methods 0.000 claims description 11
- 238000012545 processing Methods 0.000 claims description 6
- 238000005259 measurement Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 7
- 230000005284 excitation Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
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- 230000005540 biological transmission Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 238000005086 pumping Methods 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
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Abstract
The utility model relates to an integrated automatic integration-testing instrument comprising a testing signal generating unit, a main control unit for hard logic gate, an acquisition unit for the response signal of the tested subject, a data storage unit, a data communications unit, and a sensor. The testing signal generating unit, comprises a DSP digital processor, and a D/A converter; the testing signal generating unit is connected with the main control unit for hard logic gate, the acquisition unit for the response signal of the tested subject, the data storage unit and the main control unit for hard logic gate. The sensor is connected with the acquisition unit for the response signal of the tested subject and data storage unit, and the main control unit for hard logic gate is connected with the data communications unit. The utility model features in high measurement precision, low cost and a reduced number of external connection wires. The device is easy to use and the testing system features in excellent reliability and high reliability.
Description
Technical field
The utility model relates to the test macro field, relates in particular to integrated automatic integration testing instrument.
Background technology
Test macro is widely used in the every field of national economy and national defense construction, is one of indispensable technical equipment of research and production.Traditional test macro mainly is made up of three parts: test signal generation device, tested object, the collection of tested object response signal and treating apparatus.In the legacy test system, the collection of the generation of test and excitation signal, tested object response signal is finished by two instruments respectively with handling, and time synchronized, collaborative work between two instruments become the technical barrier that influences measuring accuracy, system's ease for use, cost etc.
The signals collecting of test macro and processing unit can be further divided into two parts usually: test macro is only finished signals collecting and pre-service; The aftertreatment of acquired signal, storage, analysis, man-machine interface etc. are then realized by host computer (mostly being PC greatly).This also is the international mainstream technology of present test macro.Therefore, test macro needs to communicate by letter with host computer by certain communication protocol.Engineering practice shows, has certain bit error rate under the bad working environments or during the big data quantity transmission, thereby causes test crash; Simultaneously, must dispose PC during the test macro operation, under vibrations and strong electromagnetic condition, commercial PC can not guarantee stable operation.
The main control unit of existing test macro generally realized by general purpose microprocessors such as single-chip microcomputers, the operation of the software control test macro by microprocessor, and there is the possibility of program fleet in software; Though employing Watch dog settlement procedure to a certain extent runs the problem that flies, the confidence level of measuring accuracy and test result certainly will be affected.
Summary of the invention
The purpose of this utility model provides integrated automatic integration testing instrument, overcomes three big defectives of existing test macro.
Integrated automatic integration testing instrument comprises test signal generating unit, hard logic door main control unit, the collecting unit of tested object response signal, data storage cell, data communication units, sensor, and the test signal generating unit comprises DSP digital processing unit, D/A converter; The collecting unit of test signal generating unit and hard logic door main control unit, tested object response signal, data storage cell, hard logic door main control unit join, collecting unit, the data storage cell of sensor and tested object response signal join, and hard logic door main control unit and data communication units are joined.
The circuit of described hard logic door main control unit is: microprocessor joins with DSP First Input First Output unit, A/D sampling controller, D/A First Input First Output unit, A/D First Input First Output unit respectively; D/A controller and D/A First Input First Output unit join.Collecting unit adopts the AD785 chip, has 4 A/D passages, maximum sample frequency 300Ksps.Data storage cell adopts the K9WAG08U1M chip.Data communication units adopts the EZ-USBFX2 chip.
The utility model organically is integrated in signal generation, signals collecting and processing on the instrument, efficiently solve between the testing tool that existing test macro exists time synchronized, collaborative work, system's aerial lug too much, technical barrier such as ease for use difference.
Upload the error code that image data may occur at test macro, set up the mass data storage unit; Tested object response signal data not only is uploaded to host computer, and deposits the data storage cell of integral automatic integrating testing system in.In case when host computer finds that the image data of uploading is wrong like this, can read in image data from data storage cell and remedy.On the other hand, integral automatic integrating testing system both can with online test of host computer (PC); Also can with the independent test of host computer off line, carry out data analysis with host computer is online again after the end of test (EOT).Therefore, the introducing of data storage cell has brought the benefit of the multiple method of operation to the user; Especially be under vibrations, the strong electromagnetic operating mode, when commercial PC can not guarantee stable operation, the advantage of integral automatic integrating testing system independent operation mode was particularly evident.
At test macro under bad working environments, the phenomenon that microprocessor software exists race to fly adopts FPGA to use Verilog HDL hardware description language and is configured, and promptly the hard logic door is controlled whole testing process, the software of stopping to occur runs and flies phenomenon, promotes the reliability and stability of test.
Description of drawings
Below in conjunction with accompanying drawing the utility model is described further
Fig. 1 is integrated automatic integration testing instrument circuit block diagram;
Fig. 2 is FPGA hard logic door main control unit configuration module figure of the present utility model;
Fig. 3 (a) is an A/D sampling reading state machine of the present utility model;
Fig. 3 (b) is that sequential chart is read in A/D sampling of the present utility model;
Fig. 4 (a) is EZ-USBFX2 of the present utility model and FPGA connection layout;
Fig. 4 (b) is the firmware program block diagram of EZ-USBFX2 of the present utility model.
Embodiment
Below in conjunction with accompanying drawing concrete enforcement of the present utility model is explained in detail.
As shown in Figure 1, integrated automatic integration testing instrument comprises test signal generating unit 1, hard logic door main control unit 2, the collecting unit 3 of tested object response signal, data storage cell 4, data communication units 5, sensor 6, and test signal generating unit 1 comprises DSP digital processing unit, D/A converter; The collecting unit of test signal generating unit and hard logic door main control unit, tested object response signal, data storage cell, hard logic door main control unit join, collecting unit, the data storage cell of sensor and tested object response signal join, and hard logic door main control unit and data communication units are joined.
Collecting unit 3 adopts the AD785 chip, has 4 A/D passages, maximum sample frequency 300Ksps.Collecting unit is used the finite state machine design, under AD sampling controller module 25 controls of hard logic door main control unit, finishes the collection of tested object response signal.Data storage cell 4 adopts the K9WAG08U1M chip, capacity 2G, and the tested object response signal data of data acquisition unit collection is uploaded to host computer on the one hand, deposits data storage cell simultaneously in.The introducing of data storage cell makes the use-pattern variation of integral automatic integrating testing system, has improved the reliability of system simultaneously.Data communication units 5 adopts the EZ-USBFX2 chip, and hard logic door main control unit is as the primary controller of integral automatic integrating testing system, and data communication units then is in slave status, so usb mode is the slave First Input First Output.Integral automatic integrating testing system is communicated by letter with host computer through communication unit; Testing process parameter that host computer is downloaded and initialization information are confirmed by host computer by hard logic door main control unit passback host computer; The tested object response signal data of integral automatic integrating testing system collection is uploaded to host computer, handles for upper computer analyzing software (Matlab, Labview etc.).
Integrated automatic integration testing instrument is realized functions such as the collection of pumping signal, response signal of test macro and control, Signal Processing, result's expression and output on the separate unit instrument.
Described test signal generating unit 1 is made up of fixed point 16 bit DSP chip TMS320VC5509A (11) and DAC904D/A conversion chip 12.Hard logic door main control unit receives the testing process instruction of host computer through data communication units, and is transmitted to DSP; DSP generates test signal Wave data (sine, triangle, square wave, sawtooth, linear frequency sweep, white noise, the pseudorandom etc.) signal of assigned frequency and amplitude according to the testing process instruction, export D/A First Input First Output module 24 buffer memorys of FPGA inside to, export measurand to through D/A conversion chip DAC904 again; Introduce the data test signal buffer module, make the calculating of DSP can independent operating, the output of test and excitation signal be more stable.Wherein the test waveform data are generated by host computer arbitrarily, and directly from DAC904 output, the output resolution ratio of test signal generating unit is 12bit through hard logic door main control unit, and maximum rate is 300Ksps.In view of DSP generates the D/A slewing rate of the speed of test data much larger than DAC904, therefore, the process that DSP generates test data adopts 32 precision, only is converted into 16 when exporting DAC904 to, thereby the precision of test macro pumping signal is significantly improved.
As shown in Figure 2, the circuit of hard logic door main control unit 2 is: microprocessor 21 joins with DSP First Input First Output unit 22, A/D sampling controller 25, D/A First Input First Output unit 24, A/D First Input First Output unit 26 respectively; D/A controller 23 joins with D/A First Input First Output unit 24.
Hard logic door main control unit adopts fpga chip EPIC3T144C8.FPGA controls whole testing process, and control communication unit 5 is communicated by letter with host computer; According to the configuration information that host computer is downloaded, finish system initialization, control figure processor 11 generates various test and excitation signal waveform datas, or directly controls any test and excitation signal waveform data that DAC904 converter 12 output host computers generate; Hard logic door main control unit is controlled collecting unit 3 simultaneously, the response signal of collecting test object, and sampled signal is uploaded to host computer through communication unit 5, and stores data storage cell 4 into.Hard logic door main control unit adopts the design of Verilog HDL hardware description language, and fpga chip EPIC3T144C8 is configured to MCU microprocessor 21, DSP First Input First Output unit 22, D/A controller 23, D/A First Input First Output unit 24, A/ D sampling controller 25,26 6 modules in A/D First Input First Output unit.
Fig. 3 (a) is an A/D sampling reading state machine, and Fig. 3 (b) is that sequential chart is read in the A/D sampling.In Fig. 3 (a), S1 and S2 state all do not have signal output, and just prepare for reading of data.When state machine enters into the S3 state, show that AD sampling finishes, at this moment just can export RD and CS signal, read sampled signal successively.The data that read are written directly in the First Input First Output of synchronous high-speed, data are sent to the slave First Input First Output of USB when First Input First Output is half-full or full up.The working timing figure of response is shown in Fig. 3 (b).
Fig. 4 (a) is EZ-USBFX2 and FPGA connection layout.Because FPGA is as the primary controller of system, USB is in slave status, so usb mode adopts the slave First Input First Output, wherein interface clock IFCLK is set to inside clock signal 48MHZ is provided, and also is the work clock of FPGA simultaneously.FLAGA, FLAGB and FLAGC represent the level state able to programme of indication passage, full state and dummy status respectively.
Fig. 4 (b) is the firmware program block diagram of EZ-USBFX2.The developing instrument of USB driver has C compiler and Windows DDK.Here drive the overall process that the device driver exploitation is finished in the kit guiding by DriverWorks, generate the device driver source code automatically.The slave First Input First Output of USB adopts synchronous read-write mode, realizes by finite state machine, and wherein IDLE and S1-S4 are respectively read-write state.It is as follows that its part is write sequential state machine Verilog HDL program:
Case (state) IDLE: // idle condition state＜=S1; S1: // begin to transmit First Input First Output ADR[1:0]＜=2'b11; // sensing transmission channel state＜=S2; S2: // First Input First Output state is judged if (FULL==1'b1) state＜=S3; // First Input First Output is less than then writing else state＜=S2; // wait for
S3: // write data SLWR＜=1'b0; State＜=S4; S4: // judge whether to also have data if (DATAFLAG==1'b1) state＜=S2; // data else state＜=IDLE arranged; // stop
Claims (5)
1. integrated automatic integration testing instrument, it is characterized in that, it comprises collecting unit (3), data storage cell (4), data communication units (5), the sensor (6) of test signal generating unit (1), hard logic door main control unit (2), tested object response signal, and test signal generating unit (1) comprises DSP digital processing unit, D/A converter; The collecting unit of test signal generating unit and hard logic door main control unit, tested object response signal, data storage cell, hard logic door main control unit join, collecting unit, the data storage cell of sensor and tested object response signal join, and hard logic door main control unit and data communication units are joined.
2. a kind of integrated automatic integration testing instrument according to claim 1, it is characterized in that the circuit of described hard logic door main control unit (2) is: it comprises microprocessor (21), DSP First Input First Output unit (22), D/A controller (23), D/A First Input First Output unit (24), A/D sampling controller (25), A/D First Input First Output unit (26); Microprocessor joins with DSP First Input First Output unit, A/D sampling controller, D/A First Input First Output unit, A/D First Input First Output unit respectively; D/A controller and D/A First Input First Output unit join.
3. a kind of integrated automatic integration testing instrument according to claim 1 is characterized in that, described collecting unit (3) adopts the AD785 chip, has 4 A/D passages, maximum sample frequency 300Ksps.
4. a kind of integrated automatic integration testing instrument according to claim 1 is characterized in that, described data storage cell (4) adopts the K9WAG08U1M chip.
5. a kind of integrated automatic integration testing instrument according to claim 1 is characterized in that, described data communication units (5) adopts the EZ-USBFX2 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620140566 CN200972500Y (en) | 2006-11-30 | 2006-11-30 | Integral automatic integrated tester |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620140566 CN200972500Y (en) | 2006-11-30 | 2006-11-30 | Integral automatic integrated tester |
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| CN200972500Y true CN200972500Y (en) | 2007-11-07 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100423039C (en) * | 2006-11-30 | 2008-10-01 | 浙江大学 | Integral automatic integrating testing system |
| CN103837824A (en) * | 2014-03-03 | 2014-06-04 | 中国科学院电子学研究所 | Automatic test system for digital integrated circuit |
| CN105487522A (en) * | 2015-11-24 | 2016-04-13 | 昆山凯捷特电子研发科技有限公司 | Test system and method of gate control system |
| CN113608092A (en) * | 2021-06-28 | 2021-11-05 | 臻驱科技（上海）有限公司 | Double-pulse test system |
-
2006
- 2006-11-30 CN CN 200620140566 patent/CN200972500Y/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100423039C (en) * | 2006-11-30 | 2008-10-01 | 浙江大学 | Integral automatic integrating testing system |
| CN103837824A (en) * | 2014-03-03 | 2014-06-04 | 中国科学院电子学研究所 | Automatic test system for digital integrated circuit |
| CN103837824B (en) * | 2014-03-03 | 2016-08-17 | 中国科学院电子学研究所 | Digital integrated electronic circuit Auto-Test System |
| CN105487522A (en) * | 2015-11-24 | 2016-04-13 | 昆山凯捷特电子研发科技有限公司 | Test system and method of gate control system |
| CN113608092A (en) * | 2021-06-28 | 2021-11-05 | 臻驱科技（上海）有限公司 | Double-pulse test system |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20081001 |
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| C25 | Abandonment of patent right or utility model to avoid double patenting |