CN206741275U - High-speed data acquiring device based on FPGA - Google Patents

Abstract

The utility model discloses a kind of high-speed data acquiring device based on FPGA, including fpga chip, AD conversion chip, SDRAM chips and host computer；The fpga chip is connected with AD conversion chip, SDRAM chips and host computer respectively；The fpga chip receives the control signal of host computer, from AD conversion chip gathered data and stores to SDRAM chips, and by the data feedback stored in SDRAM chips to host computer；The clock signal of the fpga chip output AD conversion chip and SDRAM chips.The fpga chip that the utility model uses plays " bridge " effect in whole harvester, AD samplings and SDRAM storages and single-chip microcomputer these devices are connected co-ordination, can solve the problems, such as directly use single-chip microcomputer control existing for speed is slow, internal memory is small and causes mass data to send not in time with data receiver without local caching.

Description

High-speed data acquiring device based on FPGA

Technical field

A kind of high-speed data acquiring device based on FPGA is the utility model is related to, for higher, complete to acquisition rate The higher high-speed data acquisition of degree requirement and the occasion of processing.

Background technology

Traditional data acquisition is typically using single-chip microcomputer or DSP as control unit come the work of Control peripheral circuit. The small volume of single-chip microcomputer, it is cheap, using also very extensively, but its real-time is poor, the sampling speed that can reach Degree also has great limitation, is typically employed in real-time and the less demanding occasion of sampling rate.For DSP, at data It is very strong to manage function, the gathered data of high-speed can also be reached, but carrys out Control peripheral circuit as CPU with DSP, is controlling In terms of complicated logical device there is also it is very big the defects of.

Utility model content

Goal of the invention：In view of the shortcomings of the prior art, the utility model provides a kind of high-speed data acquisition based on FPGA Device, using FPGA as high-speed data acquisition control unit, solves the difficult point that acquisition rate is high, data volume is big.

Technical scheme：To achieve the above object, the utility model adopts the following technical scheme that：

High-speed data acquiring device based on FPGA, including fpga chip, AD conversion chip, SDRAM chips and host computer； The fpga chip is connected with AD conversion chip, SDRAM chips and host computer respectively；The fpga chip receives host computer Control signal, from AD conversion chip gathered data and store to SDRAM chips, and the data that will be stored in SDRAM chips Feed back to host computer；The clock signal of the fpga chip output AD conversion chip and SDRAM chips；The fpga chip uses The Enable Pin of 1 I/O mouth and AD conversion chip connects, and is connected with 8 I/O mouths and the FPDP of AD conversion chip；It is described Fpga chip connects with 13 I/O mouths and SDRAM address wire, is connected with two I/O mouths with SDRAM sections, with 4 I/O mouths and SDRAM CS, RAS, CAS and WE connections, connected with 8 I/O mouths and SDRAM FPDP；Fpga chip It is connected by serial port chip with host computer.

Preferably, it is provided with controllable frequency division module, AD control modules and SDRAM control modules in the fpga chip；Institute The clock signal of system that the input of controllable frequency division module has source crystal oscillator to provide is stated, output supplies AD control modules and SDRAM control modules First clock signal CLOCK1 of work, second clock signal CLOCK2 of the output for SDRAM chip operations；The AD controls mould Block communicates with AD conversion chip data, and the SDRAM control modules communicate with SDRAM chip datas.

Preferably, being additionally provided with the first FIFO cachings and the 2nd FIFO cachings in the fpga chip, it is used separately as reading SDRAM and the data buffer zone for writing SDRAM.

In specific embodiments, the fpga chip is EP4CE6E22C8N, and the AD conversion chip is AD9283； The controllable frequency division module inputs 50MHz clock signals, output 100kHz displacements be -210 ° of the first clock signal CLOCK1 extremely AD control modules and SDRAM control modules, the second clock signal CLOCK2 that output 100kHz displacements are 0 ° to SDRAM chips； The AD control modules communicate with AD conversion chip data, and the SDRAM control modules communicate with SDRAM chip datas.

Beneficial effect：The fpga chip that the utility model uses plays " bridge " effect in whole harvester.One side Face produces the clock required for AD work, and sampled value is obtained from AD；On the other hand FIFO cachings are opened up sampled data is quick Continuously latch into SDRAM, while can also realize and be communicated with the single-chip microcomputer SPI of host computer.According to wanting for host computer single-chip microcomputer Realistic existing sampling starts, the functions such as the data stored in SDRAM is transmitted to single-chip microcomputer.FPGA AD sample and SDRAM storage with And single-chip microcomputer these devices connect co-ordination, can solve directly to use single-chip microcomputer control existing for speed it is slow, interior Deposit small and cause mass data to send the problem of being cached not in time with data receiver without place.Compared with prior art, this dress The sampling that can be realized to high-speed data is put, and is capable of the mass data of accurate accurately storage collection.The utility model has following Advantage：1) sample frequency is high, and speed is fast, can accurately preserve the mass data of collection.2) by the way of FPGA controls SDRAM Mass data is accurately stored.

Brief description of the drawings

Fig. 1 is the structural representation of the utility model embodiment.

Fig. 2 is the core component hardware elementary diagram of the utility model embodiment.

Fig. 3 is the test result figure of the utility model embodiment.Wherein (a) is 100KHz sine wave, and (b) is 100KHz Triangular wave, (c) be 100KHz square wave.

Embodiment

The technical solution of the utility model is further described below in conjunction with accompanying drawing：

Such as Fig. 1, a kind of high-speed data acquiring device based on FPGA disclosed in the utility model embodiment, mainly include Fpga chip, AD conversion chip, SDRAM chips and host computer.Fpga chip be harvester controller, respectively with AD conversion Chip, SDRAM chips and host computer are connected, and receive the control signal of host computer, from AD conversion chip gathered data and deposit Storage is to SDRAM chips, and by the data feedback stored in SDRAM chips to host computer.Fpga chip exports AD conversion chip With the clock signal of SDRAM chips, the control sequential required for speed A/D converter and the work of Large Copacity SDRAM memory is produced Signal, controlling of sampling is carried out to high-speed a/d conversion chip AD9283 of the acquisition rate up to 100MHz, delayed by opening up FIFO1 Deposit, mass data Fast Persistence is latched into Large Copacity SDRAM memory and to the caching by FIFO2 by SDRAM In data exported from serial ports to host computer.

Below with fpga chip EP4CE6E22C8N, AD conversion chip AD9283, SDRAM storage chip MT48LC32M82A Exemplified by, describe the concrete structure and principle of the present embodiment in detail.

As shown in Fig. 2 No. 98 I/O mouths connection AD9283 of EP4CE6E22C8N utilization Enable Pin, with as shown in Figure 2 Remaining I/O connection AD9283 data segment, and EP4CE6E22C8N connects SDRAM address wires A0 with 13 I/O mouths and arrived A12, SDRAM Bank is connected with two I/O mouths, with 4 I/O mouths and SDRAM CS, RAS, CAS and WE connections, most Connected afterwards with 8 I/O mouths and SDRAM FPDP.EP4CE6E22C8N passes through serial port chip (such as CH340) and host computer Connect (not illustrating in figure), the TX ports of FPGA RX ports and serial port chip connect, FPGA TX ports and serial port chip RX connections, complete the connection with host computer.

Controllable frequency division module, AD control modules and SDRAM control modules are provided with fpga chip EP4CE6E22C8N.Wherein Controllable frequency division module PLL is that system clock has source crystal oscillator using 50MHz, after chip EP4CE6E22C8N is input to, by compiling The CLOCK2 that journey frequency dividing is 0 ° into CLOCK1 the and 100kHz displacements that 100kHz displacements are -210 °.SDRAM basic modules and The clock signal of AD9283 working state control modules is provided by CLOCK1, and the clock signal of SDRAM chips is provided by CLOCK2.

AD control modules are controls of the FPGA to AD9283 working conditions, can be operated according to the service manual of A/D chip, AD9283 is mainly configured by 8 registers in the piece to it, and the setting to each register will be by posting communication The write operation of storage starts.AD9283 control modules need 100MHz clock signal CLOCK and clock signal ten divide AD_CLK clock signals.When the AD_EN signals of AD9283 control modules are high level and AD_CLK clock signals are also high level When, AD9283 control modules start gathered data, and data are placed in the memory block that AD9283 is carried.Deng 8Bit data acquisitions After complete, when waiting CLOCK next rising edge, while AD_RD signals are high level, and the data of collection are sent.

SDRAM control modules are operational controls of the FPGA to storage chip MT48LC32M82A, in order to be stored in Mass data caused by sampling period high speed, the first FIFO caching FIFO1 and the 2nd FIFO cachings are opened inside FPGA FIFO2, as the data buffer zone read SDRAM with write SDRAM.It is temporary during SDRAM that wherein FIFO1 is that data are read in After area, i.e. AD9283 control modules complete AD data acquisition, the data of collection are placed in FIFO1, wait FIFO1 to adopt full During 512 data, SDRAM control module can happen suddenly a line write operation to SDRAM functional modules, so that it may deposit the data of collection Storage is in SDRAM.After having stored data Deng SDRAM, SDRAM control modules can happen suddenly a line read operation to SDRAM functional modules, Digital independent in SDRAM is come out, and the caching by the data of reading by FIFO2, then exported by serial ports, so as to complete The collection of high-speed data.

In order to verify the feasibility of the utility model device and beneficial effect, make following test.Such as Fig. 3, with DG1022U It is 1V that signal generator produces Vpp respectively, and frequency is 100KHz sine wave, triangular wave and square wave.Signal is connected to this implementation The high-speed data acquiring device of example, the sampling rate of data sampling device is for 100MHz.Read by a PC by FIFO2 The data gone out in SDRAM, exported using FPGA serial port chip CH340 and receive data in COM Debug Assistant XCOM V2.0. The data application turboc2 that serial ports receives is converted into decimal number, finally with Origin mapping softwares by the number of preservation According to being drawn.In Origin, using the time as transverse axis, amplitude is that the longitudinal axis draws 100kHz sine waves, triangular wave and square wave.Root Understood according to test result, the device can complete the collection of high-speed data and complete storage.

FPGA is applied in data acquisition technology by the utility model, is successfully solved directly using under single-chip microcomputer control Control signal sequential speed is slow and because memory read-write speed is not enough and the problem of mass data is had little time to send and is stored. System has the advantages that flexibility is strong, general-purpose capability is good, is easy to develop, extends, be modernize high-speed data acquisition development must Right trend.

Claims (4)

1. the high-speed data acquiring device based on FPGA, it is characterised in that including fpga chip, AD conversion chip, SDRAM chips And host computer；The fpga chip is connected with AD conversion chip, SDRAM chips and host computer respectively；The fpga chip The control signal of host computer is received, from AD conversion chip gathered data and is stored to SDRAM chips, and by institute in SDRAM chips The data feedback of storage is to host computer；The clock signal of the fpga chip output AD conversion chip and SDRAM chips；It is described Fpga chip connects with the Enable Pin of 1 I/O mouth and AD conversion chip, with 8 I/O mouths and the data terminal of AD conversion chip Mouth connection；The fpga chip connects with 13 I/O mouths and SDRAM address wire, with two I/O mouths and SDRAM sections Connection, with 4 I/O mouths and SDRAM CS, RAS, CAS and WE connections, with 8 I/O mouths and SDRAM FPDP Connection；Fpga chip is connected by serial port chip with host computer.

2. the high-speed data acquiring device according to claim 1 based on FPGA, it is characterised in that in the fpga chip Provided with controllable frequency division module, AD control modules and SDRAM control modules；The controllable frequency division module input has what source crystal oscillator provided Clock signal of system, the first clock signal CLOCK1 that output works for AD control modules and SDRAM control modules, output supply The second clock signal CLOCK2 of SDRAM chip operations；The AD control modules communicate with AD conversion chip data, described SDRAM control modules communicate with SDRAM chip datas.

3. the high-speed data acquiring device according to claim 2 based on FPGA, it is characterised in that in the fpga chip The first FIFO cachings and the 2nd FIFO cachings are additionally provided with, is used separately as reading SDRAM and writes SDRAM data buffer zone.

4. the high-speed data acquiring device according to claim 2 based on FPGA, it is characterised in that the fpga chip is EP4CE6E22C8N, the AD conversion chip are AD9283；The controllable frequency division module inputs 50MHz clock signals, output The first clock signal CLOCK1 that 100kHz displacements are -210 ° exports 100kHz positions to AD control modules and SDRAM control modules The second clock signal CLOCK2 for 0 ° is moved to SDRAM chips；The AD control modules communicate with AD conversion chip data, described SDRAM control modules communicate with SDRAM chip datas.