CN109656862A - A kind of USB2.0 protocol analyzer and analysis method based on FPGA - Google Patents
A kind of USB2.0 protocol analyzer and analysis method based on FPGA Download PDFInfo
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- CN109656862A CN109656862A CN201811384650.5A CN201811384650A CN109656862A CN 109656862 A CN109656862 A CN 109656862A CN 201811384650 A CN201811384650 A CN 201811384650A CN 109656862 A CN109656862 A CN 109656862A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The present invention provides a kind of USB2.0 protocol analyzer and analysis method based on FPGA, and differential signal sampling input module is used to acquire the data that equipment under test transmits on USB2.0 differential bus in normal operating conditions；Logic control device is enumerated for realizing USB2.0 protocol analyzer, reads sampled result from sampling front-end, is uploaded to monitoring host computer by host interface as unit of the usb data packet for presetting size by data buffering to data storage, and by sampled data.Real-time sampling and analysis can be carried out to high speed and full speed USB device differential data bus Low Voltage Differential Signal, sampling dead-time problem is overcome using the concurrent processing characteristic of hardware, data accumulation and packet loss caused by solving the problems, such as because of different USB interfaces transmission phase difference, reduce the requirement to primary processor performance, design cost is reduced, provides a kind of effectively support for USB system exploitation and test.
Description
Technical field
The present invention relates to computer hardware fields, be specifically related to a kind of USB2.0 protocol analyzer based on FPGA and
Analysis method.
Background technique
For general-purpose serial bus USB (Universal Serial Bus) because of its versatility, high-speed type and plug and play etc. are special
Property, become the data transmission interface that computer peripheral equipment generallys use, however, since usb bus uses nrzi encoding format and nothing
The synchronous differential data transmission mode of clock, bus activity content is higher to user's transparency, in addition usb protocol itself
Complexity is opened so that usb host controller, USB device, USB firmware program and USB device driver development are very difficult
The hair period is generally longer, on the other hand, as usb bus becomes the data transmission interface of mainstream, the test and maintenance of USB device
Problem also becomes increasingly conspicuous, and the logic analyser or protocol analyzer class equipment price currently used for USB device test are generally held high
Expensive, part instrument has serious sampling dead zone, it is difficult to meet the application demand of developer.
Summary of the invention
In order to overcome the deficiencies in the prior art described above, the present invention provides a kind of USB2.0 protocal analysis based on FPGA
Instrument, comprising: differential signal samples input module, logic control device, host interface and data storage；
Differential signal sampling input module and data storage are connect with logic control device respectively；
Differential signal sampling input module transmits on USB2.0 differential bus in normal operating conditions for acquiring equipment under test
Data；
Logic control device is enumerated for realizing USB2.0 protocol analyzer, sampled result is read from sampling front-end, by data
It is buffered to data storage, and sampled data is uploaded to prison by host interface as unit of the usb data packet for presetting size
Control host.
Preferably, logic control device includes: FPGA main controller module, control fifo module and control interface；
Control fifo module is connect with FPGA main controller module；
FPGA main controller module is used to read the differential impedance data of acquisition from differential signal sampling input module, and will read
Differential impedance data buffering in data storage；Control fifo module configures FPGA main controller module to advanced elder generation
Mode out reads differential impedance data from data storage and is handled；Will treated data buffer storage in data storage
In, while by treated, data pass through host interface for differential impedance data from data storage in a manner of first in first out
It is transmitted to monitoring host computer.
Preferably, differential signal sampling input module uses non-intrusion type detection mode, acquires the difference on differential bus
Impedance；
The precision that the differential output impedance of the front end difference amplifier of differential signal sampling input module meets 90ohm ± 15% is wanted
It asks.
Preferably, differential signal sampling input module adopts differential impedance using high-speed-differential amplifier AD8352
Sample.
Preferably, logic control device further include: USB physical layer interface chip samples input module string in differential signal
After row sampling, select that serial differential signals are converted to byte wide by USB physical layer interface chip CY7C68000 and line number
According to.
Preferably, FPGA main controller module selects the CYCLONE Series FPGA chip EP1C12 of Altera；
Data storage is using the High speed asynchronous FIFO of Integrated Device Technology, Inc. as data buffer.
Preferably, the protocol layer of logic control device and firmware layer processing use the pure hardware based on FPGA and VHDL language
Circuit is realized.
A kind of usb protocol analysis method based on FPGA, method include:
Differential signal samples the differential impedance on input module acquisition differential bus；
Logic control device reads the differential impedance data of acquisition from differential signal sampling input module, and to differential impedance data
It is handled, differential impedance data is transmitted to by monitoring host computer by host interface after processing；Logic control device be also used to by
Differential impedance data storage is to data storage after the acquisition differential impedance data of reading and processing.
Preferably, FPGA main controller module reads the differential impedance data of acquisition from differential signal sampling input module,
And by the differential impedance data buffering of reading in data storage；Control fifo module configures FPGA main controller module to
Differential impedance data are read from data storage in a manner of first in first out to be handled；Will treated data buffer storage in number
According in memory, at the same in a manner of first in first out from data storage will treated data by host interface by difference
Impedance data is transmitted to monitoring host computer.
As can be seen from the above technical solutions, the invention has the following advantages that
The present invention can will be uploaded in the case where not influencing equipment under test and working normally after the activity description decoding on differential bus
It is analyzed to PC machine for upper level applications, it is asked using the detection that high-speed-differential amplifier solves high velocity, low pressure differential signal
Topic；It selects compatible USB2.0 agreement high speed and the analog transceiver of Full-Speed mode to realize the serioparallel exchange of data, improves system
Processing capacity；Sampling dead zone is effectively overcome with High speed asynchronous FIFO is extended out using the concurrent processing mechanism of programmable logic device
Problem, secondly protocol layer and firmware layer processing are realized using based on the pure hardware circuit of FPGA and VHDL language, are reduced to master
The requirement of processor performance, effectively reduces design cost.
Detailed description of the invention
In order to illustrate more clearly of technical solution of the present invention, attached drawing needed in description will be made below simple
Ground introduction, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ordinary skill
For personnel, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the USB2.0 protocol analyzer schematic diagram based on FPGA；
Fig. 2 is logic control device schematic diagram；
Fig. 3 is the usb protocol analysis method flow chart based on FPGA.
Specific embodiment
The present invention provides a kind of usb protocol analyzer based on FPGA, as depicted in figs. 1 and 2, comprising: differential signal is adopted
Sample input module 1, logic control device 2, host interface 3 and data storage 4；
Differential signal sampling input module 1 and data storage 4 are connect with logic control device 2 respectively；
Differential signal sampling input module 1 transmits on USB2.0 differential bus in normal operating conditions for acquiring equipment under test
Data；
Logic control device 2 is enumerated for realizing USB2.0 protocol analyzer, sampled result is read from sampling front-end, by data
It is buffered to data storage, and sampled data is uploaded to as unit of the usb data packet for presetting size by host interface 3
Monitoring host computer.
Technology as described herein may be implemented in hardware, software, firmware or any combination of them.The various spies
Sign is module, and unit or assembly may be implemented together in integration logic device or separately as discrete but interoperable logic
Device or other hardware devices.In some cases, the various features of electronic circuit may be implemented as one or more integrated
Circuit devcie, such as IC chip or chipset.
After the present invention can decode the activity description on differential bus in the case where not influencing equipment under test and working normally
It is uploaded to PC machine to analyze for upper level applications, it solves the detection of high velocity, low pressure differential signal using high-speed-differential amplifier
Problem；It selects compatible USB2.0 agreement high speed and the analog transceiver of Full-Speed mode to realize the serioparallel exchange of data, improves and be
System processing capacity；Sampling is effectively overcome extremely with High speed asynchronous FIFO is extended out using the concurrent processing mechanism of programmable logic device
Area's problem, secondly protocol layer and firmware layer processing are realized using based on the pure hardware circuit of FPGA and VHDL language, are reduced pair
The requirement of primary processor performance, effectively reduces design cost.
In the present invention, logic control device 2 includes: FPGA main controller module 11, control fifo module 12 and control
Interface 14 processed；
FPGA main controller module 11 is used to read the differential impedance data of acquisition from differential signal sampling input module 1, and will
The differential impedance data buffering of reading is in data storage 4；Control fifo module 12 configures FPGA main controller module 11
It is handled to read differential impedance data from data storage 4 in a manner of first in first out；It will treated data buffer storage
By treated, data pass through host interface from data storage 4 in data storage 4, while in a manner of first in first out
Differential impedance data are transmitted to monitoring host computer by 3.
If realized within hardware, the present invention relates to a kind of devices, such as can be used as processor or integrated circuit dress
It sets, such as IC chip or chipset.Alternatively or additionally, if realized in software or firmware, the technology can
Realize at least partly by computer-readable data storage medium, including instruction, when implemented, make processor execute one or
More above methods.For example, computer-readable data storage medium can store the instruction such as executed by processor.
The major function of FPGA main controller module control logic is to realize USB2.0 protocal analysis in logic control device
Instrument equipment is enumerated, and is read sampled result from sampling front-end, is buffered to data, and by sampled data as unit of USB packet
It is uploaded to monitoring host computer.Parallel processing capability, data throughput and the data buffer capacity of control logic are to influence equipment packet loss
The key factor of rate.
In the present invention, since USB system is more stringent to the differential signal quality requirement under high-speed mode, high speed USB
Equipment differential bus must keep the differential impedance of ± 15% precision of continuous 90ohm, the earth impedance of single differential signal line
It must be in ± 10% range of 45ohm.When earth impedance is accurately 45ohm, differential signal driving current is about 17.78m, poor
Sub-signal amplitude is ± 400mV.If differential impedance is discontinuous or precision does not reach requirement, usb bus differential signal it is complete
Whole property will be severely impacted.In conjunction with parameters such as PCB material and thickness, the line width and line of differential lines can be adjusted by calculating
Away to reach USB2.0 agreement to the exact requirements of differential impedance.
Sampling input module: test need to use non-intrusion type detection mode, it is desirable that the introducing of test equipment does not influence to be tested
The normal work of equipment, specific requirement are that test equipment cannot pull super-high-current from test point, otherwise will make to test source signal
Serious distortion.Therefore, the precision that the differential output impedance of front end difference amplifier should also meet 90ohm ± 15% in design is wanted
It asks.
In the present invention, USB2.0 protocol analyzer PCB is designed using 4 laminates, and differential signal samples input module and uses
High-speed-differential amplifier AD8352 samples differential impedance.
Logic control device further include: USB physical layer interface chip samples input module serial samples in differential signal
Afterwards, select USB physical layer interface chip CY7C68000 that serial differential signals are converted to the parallel data of byte wide.
The CYCLONE Series FPGA chip EP1C12 of FPGA main controller module selection Altera；Data storage uses
The High speed asynchronous FIFO of Integrated Device Technology, Inc. is as data buffer.Protocol layer and the firmware layer processing of logic control device, which use, to be based on
The pure hardware circuit of FPGA and VHDL language is realized.
The computer program product of computer-readable medium can form a part, may include packaging material.Data
Computer-readable medium may include computer storage medium, such as random access memory (RAM), read-only memory
(ROM), nonvolatile RAM (NVRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory, magnetic or
Optical data carrier and analog.In some embodiments, a kind of manufacture product may include that one or more computers can
Read storage media.
In the present invention also provides a kind of usb protocol analysis method based on FPGA, as shown in figure 3, method includes:
S1, differential signal sample the differential impedance on input module acquisition differential bus；
S2, logic control device read the differential impedance data of acquisition from differential signal sampling input module, and to differential impedance
Data are handled, and differential impedance data are transmitted to monitoring host computer by host interface after processing；Logic control device is also used
Differential impedance data storage is to data storage after the acquisition differential impedance data that will read and processing.
Method and device of the invention may be achieved in many ways.For example, can by software, hardware, firmware or
Person's software, hardware, firmware any combination realize method and device of the invention.The step of for the method it is above-mentioned
Sequence is merely to be illustrated, and the step of method of the invention is not limited to sequence described in detail above, unless with other sides
Formula illustrates.In addition, in some embodiments, the present invention can be also embodied as recording program in the recording medium, these
Program includes for realizing machine readable instructions according to the method for the present invention.Thus, the present invention also covers storage for executing
The recording medium of program according to the method for the present invention.
In the method, FPGA main controller module reads the differential impedance number of acquisition from differential signal sampling input module
According to, and by the differential impedance data buffering of reading in data storage；Control fifo module matches FPGA main controller module
It is set in a manner of first in first out and to read differential impedance data from data storage and handled；It will treated data buffer storage
By treated, data will by host interface from data storage in data storage, while in a manner of first in first out
Differential impedance data are transmitted to monitoring host computer.
Method can carry out real-time sampling to high speed and full speed USB device differential data bus Low Voltage Differential Signal and divide
Analysis, overcomes sampling dead-time problem using the concurrent processing characteristic of hardware, solves because different USB interfaces transmission phase difference causes
Data accumulation and packet loss problem, reduce the requirement to primary processor performance, reduce design cost, for USB system develop
A kind of effectively support is provided with test.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (9)
1. a kind of USB2.0 protocol analyzer based on FPGA characterized by comprising differential signal samples input module, patrols
Collect control device, host interface and data storage；
Differential signal sampling input module and data storage are connect with logic control device respectively；
Differential signal sampling input module transmits on USB2.0 differential bus in normal operating conditions for acquiring equipment under test
Data；
Logic control device is enumerated for realizing USB2.0 protocol analyzer, sampled result is read from sampling front-end, by data
It is buffered to data storage, and sampled data is uploaded to prison by host interface as unit of the usb data packet for presetting size
Control host.
2. the USB2.0 protocol analyzer according to claim 1 based on FPGA, which is characterized in that
Logic control device includes: FPGA main controller module, control fifo module and control interface；
Control fifo module is connect with FPGA main controller module；
FPGA main controller module is used to read the differential impedance data of acquisition from differential signal sampling input module, and will read
Differential impedance data buffering in data storage；Control fifo module configures FPGA main controller module to advanced elder generation
Mode out reads differential impedance data from data storage and is handled；Will treated data buffer storage in data storage
In, while by treated, data pass through host interface for differential impedance data from data storage in a manner of first in first out
It is transmitted to monitoring host computer.
3. the USB2.0 protocol analyzer according to claim 1 or 2 based on FPGA, which is characterized in that
Differential signal samples input module and uses non-intrusion type detection mode, acquires the differential impedance on differential bus；
The precision that the differential output impedance of the front end difference amplifier of differential signal sampling input module meets 90ohm ± 15% is wanted
It asks.
4. the USB2.0 protocol analyzer according to claim 1 or 2 based on FPGA, which is characterized in that
Differential signal sampling input module samples differential impedance using high-speed-differential amplifier AD8352.
5. the USB2.0 protocol analyzer according to claim 1 or 2 based on FPGA, which is characterized in that
Logic control device further include: USB physical layer interface chip, after differential signal samples input module serial samples, choosing
Serial differential signals are converted to the parallel data of byte wide with USB physical layer interface chip CY7C68000.
6. the USB2.0 protocol analyzer according to claim 2 based on FPGA, which is characterized in that
The CYCLONE Series FPGA chip EP1C12 of FPGA main controller module selection Altera；
Data storage is using the High speed asynchronous FIFO of Integrated Device Technology, Inc. as data buffer.
7. the USB2.0 protocol analyzer according to claim 1 or 2 based on FPGA, which is characterized in that
Protocol layer and the firmware layer processing of logic control device are realized using based on the pure hardware circuit of FPGA and VHDL language.
8. a kind of usb protocol analysis method based on FPGA, which is characterized in that method includes:
Differential signal samples the differential impedance on input module acquisition differential bus；
Logic control device reads the differential impedance data of acquisition from differential signal sampling input module, and to differential impedance data
It is handled, differential impedance data is transmitted to by monitoring host computer by host interface after processing；Logic control device be also used to by
Differential impedance data storage is to data storage after the acquisition differential impedance data of reading and processing.
9. the usb protocol analysis method according to claim 8 based on FPGA, which is characterized in that
FPGA main controller module reads the differential impedance data of acquisition from differential signal sampling input module, and by the difference of reading
Impedance data is divided to be buffered in data storage；Control fifo module configures FPGA main controller module to first in first out
Mode reads differential impedance data from data storage and is handled；Will treated data buffer storage in data storage,
By treated, data are passed differential impedance data by host interface from data storage in a manner of first in first out simultaneously
Transport to monitoring host computer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113886163A (en) * | 2021-10-28 | 2022-01-04 | 珠海一微半导体股份有限公司 | USB signal detection device and system |
| WO2022088542A1 (en) * | 2020-11-02 | 2022-05-05 | 芯启源(上海)半导体科技有限公司 | Fpga-based usb3.0/3.1 control system |
| CN114489476A (en) * | 2021-12-16 | 2022-05-13 | 深圳市德明利技术股份有限公司 | Flash memory data acquisition device and acquisition method based on FPGA |
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Application publication date: 20190419 |