CN1996578A - 微器件的触点 - Google Patents

微器件的触点 Download PDF

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Publication number
CN1996578A
CN1996578A CNA2006100642009A CN200610064200A CN1996578A CN 1996578 A CN1996578 A CN 1996578A CN A2006100642009 A CNA2006100642009 A CN A2006100642009A CN 200610064200 A CN200610064200 A CN 200610064200A CN 1996578 A CN1996578 A CN 1996578A
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CN
China
Prior art keywords
substrate
micro element
contact tab
patterned layer
recess
Prior art date
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Pending
Application number
CNA2006100642009A
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English (en)
Inventor
F·G·C·比杰南
W·D·维恩尼克
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ASML Netherlands BV
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ASML Netherlands BV
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Filing date
Publication date
Application filed by ASML Netherlands BV filed Critical ASML Netherlands BV
Publication of CN1996578A publication Critical patent/CN1996578A/zh
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    • G03F7/70375Multiphoton lithography or multiphoton photopolymerization; Imaging systems comprising means for converting one type of radiation into another type of radiation
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Abstract

本发明提供具有接触凸块的微器件以及制造该微器件的方法,其中微器件例如是集成电路。该微器件在该微器件两侧或多侧上具有接触凸块。本发明还提供叠置式微器件。

Description

微器件的触点
技术领域
本发明涉及微器件。
背景技术
光刻装置是一种将所希望的图案施加到基底上,通常施加到基底的目标部分上的机器。光刻装置可以用在例如集成电路的微器件的制造过程中。图案形成装置,例如中间掩模版,可以用于产生例如形成在集成电路的各层上的电路图案。该图案可以被转印到基底(例如,硅晶片)上的目标部分(例如,包括部分、一个或多个管芯)上。通常通过在基底上的辐射敏感材料(抗蚀剂)层上成象进行图案的转印。一般情况下,单个基底将包含被相继图案化的邻近目标部分的网格。已知的光刻装置包括所谓的步进器,其中每个目标部分都通过一次将整个图案曝光在目标部分上而被辐射,并且包括所谓的扫描器,其中每个目标部分是通过将图案沿给定方向(“扫描”方向)扫描通过辐射束,同时与该方向平行或反向平行地扫描基底而被辐射的。还可以通过将图案压印到基底上来将图案从图案形成装置转印到基底。
通常,多层图案形成于基底上,从而形成三维尺寸的微结构,例如电路。一旦这个工艺完成,那么因此形成的集成电路则通常是“封装的”。封装可以包括将集成电路设置在塑料外壳内,该塑料外壳具有导电引线。在封装内,在导电引线和集成电路的电路之间建立连接。正需要的是改进导电引线和集成电路的电路之间设置的连接。
发明内容
在实施例中,提供一种微器件(例如,集成电路),其具有至少两侧(例如,相反的两侧),这两侧具有接触凸块。
在实施例中,提供一种方法,包括:
在基底的第一侧上形成微结构,所述基底具有背离所述第一侧面的第二侧面;
在所述第二侧中蚀刻凹槽,所述凹槽达到所述微结构;
利用金属填充凹槽,从而提供接触凸块。
还有,叠置式微器件包括第一微器件和第二微器件,所述第一和第二微器件通过接触凸块连接。
而且,提供一种制造微器件的方法,该微器件例如是集成电路,该方法包括:
在基底的第一侧上形成对准标记;
在基底的第二侧上形成多个图案层,该图案层一起形成微器件,该图案层与对准标记对准;
在基底的第一侧上蚀刻凹槽,该凹槽与对准标记对准,对该凹槽进行蚀刻,直到露出第一图案层;以及
在与第一图案层接触的凹槽内形成接触凸块。
此外,提供一种具有多个图案层的基底,这些图案层一起构成微器件,例如集成电路,该基底还具有位于基底的凹槽中的一组接触凸块,这样它们与最深处的图案层电接触。
而且,还提供一组三个或更多叠置在一起的基底,每个基底都具有微器件,例如集成电路,并且在两侧上具有接触凸块,从而使得邻近的基底彼此电联系,并且允许提供外部连接给基底组。
附图说明
本发明的实施例现在将仅仅通过示例的方式,参考所附的示意性附图进行描述,其中:
图1示出了根据本发明的一个实施例的光刻装置;
图2是说明基底台的示意性横截面图,该基底台包含用于双侧对准的光学系统的两个分支;
图3是示出双侧对准光学器件的位置和定位的基底的平面图;
图4是示出双侧对准光学器件的另一个位置和定位的平面图;
图5是具有整体光学部件的基底台的一部分的横截面图;以及
图6a-6i示出了基底的横截面图,其示意性的示出了本发明的实施例。
图7A和7B示出了根据本发明的一个实施例叠置微器件的示意图。
图8A-8C示出了根据本发明的一个实施例叠置微器件的示意图。
具体实施方式
在一个实施例中,本发明提供了一种具有接触凸块的微器件。
首先,图1-5描述了用于制备根据本发明的微器件的装置的一个示例。
图1示意性的描述了根据本发明的一个实施例的一种光刻装置。该装置包括:
一被构造成调节辐射束B(例如,UV辐射或EUV辐射)的照射系统(照射装置)IL。
-被构造成支撑图案形成装置(例如,掩模)MA并且连接到第一定位器PM的支撑结构(例如,掩模台)MT,其中第一定位器PM用于根据特定的参数精确地定位图案形成装置;
被构造成固定基底(例如,涂覆抗蚀剂的基底)W并连接到第二定位器PW的基底台(例如,基底台)WT,其中第二定位器PW用于根据特定的参数精确的定位基底;以及
被构造成将图案形成装置MA赋予辐射束B的图案投影到基底W的目标部分C(例如,包括一个或多个管芯)的投影系统(例如,折射投影透镜系统)PS。
照射系统可以包括多种类型的光学部件,例如折射、反射、磁、电磁、静电或其它类型的光学部件,或者它们的组合,用于引导、成形或控制辐射。
该支撑结构支撑,也就是承受图案形成装置的重量。它根据图案形成装置的定位、光刻装置的设计以及其它条件,例如图案形成装置是否固定在真空环境中,来固定图案形成装置。该支撑结构可以使用机械、真空、静电或其它夹紧技术来固定图案形成装置。该支撑结构可以是框架或台,例如,它们可以根据需要被固定或移动。该支撑结构可以确保图案形成装置处于所希望的位置,例如,相对于投影系统处于所希望的位置。这里使用的术语“中间掩模版”或“掩模”可以被认为是更通用的术语“图案形成装置”的同义词。
这里使用的术语“图案形成装置”可以被广义的理解为指可以用于给辐射束的横截面赋予图案以产生基底的目标部分中的图案的任何装置。应当注意到的是,被赋予给辐射束的图案将不精确的对应基底的目标部分中所希望的图案,例如,如果该图案包括相移特征或者所谓的辅助特征。通常情况下,被赋予给辐射束的图案将对应目标部分中产生的装置的特定功能层,例如集成电路。
图案形成装置可以是透射或反射型的。图案形成装置的示例包括掩模、可编程反射镜阵列以及可编程LCD板。掩模是光刻中公知的,并且包括多种掩模类型,例如二进制、交替相移、衰减相移以及各种混合掩模类型。可编程反射镜阵列的一个示例采用矩阵设置的小反射镜,每个小反射镜都可以被单独的倾斜,从而沿不同的方向反射入射辐射束。倾斜的反射镜在被反射镜矩阵反射的辐射束中赋予图案。
这里所使用的术语“投影系统”应当被广义理解为包含任意类型的投影系统,包括折射、反射、反折射、磁、电磁以及静电光学系统,或它们的任意组合,只要适合于所使用的曝光辐射,或者适合于其它的因素,例如使用浸液或者使用真空的情况。这里所使用的术语“投影透镜”可以被认为是更通用的术语“投影系统”的同义词。
在本发明的一个示例性实施例中,该装置是透射型(例如,采用透射性掩模)的装置。另外,该装置可以是反射型(例如,采用可编程的反射镜阵列或者采用反射掩模)的装置。
光刻装置可以是一种具有两个(双工作台)或更多的基底台(和/或两个或更多的掩模台)类型的装置。在这种“多工作台”机器中,另外的台可以并行使用,或者在一个或多个台上可以进行预备的步骤,而一个或多个其他台用于曝光。
光刻装置还可以是这样的类型,即其中基底的至少一部分被液体覆盖,从而填充投影系统和基底之间的空间,其中该液体例如水具有相对高的折射率。浸液还可以被施加给光刻装置中的其它空间,例如掩模和投影系统之间。浸没法是现有技术中公知的用于增加投影系统的数值孔径的方法。这里所使用的术语“浸没”并不表示例如基底的结构必须被液体浸没,而表示的是在曝光期间该液体位于投影系统和基底之间。
现在参考图1,照射装置IL从辐射源SO接收辐射束。该辐射源和光刻装置可以是单独的主体,例如当辐射源是受激准分子激光器时。在这种情况下,该辐射源不被认为构成光刻装置的一部分,并且辐射束利用束传送系统BD从辐射源SO传递到照射装置IL,其中束传送系统BD包括例如合适的定向反射镜和/或光束扩展器。在其它的情况中,该辐射源可以是光刻装置的组成部分,例如当该辐射源是汞灯时。该辐射源SO和照射装置IL(在需要情况下与束传送系统BD一起)可以被称作辐射系统。
照射装置IL可以包括用于调节辐射束的角强度分布的调节器AD。通常情况下,照射装置的光瞳平面中的强度分布的至少外部和/或内部辐射范围(通常分别被称为σ-外σ-内)可以被调节。此外,照射装置IL可以包括各种其它的元件,例如积分器IN和聚光器CO。该照射装置可以用于调节辐射束,从而在辐射束横截面具有所希望的均匀性以及强度分布。
辐射束B入射到图案形成装置(例如,掩模MA)上,该图案形成装置被固定在支撑结构(例如,掩模台MT)上,并且被图案形成装置图案化。横穿掩模MA的辐射束B通过投影系统PS,该投影系统将辐射束聚焦在基底W的目标部分C上。在一个实施例中,抗蚀层位于该基底上。在一个实施例中,基底W是一种晶片,例如是半导体晶片。在一个实施例中,晶片材料从由Si,SiGe,SiGeC,SiC,Ge,GaAs,InP和InAs组成的组中选择出。在一个实施例中,晶片是III/V族化合物半导体晶片。在一个实施例中,该晶片是硅晶片。在一个实施例中,该基底是陶瓷基底。在一个实施例中,该基底是玻璃基底。玻璃基底可以用在例如制造平板显示器和液晶显示板中。在一个实施例中,该基底是塑料基底。在一个实施例中,该基底是柔性的。在一个实施例中,该基底是透明的(对于人的裸眼来说)。在一个实施例中,该基底是彩色的。在一个实施例中,该基底是没有颜色的。
在第二定位器PW和位置传感器IF(例如,干涉测量装置,线性编码器或电容传感器)的帮助下,基底台WT可以被精确的移动,例如,从而将不同的目标部分C定位在辐射束B的路径中。类似的是,例如在从掩模库机械取出掩模之后,或者在扫描期间,第一定位器PM和另一个位置传感器(图1中没有明显绘制出)可以用来相对于辐射束B的路径精确定位掩模MA。通常情况下,掩模台MT的移动可以利用形成第一定位器PM的一部分的长行程模块(粗调定位)和短行程模块(细调定位)的帮助来实现。类似的是,基底台WT的移动可以利用形成第二定位器PW的一部分的长行程模块和短行程模块来实现。在步进器(相对于扫描器)的情况下,掩模台MT仅可以连接到短行程致动器,或者可以被固定。掩模MA和基底W可以利用掩模对准标记M1,M2和基底对准标记P1,P2来对准。虽然所示的基底对准标记占用了指定的目标部分,但是它们可以位于目标部分(被称为划线道对准标记)之间的空间内。类似的是,在超过一个模具位于掩模MA上的情况下,掩模对准标记可以定位在模具之间。
所绘制出的装置可以用于例如一个或多个以下的模式中:
1.在步进模式中,掩模台MT和基底台WT基本上保持稳定,而赋予给辐射束的整个图案一次投射到目标部分C上(也就是,单次静态曝光)。基底台WT然后沿X和/或Y方向移位,从而可以曝光不同的目标部分C。在步进模式中,曝光场的最大尺寸限制了在单次静态曝光中成像的目标部分C的尺寸。
2.在扫描模式中,掩模台MT和基底台WT被同时扫描,而赋予辐射束的图案投射到目标部分C上(也就是,单次动态曝光)。基底台WT相对于掩模台MT的速率和方向可以由投影系统PS的(反)放大和图像反转特性决定。在扫描模式中,曝光场的最大尺寸限制了在单次动态曝光中成像的目标部分的尺寸的宽度(沿非扫描方向),而扫描动作的长度决定目标部分的高度(沿扫描方向)。
3.在另一种模式中,掩模台MT基本上保持静止地固定可编程图案形成装置,并且当赋予给辐射束的图案投射到目标部分C上时,基底台WT被移动或扫描。在这种模式中,通常采用脉冲辐射源,并且在基底台WT的每一次移动之后或者在扫描期间的连续的辐射脉冲之间,可编程的图案形成装置根据需要被更新。这种操作模式可以容易地应用于利用可编程图案形成装置的无掩模光刻中,其中可编程图案形成装置例如是上述类型的可编程反射镜阵列。
还可以采用上述应用模式的组合和/或变化,或者完全不同的应用模式。
图2示出了基底台WT上的基底W。基底掩模WM3和WM4位于基底W的第一侧(“前侧”),并且光可以从这些标记被反射,这由WM3和WM4上的箭头表示,并且用于与连接到对准系统(未示出)的掩模上的标记进行对准。这种前侧对准的一个示例由2003年12月17日提交的美国专利申请公开号2005-0133743更加详细说明,其整个在这里被结合用作参考。
基底标记WM1和WM2位于基底W的第二侧(“后侧”)上。在光刻应用中,基底W的后侧在此是指背离暴露于辐射那侧的基底的侧部。尽管图2所示出的实施例描述了基底的两侧上的对准标记,但是在一个实施例中,该标记可以仅仅位于基底的一侧上。例如,特定侧上的标记可以首先用作前侧对准中的前侧标记,并且当基底翻转时,相同的标记可以用作后侧标记(反之亦然)。
一种光学系统被构造到基底台WT中,用于提供至基底W的后侧上的基底标记WM1、WM2的光学路径。光学系统包括一对臂10a,10b。每个臂都由两个反射镜12、14和两个透镜16、18组成。每个臂中的反射镜12、14被倾斜,从而使得它们与水平方向所成角度的总和为90°。通过这种方式,当反射离开另一个反射镜时,竖直射到一个反射镜上的光束将保持竖直。当然,可以考虑获得方向上的180°的变化的其它方式。例如,透镜和安装可以被设计成,只要整个光学系统提供180°的方向变化,就认为它们造成了大部分的方向改变。
在使用中,光从反射镜12上的基底台WT通过透镜16和18引导到反射镜14上,然后引导到各个基底标记WM1,WM2上。光反射离开基底标记的部分,并且沿光学系统的臂借助反射镜14、透镜18和16和反射镜12返回。反射镜12、14和透镜16、18被设置成,使得基底标记WM1,WM2的像20a,20b形成在基底W的前(顶)部表面的平面上,对应于位于基底W的前侧上的基底标记WM3,WM4的竖直位置。透镜16,18和反射镜12,14的顺序可以不同,只要对于光学系统是合适的即可。例如,透镜18可以位于反射镜14和基底W之间(参见后面的实施例的说明)。
基底标记WM1,WM2的像20a,20b作为虚基底标记,并且可以通过与位于基底W的前(顶)侧上的实基底标记完全相同的方式用于通过预存在对准系统(未示出)对准。
如图2所示,光学系统10a,10b的臂产生移位到基底W的侧部的像20a,20b,因此它们可以通过基底W上方的对准系统观察。光学系统10a,10b的臂的两个优选的定位在图3和4中示出,其中图3和图4是位于XY平面的基底W的平面图。为了清楚起见,在图3和图4中省去基底台WT。在图3中,光学系统10a,10b的臂沿X轴对准。在图4中,光学系统10a,10b的臂与Y轴平行。在两种情况中,基底标记WM1,WM2位于X轴上。基底标记WM1,WM2位于基底W的下侧,因此它们与基底W的顶侧的观察点相反。但是,光学系统的臂的反射镜12、14的结构可以被构造成,使得基底标记WM1,WM2的像20a,20b恢复到适当的定位。因此,如果像位于基底W的顶侧上,那么呈现的像完全相同。光学系统还可以被设置成,使得基底标记WM1,WM2与它的像20a,20b的尺寸的比例是1∶1,也就是,没有放大或减小。结果是,如果像20a,20b可以像基底W的前侧上的实基底标记一样被精确的使用。位于掩模上的普通对准图案或键可以用于进行与实和虚基底标记的对准。
在当前的示例中,基底标记位于相应位置的基底W的前侧和后侧上,如图2所示。在图3和4中,为了更加清楚,仅有基底W的后侧上的基底标记被示出。根据这种结构,当基底W通过大概绕X或Y轴旋转而翻转时,位于基底W的顶侧上的基底标记现在可以位于基底W的下侧上,但是处于可以由光学系统10a,10b的臂成像的位置。
应当注意到的是,由于这种反射镜的设置,沿平行于光学系统的臂10a,10b的一个方向移动基底W将沿相反方向移动基底的下侧上的基底标记WM1,WM2的相应像20a,20b。例如,在图3中,如果基底W被移位到右侧,那么像20a,20b则会被移位到左侧。当确定基底标记WM1,WM2的位置,以及当进行对准时调节基底W和掩模的相对位置时,软件控制对准系统会考虑到这种情况。如果光学系统10a,10b的两臂对称,那么当基底被移位时,像20A和20B之间的间隔实际上将保持为常数。
在本发明的另一个实施例中,基底台WT可以具有不相对于基底标记WM1,WM2的移动改变像20a,20b的移动方向的反射镜结构。
至少两个基底标记可以位于基底W的一侧上。单个标记可以提供关于掩模上特定点相对于基底上特定点的像的相对位置的信息。但是,为了确保正确的定位对准和放大,优选使用至少两个标记。
图5示出了基底台WT的一部分的横截面。根据本发明的一个实施例,用于在基底的后侧上成像基底标记的光学系统10a,10b可以通过特殊的方式被构造到基底台WT中。如图5所示,光学系统的臂的反射镜12、14不会作为分立部件,而是可以与基底台WT成为整体。合适的面被机械加工成基底台WT,该基底台然后可以提供有涂层从而改进反射率,从而形成反射镜12,14。光学系统可以由与基底台相同的材料制成,例如ZerodurTM,其具有十分低的热膨胀系数并且因此可以有助于获得较好的对准精度。
基底标记WM1,WM2,WM3和WM4可以位于基底W上,从而允许基底W相对于投射的图案束对准。对基底W的不同层彼此进行正确的定位需要对准。基底W可以由多层构造,这些层均相继形成在基底W上,并且经受曝光。由于不同的层被构造成用于形成工作装置,因此不同的曝光应当相对彼此被最佳对准。
图1至5中所述的光刻装置可以用于制造例如集成电路的微器件的输入/输出触点。集成电路可以被安装在封装中,该封装包括塑料外壳以及导电引线。导电引线使得集成电路可以容易的连接到例如印刷电路板。封装的一个示例被称为倒装芯片封装。在倒装芯片封装中,光刻用于提供一组球形的焊料,该焊料从集成电路的上表面凸出。焊料球位于提供电触点给集成电路的位置。该集成电路被倒置(翻转)并且被置于基板上。该基板具有导电引线,该导电引线具有被设置为与焊料球电接触的接触区域。该触点可以通过加热焊料制成,以使得它熔化在基板的导电引线上。在另一种结构中,金可以用来代替焊料。金和基板的导电引线之间的接触可以通过例如给金施加压力来实现。
在本发明的一个实施例中,图1至5中所描述的装置可以用来在集成电路的第一侧和第二侧上提供接触凸块,其中接触凸块例如是金属。可以通过其实现的过程的一个示例由图6示意性的示出。
参考图6a,抗蚀层30位于基底31上。由于基底31在图6所示的过程中被倒置,因此为了易于指明,基底的侧部被标记。具有图6a(也就是,图6a中的前侧)中的抗蚀层的基底31的侧部被标记为A侧。位于图6a中最下方(也就是,图6a的后侧)的基底31的侧部被标记为B侧。
现在参考图6b,对准标记32例如通过使用图1示意性示出的光刻装置曝光在抗蚀层30中。此外,接触凸块所位于的区域也曝光。该区域在下面将被称为接触区域33。应当理解,任何适合的光刻装置都可以用来曝光对准标记32和接触区域33。使用光学光刻不是必须的;例如也可以使用压印光刻。实际上,压印光刻在产生对准标记32和接触区域33中是很合适的,这是因为这些对准标记32和接触区域33不必与任何之前的层对准(通过使用压印光刻实现层之间的精确的对准是相对麻烦的)。对准标记32和接触区域33可以在一个步骤中被曝光(或被压印)。或者,它们可以在不同的步骤中被曝光(或被压印);例如,对准标记32可以首先被曝光,然后用于确定曝光接触区域33的正确位置。
现在参考图6c,例如通过传统的方式显影曝光的抗蚀剂。例如通过使用传统蚀刻化学品可以蚀刻抗蚀剂。化学品仅在抗蚀剂已经曝光的位置蚀刻进入抗蚀剂中。在所示出的实施例中,在相对短的时间周期进行蚀刻,以使得(从未曝光的抗蚀剂的上表面测量的)蚀刻到基底31中的距离例如为160纳米。
如图6d所示,对准标记32被覆盖有一层抗蚀剂。接下来,基底31被再次蚀刻,在这个时机进行蚀刻仅仅发生在接触区域33的位置(蚀刻不发生在对准标记32处,这是因为在这些位置抗蚀剂未被曝光)。在所示出的实施例中,继续进行蚀刻,直到它通过大部分的基底31,例如直到保留基底的小于100微米的厚度。在一个实施例中,余下基底的厚度小于50微米,例如,小于20微米。在蚀刻之后,接触区域33将被称为接触凹口33a,并且在图6e中被示出。
基底31被倒置(翻转),从而B侧变成基底31的前侧,如图6f所示。接下来,基底31被引入(或者再引入)图1至5中所示的光刻装置中。该光刻装置用来将图案层投射到基底31的B侧上。图案层与基底31的A侧上的对准标记32对准,其中该A侧现在是基底的后侧。实现与对准标记32对准的方式如上所述结合等效的对准标记WM1,WM2来描述。
由于位于基底31的上表面上的图案层与基底的后侧上的对准标记32对准,因此它们还相对于基底的后侧中的接触凹口33a对准。这使得图案的合适的部分位于接触凹口33a的正上方。例如,希望提供触点的图案区域可以位于接触凹口33a的正上方。
应当理解,多个图案层34可以位于基底31的前侧(B侧)上,例如图6g中所示。如前所述,每一层都与位于基底31的后侧(A侧)上的对准标记32对准。可选地或者另外地,一些图案层可以与位于基底的上侧(B侧)上的对准标记对准。在一个或多个图案层曝光期间,合适的对准标记可以位于基底31的上侧上。
一旦完成了图案层的曝光和处理,例如焊料的导电材料35的凸块可以位于基底31的前侧(B侧)上的合适的位置。通过在图案层的顶部上提供厚层的抗蚀剂,然后利用例如图1至5中所述的光刻装置曝光抗蚀剂,以制成焊料的凸块,其中抗蚀剂在提供焊料的凸块的位置曝光。然后,通过传统的方式进行蚀刻,以除去曝光的抗蚀剂。焊料被电镀到基底上,并且通过传统方式被处理,因此仅有位于蚀刻凹口中的焊料保留。抗蚀剂通过传统方式从基底剥离,从而留下从基底向上突出的块状的焊料。然后,焊料在有限的时间周期内被加热,因此它被熔化成球状然后硬化。这还被称为再回流焊料。所得到的球形接触凸块35在图6g中被示出。
参考图6h,蚀刻用来除去留在接触凹口33a中的基底31的厚度。结果是,最下面图案层的下侧被露出。然后,基底31被倒置(A侧现在位于B侧的顶部上)。焊料被电镀到基底31的前侧(B侧)上,然后被处理,从而使得位于接触凹口33a中的任意的焊料以及在接触凹口上方伸出的小部分保留。这些将被称为接触凸块36,并且在图6i中被示出。从图6可以很明显的看出,基底的一侧上的接触凸块可以利用器件层与基底的另一侧上的接触凸块分开。而且,基底的一侧上的接触凸块不需要完全与基底的另一侧上的接触凸块相对。
基底31可以通过将其设在封装内而被封装,其中封装具有连接到基底31的A侧上的球形接触凸块35以及连接到基底的B侧上的接触凸块36的导电引线。这可以通过例如提供两个基板来实现,其中每个基板都具有导电引线和相连的接触区域,其中第一基板固定到基底31的A侧,并且第二基板固定到基底的B侧。
在基底31的两侧上提供触点的优点之一是,它可以获得更多的到基底的连接。而且,它还可以使超过一个的基底结合在一起,其中来自每个基底的触点彼此连接,以使得位于基底上的集成电路彼此电连通。参见例如图7A,B。
图8A,B,C中绘制出了另一个实施例。在图8A中,第一基底具有接触凸块,并且第二基底具有凹口。该凹口相对于凸块对准,并且在图8B中,该凹口位于凸块上方。图8C表示凸块随后经历加热过程的情况。尽管图7和8所示出的实施例涉及2个基底/微器件,但是应当理解,本发明允许叠置更多的基底/微器件。例如,在图8中,第二基底可以具有面向背离凹口的表面上的凸块,并且具有凹口的第三基底可以通过与第二基底设于第一基底上方的类似的方式设于第二基底上方。
虽然本发明主要描述了焊料用来制造触点的情况,但是应当理解,任何合适的导电材料都可以用来制造触点(例如,可以使用金或另外的合适的金属)。而且,尽管本发明主要描述的是球形的凸块,但是应当理解,可以使用任意合适的形状,例如矩形或正方形的多边形形状。
虽然已经结合按特定顺序执行的图6a-6i所示出的步骤来描述本发明的实施例,但是应当理解,这些步骤可以以不同的顺序来进行。例如,可以在图案层34已经位于基底31上之后进行接触凹口33a的蚀刻。当完成该步骤之后,接触凹口33a可以被蚀刻通过到一层图案层34(正常情况下,这会是已经位于基底31上的第一图案层)。执行这些步骤的顺序的其它改变对于本领域的技术人员来说是很明显的。
在三个或更多的基底被叠置的情况下,将不能直接达到中间的基底上的例如集成电路的微器件。因此希望上部和下部的微器件被构造成,可以通过合适定位的触点合适地达到中间微器件。例如,电压源可以通过来自一个外部微器件的连接而连接到中间微器件。
虽然本发明具体参考在制造IC中使用光刻装置的情况,但是应当理解,这里所描述的系统在一些情况下具有其它的应用,例如制造集成光学系统,用于磁畴存储器的引导和探测模型,平板显示器,液晶显示器(LCD),薄膜磁头等等。本领域技术人员应当理解,在这种可选的应用范围内,这里的术语“晶片”或“管芯”的任何使用都可以分别被认为是更通用的术语“基底”或“目标部分”的同义词。
尽管在上文中具体参照光学光刻应用已经对本发明的实施例进行了描述,但是应当理解,本发明可以用于其它的应用,例如压印光刻,以及上文并不限制于光学光刻。在压印光刻中,图案形成装置中的形貌限定基底上产生的图案。图案形成装置的形貌可以被压到提供给基底的抗蚀层中,在该基底上通过施加电磁辐射、加热、压力或它们的组合抗蚀剂被固化。图案形成装置移出抗蚀剂,并在抗蚀剂被固化之后在其中留下图案。
这里所使用的术语“辐射”和“束”包含所有类型的电磁辐射,包括紫外线(UV)辐射(例如,其具有大约为436,365,355,248,193,157或126nm的波长),远紫外线(EUV)辐射(例如,其具有5-20nm范围的波长),以及例如离子束或电子束的粒子束。
上文中提到的术语“透镜”可以指多种类型的光学部件的任意一种或组合,这些光学部件包括折射、反射、磁、电磁和静电光学部件。
根据这里所公开的本发明的说明和实践,本发明的其它实施例、使用和优点对于本领域的技术人员来说是很明显的。说明书应当仅仅作为示例,因此本发明的范围仅仅由下面的权利要求来限定。

Claims (22)

1、一种具有至少两侧的微器件,所述两侧具有接触凸块。
2、如权利要求1所述的微器件,其中所述微器件是集成电路。
3、如权利要求1所述的微器件,其中所述接触凸块包括焊料。
4、如权利要求1所述的微器件,其中所述接触凸块包括金。
5、如权利要求1所述的微器件,其中所述接触凸块基本上为球形。
6、一种包括权利要求1所述的微器件的外壳,其中外壳具有金属引线。
7、如权利要求6所述的外壳,其中金属引线与接触凸块接触。
8、一种包括叠置两个或更多的微器件方法,所述两个或更多的微器件的至少一个是具有至少两侧的微器件,所述两侧具有接触凸块。
9、一种包括第一微器件和第二微器件的微器件的微器件叠置体,所述第一和第二微器件通过接触凸块连接。
10、如权利要求9所述的微器件叠置体,其中所述第一和第二微器件均包括至少一个侧面,所述至少一个侧面具有接触凸块,并且其中第一微器件的一侧上的接触凸块连接到第二微器件的一侧上的接触凸块。
11、如权利要求9所述的微器件叠置体,其中
所述第一微器件包括具有接触凸块的一侧,
所述第二微器件形成在具有凹口的基底上,所述凹口形成在背离第二微器件的一侧上,以及
接触凸块通过一个或多个凹口达到第二微器件。
12、如权利要求9所述的微器件叠置体,其中超过两个的微器件被叠置。
13、一种制造集成电路的方法,该方法包括:
在基底的第一侧上形成对准标记;
在基底的第二侧上形成多个图案层,所述图案层一起构成集成电路,并且所述图案层相对对准标记被对准;
在基底的第一侧上蚀刻凹口,该凹口相对对准标记对准,并且对凹口进行蚀刻,直到露出第一图案层;以及
在与第一图案层接触的凹口内形成接触凸块。
14、根据权利要求13所述的方法,其中所述对准标记和蚀刻凹口的所述位置在相同的光刻步骤中被限定。
15、根据权利要求13所述的方法,其中对准标记和蚀刻凹口的位置在独立的光刻步骤中被限定。
16、根据权利要求13所述的方法,其中在提供图案层到基底的第二表面上之前蚀刻凹口,该蚀刻通过基底的超过一半。
17、根据权利要求13所述的方法,其中在提供图案层到基底的第二表面上之后蚀刻凹口,该蚀刻通过其中一个图案层。
18、根据权利要求13所述的方法,其中接触凸块也形成在基底的第一侧上。
19、根据权利要求13所述的方法,其中通过使用对准系统来实现基底的第二侧上的多个图案层与基底的第一侧上的对准标记的对准,该对准系统包括位于基底的第二侧上方的对准探测器以及被设置为使得对准探测器可以与对准标记进行光学联系的光学系统。
20、一种具有多个一起形成集成电路的图案层的基底,该基底还具有一组位于基底的凹口内的接触凸块,使其与最深处的图案层电连接。
21、根据权利要求20所述的基底,该基底具有第二组接触凸块,所述第二组接触凸块位于最外侧图案层的顶部上,并且与其电连接。
22、根据权利要求21所述的基底,其中所述基底是多个基底之一,所述基底通过彼此连接的各个接触凸块而相互电联系。
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