CN1983228A - System for transmitting control signal by internal IC bus - Google Patents
System for transmitting control signal by internal IC bus Download PDFInfo
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- CN1983228A CN1983228A CN 200510102370 CN200510102370A CN1983228A CN 1983228 A CN1983228 A CN 1983228A CN 200510102370 CN200510102370 CN 200510102370 CN 200510102370 A CN200510102370 A CN 200510102370A CN 1983228 A CN1983228 A CN 1983228A
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- pin
- bus
- controller
- microcontroller
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Abstract
A control system using internal integrated circuit bus transmission to control signal is prepared as setting multiple pin on controller, connecting these pins separately to clock line and multiple data line one by one, providing relevant clock signal and control signal to each controlled peripheral unit with the same address by said controller through each data line and clock line.
Description
[technical field]
The invention relates to a kind of control system, particularly about a kind of control system that adopts the internal integrate circuit bus transmission of control signals.
[background technology]
Internal integrate circuit bus (Inter Integrated Circuit BUS, I
2C-BUS) be a kind of interior two-wire system serial expansion bus of chip that is widely used in consumer electronics, communication and industrial electronic etc. that Philips Semiconductor Co., Ltd. proposes.I
2The IC interior control bus that C-BUS is made up of two bidirectional data lines, its principal feature is only to need two data transmission paths, be the serial datum line (Serial Data Line, SDA) and a serial clock line (Serial Clock Line, SCL).Each parts that is connected on the bus all have unique address.I
2C-BUS allows some compatible devices (as internal memory, analog/digital converter, digital/analog converter and organic light emitting diode display driver, LCD driver etc.) shared bus.I
2The address signal addressing that last all devices of C-BUS will rely on data line to send does not need chip select line.Any moment I
2C-BUS can only be by the control of main device, respectively from device in I
2Log-on data transmitted when C-BUS was idle, by I
2Which main device of C-BUS arbitration passes through I
2C-BUS control is from device.I
2C-BUS is the many host buses of high-performance that possess functions such as bus arbitration and high low speed device synchronization.
Please refer to Fig. 1, is a kind of employing I of prior art
2The control system structural representation of C-BUS transmission of control signals.This control system 100 comprises microcontroller (Microprogrammed Control Unit, MCU) 10, the first clock line SCL1, the first data line SDA1, second clock line SCL2, the second data line SDA2, the 3rd clock line SCL3 and the 3rd data line SDA3.This microcontroller 10 comprises six pins, and first pin 1, second pin 2, the 3rd pin 3, the 4th pin 4, the 5th pin 5 are connected with the first clock line SCL1, the first data line SDA1, second clock line SCL2, the second data line SDA2, the 3rd clock line SCL3 and the 3rd data line SDA3 respectively with the 6th pin 6.First pin 1 of this microcontroller 10 and second pin 2 provide first clock signal and first control signal to controlled first peripherals (figure does not show) by the first clock line SCL1 and the first data line SDA1 respectively.The 3rd pin 3 of this microcontroller 10 and the 4th pin 4 provide the second clock signal and second control signal to controlled second peripherals (figure does not show) by the second clock line SCL2 and the second data line SDA2.The 5th pin 5 of this microcontroller 10 and the 6th pin 6 provide the 3rd clock signal and the 3rd control signal to controlled the 3rd peripherals (figure does not show) by the 3rd clock line SCL3 and the 3rd data line SDA3.This first, second identical with the address of the 3rd peripherals.
Setting the peripherals that microcontroller 10 is controlled in the above-mentioned control system 100 is that N (N 〉=1, N is an integer) is individual, and then this microcontroller 10 needs 2N pin to provide control signal to the peripherals of being controlled.Bigger as the N value, then the pin of this microcontroller 10 will be more, therefore expend more pin, increase the element cost.
[summary of the invention]
Thereby in order to overcome prior art since adopt the internal integrate circuit bus transmission of control signals control system control peripherals more multi-microcontroller expend the defective that many more pins increase the element cost, be necessary to provide a kind of control peripheral devices more but microcontroller expends less pin, thereby reduce the control system of the employing internal integrate circuit bus transmission of control signals of element cost.
A kind of control system that adopts the internal integrate circuit bus transmission of control signals, it comprises: at least one controller, a clock line and many data lines, this controller comprises a plurality of pins, it is connected with clock line and many data lines are corresponding one by one respectively, and this controller provides corresponding clock signal and control signal to the identical peripherals in controlled each address by clock line and each bar data line.
Compared to prior art, the identical peripherals in control equal number address, the needed pin number of microcontroller is less in the above-mentioned control system, therefore saves the pin of microcontroller, reduces the element cost.
[description of drawings]
Fig. 1 is the employing I of prior art
2The control system configuration diagram of C-BUS transmission of control signals.
Fig. 2 is employing I of the present invention
2The control system structural representation of C-BUS transmission of control signals.
[embodiment]
Please refer to Fig. 2, is employing I of the present invention
2The control system structural representation of C-BUS transmission of control signals.This control system 200 comprises microcontroller 20, clock line SCL11, the first data line SDA12, the second data line SDA13 and the 3rd data line SDA14.This microcontroller 20 comprises four pins, and first pin 11, second pin 12, the 3rd pin 13 are connected with clock line SCL11, the first data line SDA12, the second data line SDA13 and the 3rd data line SDA14 respectively with the 4th pin 14.First pin 11 of this microcontroller 10 and second pin 12 provide first clock signal and first control signal to controlled first peripherals (figure does not show) by the clock line SCL11 and the first data line SDA12 respectively.First pin 11 of this microcontroller 20 and the 3rd pin 13 provide the second clock signal and second control signal to controlled second peripherals (figure does not show) by the clock line SCL11 and the second data line SDA13.First pin 11 of this microcontroller 20 and the 4th pin 14 provide the 3rd clock signal and the 3rd control signal to controlled the 3rd peripherals (figure does not show) by clock line SCL11 and the 3rd data line SDA14.This first, second identical with the address of the 3rd peripherals.
Setting the peripherals that microcontroller 20 is controlled in the above-mentioned control system 200 is that N (N 〉=1, N is an integer) is individual, and then this microcontroller 20 needs N+1 pin to provide control signal to the peripherals of being controlled.Compared to prior art, the identical peripherals in control equal number address, these microcontroller 20 needed pin numbers are less, therefore save the pin of microcontroller 20, reduce the element cost.
This microcontroller 20 not only can be microcontroller, also can be special IC (Application Specific Integrated Circuit, ASIC) (as LCD driver, random access memory or remote I/O etc.) or complex instruction set counter (Complex Instruction Set Computer, CISC) (as audio frequency and video processor etc.) etc.In addition, not only can adopt microcontroller 20 control peripheral devices, can adopt a plurality of controllers to be connected with clock line SCL11, the first data line SDA12, the second data line SDA13 and the 3rd data line SDA14 respectively.
Claims (4)
1. control system that adopts the internal integrate circuit bus transmission of control signals, it comprises: at least one controller, a clock line and many data lines, this controller comprises a plurality of pins, it is connected with clock line and many data lines are corresponding one by one respectively, and this controller provides corresponding clock signal and control signal to the identical peripherals in controlled each address by clock line and each bar data line.
2. the control system of employing internal integrate circuit bus transmission of control signals as claimed in claim 1 is characterized in that: this controller is a microcontroller.
3. the control system of employing internal integrate circuit bus transmission of control signals as claimed in claim 1 is characterized in that: this controller is a special IC.
4. the control system of employing internal integrate circuit bus transmission of control signals as claimed in claim 1 is characterized in that: this controller is the complex instruction set counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510102370 CN1983228A (en) | 2005-12-12 | 2005-12-12 | System for transmitting control signal by internal IC bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510102370 CN1983228A (en) | 2005-12-12 | 2005-12-12 | System for transmitting control signal by internal IC bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1983228A true CN1983228A (en) | 2007-06-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510102370 Pending CN1983228A (en) | 2005-12-12 | 2005-12-12 | System for transmitting control signal by internal IC bus |
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| CN (1) | CN1983228A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102650977A (en) * | 2011-02-28 | 2012-08-29 | 海力士半导体有限公司 | Integrated circuit |
| CN102650977B (en) * | 2011-02-28 | 2016-12-14 | 海力士半导体有限公司 | Integrated circuit |
| CN109099959A (en) * | 2018-06-20 | 2018-12-28 | 中国科学院电工研究所 | A kind of connection of digital sensor array and data read method |
| CN109308177A (en) * | 2018-08-15 | 2019-02-05 | 南京中感微电子有限公司 | A kind of apparatus for processing audio, earphone and audio player |
-
2005
- 2005-12-12 CN CN 200510102370 patent/CN1983228A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102650977A (en) * | 2011-02-28 | 2012-08-29 | 海力士半导体有限公司 | Integrated circuit |
| CN102650977B (en) * | 2011-02-28 | 2016-12-14 | 海力士半导体有限公司 | Integrated circuit |
| CN109099959A (en) * | 2018-06-20 | 2018-12-28 | 中国科学院电工研究所 | A kind of connection of digital sensor array and data read method |
| CN109099959B (en) * | 2018-06-20 | 2021-04-02 | 中国科学院电工研究所 | Connection and data reading method of digital sensor array |
| CN109308177A (en) * | 2018-08-15 | 2019-02-05 | 南京中感微电子有限公司 | A kind of apparatus for processing audio, earphone and audio player |
| CN109308177B (en) * | 2018-08-15 | 2021-09-21 | 南京中感微电子有限公司 | Audio processing device, earphone and audio player |
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