CN102650977B - Integrated circuit - Google Patents

Integrated circuit Download PDF

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CN102650977B
CN102650977B CN201110248048.0A CN201110248048A CN102650977B CN 102650977 B CN102650977 B CN 102650977B CN 201110248048 A CN201110248048 A CN 201110248048A CN 102650977 B CN102650977 B CN 102650977B
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data
signal
transmission
data wire
transmission line
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CN102650977A (en
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文眞永
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

The open a kind of integrated circuit of the present invention, including: multiple data wires, the data being directed at by multiple pulse signals are carried on the plurality of data wire;Multiple transmission lines;Data transfer unit, described data transfer unit is configured to respond to coherent signal and the data of the plurality of data wire is sent to the plurality of transmission line;Data outputting unit, described data outputting unit is configured to the data transmitting the corresponding transmission line of signal exporting with being activated in the plurality of transmission signal;Coherent signal generating unit, described coherent signal generating unit is configured as order input to using the logical value of one of latent time value and the plurality of transmission signal to produce coherent signal during coherent signal generating unit;And pulse signal generating unit, described pulse signal generating unit is configured as during order input sequentially activating multiple pulse signal.

Description

Integrated circuit
Cross-Reference to Related Applications
This application claims the priority of the korean patent application No.10-2011-0017901 submitted on February 28th, 2011, Entire contents is incorporated herein by reference.
Technical field
The exemplary embodiment of the present invention relates to a kind of integrated circuit.
Background technology
Although the demand of high speed integrated circuit is increased, but close to physics in the speed increasing integrated circuit The limit.Such as, in the case of memory device, for reducing the access time in core space (memory cell array district) further There is physics limit.In order to overcome such physics limit, memory device can be by processing data also in inside concurrently Output data increase the speed of input/output operations serially.Here, memory device use will also parallel to serial convertor The internal data that row processed is converted into serial data, and serial data is exported chip exterior.Here, in addition to memory device Multiple integrated circuit can perform in chip (system) parallel to serial data change.
Fig. 1 is the sequential chart illustrating the operation that four parallel datas are converted into serial data.
It is by the data being loaded on multiple transmission line P0 to P3 are sequentially transmitted to single line S parallel to serial conversion Realize.As shown in fig. 1, in the case of data D0 to D3 is loaded into four transmission line P0 to P3, four line P0 to P3 Data can be sent to output lead S one by one.Therefore, produce in parallel to serial conversion and use signal CK0 Determine that to CK3, described signal CK0 to CK3 the data D0 to D3 of upper for transmission line P0 to P3 alignment is sent to output lead S time Between point signal.
In operation, data D0 of line P0 are sent to line S at the time point that signal CK0 is activated, and data D1 of line P1 exist The time point that signal CK1 is activated is sent to line S.It addition, the time point that data D2 of line P2 are activated at signal CK2 is sent to Line S, data D3 of line P3 are sent to line S at the time point that signal CK3 is activated.
As it has been described above, be by the data being loaded on multiple transmission line are sequentially transmitted to defeated parallel to serial conversion Outlet realizes.Therefore, use determines the signal of the time point that data are sent to output lead from multiple transmission lines (referred to hereinafter as For transmission signal).2N: in the case of 1 parallel to serial conversion (especially 4:1 or 8:1 is parallel to serial conversion), permissible Produce four transmission signals by clock simply and produce the signal of the time point determining transmission data.For example, such as Fig. 1 Shown in, it is possible to use clock CLK produces transmission signal CK0, CK1, CK2 and CK3.
Four 4:1 transmitting signals and produce transmission signal CK0, CK1, CK2 and CK3 are produced by clock CLK using Or in the case of 8:1 is parallel to serial conversion, the order of transmission signal CK0, CK1, CK2 and CK3 and the order phase of output data Symbol.For example, first (or 5th) data (the hereinafter referred to as initial data) exported in response to order is always at transmission letter The output of number time point that CK0 is activated.Therefore, the time point output that initial data is activated at transmission signal CK0.
DDR4 semiconductor storage unit uses the burst-length (BL) of 10 bits, and wherein ten bits of data are disposably gone here and there Export capablely, therefore in parallel to serial convertor, to perform 10:1 parallel to serial conversion.Here, clock is divided into 2N Individual transmission signal.Therefore, transmission signal CK0, CK1, CK2 and CK3 of utilizing clock CLK to produce can be used in 10:1 parallel to string In row conversion.
Fig. 2 is to be shown through use by transmission signal CK0, CK1, CK2 and CK3 of clock CLK generation by also line number According to ten bits switch become the sequential chart of operation of serial data.
During exporting data in response to the first order, initial data D0 is directed at transmission signal CK0 and is passed Deliver to output lead S.In response to the second order during exporting data, initial data D0 ' with transmit signal CK2 be directed at and It is transferred into output lead S.
It is to say, the transmission signal that initial data is sent to line S is periodically variable.Therefore, in the ten of data In the case of individual bit response exports continuously in the order of input continuously, transmit the transmission signal of initial data the most continuously Change.If in integrated circuit implement for this scheme parallel to serial conversion circuit, then may increase its complexity.Separately Outward, if integrated circuit utilizes the 8 bits parallel to serial conversion circuit output data, and parallel to serial conversion electricity Perform additional functionality in road, then the complexity parallel to serial conversion circuit increases exponential.Result is, integrated circuit institute The area occupied and complexity also increase exponential.
Summary of the invention
The exemplary embodiment of the present invention relates to a kind of parallel to serial conversion circuit, and its utilization simply configures multiple Data perform parallel to serial conversion, and the quantity of the multiple data exported in individual command with adaptive response is for 2NSituation, And the quantity of the multiple data exported in response to individual command is not 2NSituation.
According to one exemplary embodiment of the present invention, a kind of integrated circuit includes: multiple data wires, by multiple pulses The data of signal alignment are loaded on the plurality of data wire;Multiple transmission lines;Data transfer unit, described data transfer unit It is configured to respond to coherent signal and the data of the plurality of data wire are sent to the plurality of transmission line;Data output is single Unit, the transmission signal that described data outputting unit is configured to export be activated among the plurality of transmission signal is corresponding The data of transmission line;Coherent signal generating unit, described coherent signal generating unit is configured as order input to relevant letter Utilize the logical value of one of latent time value and the plurality of transmission signal to produce coherent signal during number generating unit;And Pulse signal generating unit, described pulse signal generating unit is configured as during order input sequentially activating the plurality of arteries and veins Rush signal.
According to another exemplary embodiment of the present invention, a kind of integrated circuit includes: multiple data wires;Multiple transmission Line;Data transfer unit, described data transfer unit is configured to respond to coherent signal and by the number of the plurality of data wire According to being sent to the plurality of transmission line;Data outputting unit, described data outputting unit is configured to output and the plurality of biography The data transmitting the corresponding transmission line of signal being activated among defeated signal;And coherent signal generating unit, described relevant Signal generating unit utilizes latent time value and the plurality of when being configured as order input to coherent signal generating unit The logical value of one of transmission signal produces coherent signal.
Accompanying drawing explanation
Fig. 1 is the sequential chart illustrating the operation that four parallel datas are converted into serial data.
Fig. 2 is to be shown through use by transmission signal CK0, CK1, CK2 and CK3 of clock CLK generation by also line number According to ten bits switch become the sequential chart of operation of serial data.
Fig. 3 is the configuration figure of the integrated circuit according to one exemplary embodiment of the present invention.
Fig. 4 is the configuration figure of pulse signal generating unit 340 and data stick unit 350.
Fig. 5 A and Fig. 5 B is to illustrate the oscillogram of the operation of integrated circuit when burst-length is 10 (the second operator scheme).
Fig. 6 is to illustrate the oscillogram of the operation of integrated circuit when burst-length is 8 (the first operator scheme).
Fig. 7 is the simplified block diagram of an example electronic system of the integrated circuit including the present invention.
Detailed description of the invention
It is described more fully the exemplary embodiment of the present invention below with reference to accompanying drawings.But, the present invention can be with not Same mode is implemented, and should not be construed as limited to embodiments set forth herein.Exactly, it is provided that these are implemented Example is to make this specification understand and completely, and will pass on the scope of the present invention completely to those skilled in the art.? In this specification, identical reference represents identical parts in each drawings and Examples of the present invention.
Fig. 3 is the configuration figure of integrated circuit according to an illustrative embodiment of the invention.
Seeing Fig. 3, described integrated circuit includes: multiple data wire A0 to A3, B0 and B1, multiple transmission line C0 to C3, number According to delivery unit 320, data outputting unit 330, coherent signal generating unit 310 and pulse signal generating unit 340.Data It is loaded on multiple data wire A0 to A3, B0 and B1 in response to multiple pulse signal P0 to P4.Data transfer unit 320 basis Coherent signal MAT and the data of data wire A0 to A3, B0 and B1 are sent to multiple transmission line C0 to C3.Data outputting unit The data of the transmission line that 330 outputs are corresponding with the transmission signal being activated in multiple transmission signal CK0 to CK3.Coherent signal Generating unit 310 utilizes the biography in multiple transmission signal CK0 to CK3 when ordering CMD input to coherent signal generating unit 310 Logical value and the latent time value of defeated signal CK0 produce coherent signal MAT.Pulse signal generating unit 340 is at order CMD Multiple pulse signal P0 to P4 is sequentially activated when input is to pulse signal generating unit 340.It addition, described integrated circuit includes Data stick unit 350, data stick unit 350 be aligned in response to multiple pulse signal P0 to P4 at data D0 to D9 and Data are retained when being loaded on multiple data wire A0 to A3, B0 and B1.
The plurality of data wire A0 to A3, B0 and B1 include multiple first kind data wire A0 to A3, and one or more Multiple Second Type data wire B0 and B1.The plurality of pulse signal P0 to P4 includes and the plurality of first kind data wire A0 To multiple first pulse signal P0 to P3 that A3 is corresponding, and with one or more Second Type data wire B0 and B1 Corresponding one or more second pulse signal P4.
Fig. 3 illustrates that the quantity of first kind data wire A0 to A3 is four, and the quantity of transmission line C0 to C3 is four, and Equations of The Second Kind The situation that quantity is two of type data wire B0 and B1.These quantity can change according to the varying environment of the circuit of enforcement Fig. 3.
The operation of integrated circuit is described hereinafter with reference to Fig. 3.
It is not 2 that one exemplary embodiment of the present invention can apply to the number of signals in response to individual command outputN Integrated circuit.For purposes of illustration, integrated circuit will be illustratively described be memory device and perform data output operation Situation, wherein (it is for being not equal to 2 for a length of 10 bits of data burstNNumber, wherein N is natural number).Herein, the ten of data The data D0 to D7 (hereinafter referred to first kind data) transmitted by first kind data wire A0 to A3 among individual bit is right The data of Ying Yucong memory element output, and data D8 and the D9 that are transmitted by Second Type data wire B0 and B1 (are hereinafter referred to as For Second Type data) corresponding to cyclic redundancy check (CRC) (CRC) data, described cyclic redundancy check (CRC) (CRC) data represent the The error check result of one categorical data D0 to D7.But, the invention is not limited in exemplary embodiments mentioned above.
When ordering CMD input to integrated circuit (hereinafter memory device), start defeated after in the past at latent time Go out data.Order CMD is the order for data output.Latent time is to light to data D0 from the time of input order CMD Time to the time point that D9 exports via data outputting unit 330.Said integrated circuit can be memory device.In this situation Under, order CMD is the signal corresponding with reading order, and latent time is CAS latent time (CL).
Whenever exporting data in response to order CMD, input order CMD.Input order CMD is so that continuously continuously Ground exports multiple data, and this operation may be constructed the general operation of memory device.When burst-length is 10, every five clocks are defeated Enter a subcommand CMD, and when burst-length is 8, every four clocks input a subcommand CMD.This is because CAS to CAS prolongs (tCCD) changes according to burst-length late.TCCD is that the next column after the row access of a certain memory bank accesses The little time.
The data bulk exported in response to order CMD is 2NOperator scheme be referred to as the first operator scheme, in response to Order CMD and the data bulk that exports is not 2NOperator scheme be referred to as the second operator scheme.Therefore, it is 8 when burst-length Time memory device operate in the first mode of operation, when burst-length is 10, memory device operates in the second mode of operation.
(1) the memory device situation that (such as, burst-length=10) operate in the second mode of operation
In the case of memory device operates in the second mode of operation, if with K order CMD (wherein K is natural number) The time point output that the first corresponding output data D0 (hereinafter " initial data ") is activated at CK0, then with (K+1) The time point output that initial data D0 corresponding for order CMD is activated at CK2.In this second mode of operation, initial data D0 Output time point constantly change.For example, if the time point output that the first initial data D0 activates at CK0, then next The time point output that initial data D0 activates at CK2., then the time point output that activates at CK0 of next initial data D0 then.
When burst-length is 10, every five clocks input a subcommand CMD.As input order CMD, from memory element The data D0 to D7 (hereinafter exporting data) of output is aligned and is loaded on first kind data wire A0 to A3.CRC number Aligned according to D8 and D9 and be loaded on Second Type data wire B0 and B1.Here, first kind data D0 to D7 becomes output Data, Second Type data D8 and D9 become CRC data.Second Type data D8 and D9 can also be non-CRC data, and permissible Represent except being loaded into 2 on first kind data wire A0 to A3NThe number outer data added according to this.Second Type data D8 and D9 can be loaded on Second Type data wire B0 and B1.
The execution of data loading operations is as follows.The data that data stick unit 350 is inputted when retaining order CMD input, Wherein data retention time is five clocks, and this is equal to order input interval.Pulse signal generating unit 340 is in order Multiple pulse signal P0 to P4 is produced during CMD input.Specifically, when burst-length is 10, multiple first pulse signal P0 are extremely P3 is activated, and then one or more second pulse signal P4 is activated.Pulse signal P0 is swashed when ordering CMD input Live, and to have be the pulse width of 2 clocks.Pulse signal P1 to P4 is respectively by P0 is postponed 1 to 4 clock (CLK) And produce.Pulse signal generating unit 340 sequentially activates multiple pulse signal P0 to P4.Now, when again inputting order During CMD, pulse signal generating unit 340 resets, and the order repeating the plurality of pulse signal produces.
The data D0 to D9 retained by data stick unit 350 is via with door X1 to X10 together with multiple pulse signal P0 extremely Pulse signal corresponding with data D0 to D9 among P4 and be loaded on data wire A0 to A3, B0 and B1.Pulse signal P0 is extremely P4 sequentially activates in constant interval.For example, D0 at X1 with P0 combine, and via or door Y1 be sent to data wire A0. Therefore, D0 was loaded on data wire A1 during the activation cycle of P0.Now, the activationary time point of pulse signal P0 to P4 is not With.Due to this difference, data D0 to D9 is aligned and is loaded on multiple data wire A0 to A3, B0 and B1.
It is loaded into multiple at first kind data D0 to D7 (output data) by multiple first pulse signal P0 to P3 After first kind data wire A0 to A3 is upper, Second Type data D8 and D9 (CRC data) are in response to one or more pulse Signal P4 and be loaded on one or more Second Type data wire B0 and B1.
Data transfer unit 320 will be loaded on multiple data wire A0 to A3, B0 and B1 in response to coherent signal MAT Data are sent to multiple transmission line C0 to C3.
Data outputting unit 330 is by the transmission line corresponding with the transmission signal being activated among transmission signal CK0 to CK3 Data output to output lead S.In figure 3, transmission line C0, C1, C2 and C3 respectively with transmission signal CK0, CK1, CK2 and CK3 Corresponding.For purposes of illustration, the plurality of transmission signal CK0 to CK3 utilizes clock CLK to produce, and with CK0, The reiteration of CK1, CK2 and CK3 is activated.The quantity of transmission signal can change according to the quantity of transmission line.Hereinafter, Clock CLK is referred to as data output clock, and it is also referred to as DQS.
By changing the dependency relation between multiple data wire A0 to A3, B0 and B1 and multiple transmission line C0 to C3, even if Also data output operation is performed when burst-length is 10.Even if when initial data D0 is always loaded on A0, it is also possible to substitute Property ground change into C0 or C2 by the transmission line of the data by being used for A0 and perform intended operation.This is because transmission line C0 The time point output that data are activated at transmission signal CK0, and the time point output that the data of C2 are activated at CK2.
To this end, when coherent signal MAT is activated, data transfer unit 320 will be loaded into multiple first kind data wire The data on first data wire A0 in A0 to A3 are sent among multiple transmission line C0 to C3 activate transmission signal with first Transmission line C0 corresponding for CK0.When coherent signal MAT is deactivated, data transfer unit 320 will be loaded into first kind number It is sent to multiple biography according to the data on line A2 (first data wire A0 in its most multiple first kind data wire A0 to A3) Transmission line C0 corresponding with CK0 among defeated line C0 to C3.
For the data with correct other data wire of Sequential output, these data to be passed in response to coherent signal MAT Deliver to transmission line.Specifically, after the data of first kind data wire A0 to A3 are sent to multiple transmission line C0 to C3, second The data of categorical data line B0 and B1 are sent to one or more transmission line chosen by coherent signal MAT.
In figure 3, when coherent signal MAT is activated, the data of B0 and B1 are respectively transmitted to C0 and C1.When relevant letter When number MAT is deactivated, the data of B0 and B1 are respectively transmitted to C2 and C3.
I.e., in figure 3, when coherent signal MAT is activated, the data of A0, A1, A2 and A3 be respectively transmitted to C0, C1, C2 and C3, then the data of B0 and B1 are respectively transmitted to C0 and C1.When coherent signal MAT is deactivated, A0, A1, A2 and The data of A3 are respectively transmitted to C2, C3, C0 and C1, and then the data of B0 and B1 are respectively transmitted to C2 and C3.
As reference, the configuration of data transfer unit 320 explained below and operation.When multiple pulse P0 to P4 are activated Time, multiple data D0 to D9 are loaded into multiple first number with door X1 to X10 and multiple first or door Y1 to Y4 by multiple first According on line A0 to A3 and the second data wire B0 and B1.Multiple multiplexer L1 to L4 select defeated in response to coherent signal MAT Enter to its first data wire.Multiple second selects transmission line C0 with door K1 to K4 in response to coherent signal MAT To C3 two are for receiving the signal on multiple second data wire B0 and B1.Multiple or door M1 to M4 is by the first data wire A0 Data to A3 and the second data wire B0 and B1 are sent to multiple transmission line C0 to C3.The above-mentioned configuration of data transfer unit 320 Being only exemplary, other configuration being rationally suitable for any can also be used for performing aforesaid operations.
As input order CMD, coherent signal generating unit 310 utilizes latent time value CL and multiple transmission signal The logical value of one of CK0 to CK3 produces coherent signal MAT, although shown in Fig. 3 be first activation transmission signal CK0 make For input.More specifically, when with binary notation represent transmission signal CK0 value and to order CMD input relevant Latent time value CL time, coherent signal MAT become by by the lowest order CL of latent time with transmission signal CK0 value carry out (when the odd-multiple that latent time value CL is clock, last position of latent time value CL is the result that logical combination is obtained “1”;When the even-multiple that latent time value CL is clock, last position of latent time value is " 0 ").
The activation of transmission signal CK0 is spaced apart 2 clocks (for the even-multiple of clock), and is swashed at transmission signal CK0 After work, it spends 1 clock (for the odd-multiple of clock CLK), until transmission signal CK2 is activated.Therefore, when input order Transmit signal CK0 during CMD to be activated (that is, logical value is 1), and when the odd-multiple that latent time value CL is clock (that is, is hidden Last value of time value CL is 0) time coherent signal MAT be activated.Order every five clocks of CMD are activated once.Cause This, when subsequent command CMD is activated, transmission signal CK0 be in deactivation status (that is, transmission signal CK0 last Logical value is 0), and coherent signal MAT is because last value of latent time value CL is 0 to be deactivated.
If using CK0 value and latent time value CL relevant with input order CMD to produce phase as described above OFF signal MAT, then, in the case of burst-length is 10, all can change the shape of coherent signal MAT whenever input order CMD State.Therefore, the activationary time point that the output time point of initial data D0 can be changed into CK0 or CK2 is corresponding.
Aforesaid operations is equally applicable to the situation of the odd-multiple (CL value is 1) that latent time value is clock.Real according to another Example, transmission signal CK2 can serve as producing the transmission signal of coherent signal MAT, although being illustrated that d type flip flop 311 receives CK0 Logical value and be configured as input order CMD time store described value.XOR gate 312 is to the output of d type flip flop 311 and latent Last place value CL of volt time (CL) performs XOR, to produce coherent signal MAT.
Some transmission lines (such as, C1 and C3 in Fig. 3) in multiple transmission line C0 to C3 have specific length of delay (example As, 0.5 clock).When data outputting unit 330 by the data that receive with corresponding to its transmission signal (in CK0 to CK3 One) on time, all data exported therefrom all have the front surplus of 1 clock and the rear remaining of 0.5 clock (CLK) Amount.But, such delay is optional.
(2) the memory device situation that (that is, burst-length=8) operate in the first mode of operation
In the case of memory device operates in the first mode of operation, initial data D0 can always CK0 (or CK2) swash Live time point exports.When burst-length is 8, every four clocks input a subcommand CMD.Therefore, even if inputting life continuously Making CMD, CK0 value during input order CMD is the most constant is " 1 " or constant be " 0 ", this is because transmit between the activation of signal CK0 It is divided into 2 clocks (CLK).Therefore, it is output as state of activation the state constant of coherent signal MAT, or is output as consistently State of activation.
In the first mode of operation, when exporting initial data D0 at the activationary time point of CK0, initial data D0 always exists The activationary time point output of CK0.When exporting initial data D0 at the activationary time point of CK2, initial data D0 always swashing at CK2 Live time point exports.
In response to coherent signal MAT activation multiple first kind data wire A0 to A3 and multiple transmission line C0 to C3 it Between dependency relation identical with the situation of the second operator scheme.But, in the first mode of operation, do not have data to be transferred into biography Defeated line C0 to C3, because not having data to be loaded on B0 and B1.
As input order CMD, the data D0 to D7 only exported from the memory element of memory device is (the most defeated Go out data) aligned and be loaded on first kind data wire A0 to A3.In the above-described example, the first operator scheme may correspond to Do not produce the operator scheme of CRC data D8 and D9.
Owing to not producing CRC data D8 and D9 (that is, Second Type data), there is no need for loading CRC data One or more second pulse signal P4 on one or more Second Type data wire B0 and B1.Therefore, pulse letter Number generating unit 340 sequentially activates multiple first pulse signal P0 to P3, and does not activate one or more second pulse letter Number P4.As input order CMD, P0 to P3 is sequentially activated.With the second operator scheme by contrast, every due to order CMD Four clocks (CLK) are activated once, and therefore after input order CMD, P0 to P3 is sequentially activated, and order CMD is at P4 Activation before and without again inputting in the case of any activation of P4.Then, pulse signal generating unit 340 is again Sequentially activate P0 to P3.
The operation of data outputting unit 330 is substantially the same with the second operator scheme.
Even if when the number of signals exported in response to individual command CMD is not 2NTime, it is also possible to by proper use of Produced by clock CLK 2NIndividual transmission signal CK0 to CK4 exports described signal.According to an exemplary embodiment, can use It is 2 that simple configuration carrys out the number of signals that adaptive response exports in individual command CMDNSituation, and in response to single life The number of signals making CMD and export is not 2NSituation.In either case, when performing continuous output signal or the operation of data Time, the interval being transfused to the order CMD of signal or data output and the number of signals exported in response to individual command CMD Relevant.Herein, the order input interval in the example of Fig. 3 is determined by burst-length.
The exemplary embodiment of the present invention provides a kind of integrated circuit, transmission signal when it adjusts initial data D0 output The activationary time point of CK0 or CK2.Such adjustment is by using latent time value CL and transmission when input order CMD The logical value of signal CK0 and what the control signal (corresponding to coherent signal MAT) that produces performed.
In figure 3, pulse signal generating unit 340 is configured to produce for data D0 making data stick unit 350 Pulse to D9 alignment.Therefore, when only considering the output of aligned data, according to one exemplary embodiment of the present invention Integrated circuit can include that multiple transmission line C0 to C3, data transfer unit 320, data outputting unit 330, coherent signal are sent out Raw unit 310 and pulse signal generating unit 340.Data transfer unit 320 is closed according to corresponding defined in coherent signal MAT It is and the data being loaded on multiple data wire A0 to A4, B0 and B1 are sent to multiple transmission line C0 to C3.Data output is single The data of the transmission line that unit 330 output is corresponding with the transmission signal being activated among transmission signal CK0 to CK3.Relevant letter Number generating unit 310 utilizes in multiple transmission signal CK0 to CK3 when ordering CMD input to coherent signal generating unit 310 Logical value and the latent time value of transmission signal CK0 produce coherent signal MAT.Pulse signal generating unit 340 is in order Multiple pulse signal P0 to P4 is sequentially activated when CMD input is to pulse signal generating unit 340.
It addition, integrated circuit can include that multiple transmission line C0 to C3, data pass according to an exemplary embodiment of the present invention Send unit 320, data outputting unit 330, coherent signal generating unit 310 and pulse signal generating unit 340.Data transmission The data transmission that unit 320 will be loaded on multiple data wire A0 to A4 according to corresponding relation defined in coherent signal MAT To multiple transmission line C0 to C3.The transmission signal being activated among data outputting unit 330 output and transmission signal CK0 to CK3 The data of corresponding transmission line.Coherent signal generating unit 310 is when ordering CMD input to coherent signal generating unit 310 Utilize the logical value of transmission signal CK0 in multiple transmission signal CK0 to CK3 and latent time value to produce coherent signal MAT. Pulse signal generating unit 340 sequentially activates multiple pulse letter when by order CMD input to pulse signal generating unit 340 Number P0 to P3.
Fig. 4 is the configuration figure of pulse signal generating unit 340 and data stick unit 350.
In the case of integrated circuit is memory device, with reference to Fig. 4, pulse signal generating unit 340 and data will be described The configuration of stick unit 350 and operation.
Pulse signal generating unit 340 includes multiple d type flip flop 341 to 347 and multiple or door A1 to A5.The life of input Make CMD Tong Bu with clock CLK by means of d type flip flop 341, and by means of d type flip flop 342 to the 345 (output of d type flip flop 346 There is the output identical with d type flip flop 345 and phase place) and d type flip flop 347 postpone 1 clock (CLK).Owing to order CMD is sharp The cycle of living is the pulse signal of 1 clock, thus the output of d type flip flop 342 to 345 (output of d type flip flop 346 has and D triggers Output that device 345 is identical and phase place) it is that phase contrast is 1 clock and activation cycle is 1 respectively with the output of d type flip flop 347 The pulse signal of clock.(output of d type flip flop 346 has can to combine d type flip flop 342 to 345 by utilization or door A1 to A5 Have the output identical with d type flip flop 345 and phase place) the output d type flip flop adjacent with among the output of d type flip flop 347 defeated Out produce multiple pulse signal P0 to P4.As reference, reason Tong Bu with clock CLK for order CMD is that order CMD is Tong Bu with system clock (not shown) rather than with clock CLK synchronize.In the situation that order CMD is Tong Bu with clock CLK Under, pulse signal generating unit 340 can not include d type flip flop 341.
D type flip flop 341 to 345 is configured to produce multiple first pulse signal P0 to P3, and d type flip flop 346 and 347 is joined It is set to produce one or more second pulse signal P4.Regardless of the operator scheme of integrated circuit, d type flip flop 341 to 345 The most sequentially activate the plurality of first pulse signal P0 to P3.
As input order CMD, d type flip flop 346 resets.Now, d type flip flop 346 and 347 triggers from D by receiving The delayed output signal of device 344 and postpone to export its corresponding output signal.Owing to d type flip flop 347 postpones d type flip flop The output of 346, therefore when d type flip flop 346 resets, d type flip flop 347 does not produce the pulse signal of delay.
In the case of integrated circuit operates in the second mode of operation, owing to every five clocks input a subcommand CMD, because of This d type flip flop 346 and 347 is activated at the first pulse signal P0 to P3 and activates the second pulse signal P4 afterwards.
In the case of integrated circuit operates in the first mode of operation, owing to every four clocks input a subcommand CMD, because of This order CMD inputs after the first pulse signal P0 to P3 is activated again.Therefore, export by postponing at d type flip flop 346 Before signal produced by the output of d type flip flop 344, the reset of the order CMD input Tong Bu with clock CLK to d type flip flop 346 Terminal, thus resets d type flip flop 346.Accordingly, because d type flip flop 346 and 347 postpones 1 clock and 2 clocks further The output signal of output d type flip flop 344, therefore the second pulse signal P4 is not activated.
For purpose of explanation, not shown d type flip flop 341 to 345 and the reseting terminal of 347, this is because at integrated circuit Operation during d type flip flop 341 to 345 and 347 be not reset, therefore its reseting terminal RST be prohibited enable (that is, integrated During the operation of circuit, d type flip flop 341 to 345 and 347 is not reset).
Data stick unit 350 includes storage element 351 and CRC processing unit 352.
As input order CMD, storage element 351 stores data DATA<0:7>from memory element output.Storage element 351 retain the data stored until subsequent command CMD inputs, and update the data stored when described subsequent command CMD inputs. CRC processing unit 352 is by checking that the mistake of data DATA<0:7>produces CRC data D8 and D9.According to an example, CRC Data D8 and D9 are postponed by error-correction operations, and the phase place of CRC data D8 and D9 lags behind the phase place 2 of data DATA<0:7> To 3 clocks (CLK).As discussed above concerning described by Fig. 3, data stick unit 350 retains data D0 to D9 until data D0 It is aligned and is loaded into D9 by multiple pulse signal P0 to P4 on data wire A0 to A3, B0 and B1.
Fig. 5 A and Fig. 5 B is to illustrate the waveform of the operation of (that is, the second operator scheme) integrated circuit when burst-length is 10 Figure.
Fig. 5 A is shown in the activationary time point output of transmission signal CK0 and orders initial number corresponding for CMD with the first input Operation according to D0.
In this second mode of operation, every five clocks input a subcommand CMD.First kind data D0 to D7 (that is, output Data) light to the time point of subsequent command CMD input retained from the time of order CMD input.Second Type data D8 and D9 (that is, CRC data) has the retention periods identical with first kind data D0 to D7, but due to prolonging that CRC operation is caused Late, the retention periods of Second Type data D8 and D9 lags behind 2 clocks of retention periods of first kind data D0 to D7.
In this second mode of operation, as input order CMD, pulse signal P0 to P4 is sequentially activated.As joined above According to described by Fig. 4, multiple pulse signal P0 to P4 are by carrying out by signal produced by order CMD delay constant interval Combine and produce.Now, D0 to D7 is loaded into multiple during the activation cycle of multiple first pulse signal P0 to P3 On one categorical data line A0 to A3, and D8 and D9 was loaded during the activation cycle of one or more second pulse signal P4 To or one or more Second Type data wire B0 and B1 on.Although data D0 to D7, D8 and D9 being shown as on sequential chart The group of D0-D7 and the group of D8, D9, but data D0 to D7, D8 and D9 can be loaded into different data wire A0 to A3 and On B0 and B1, even if they have identical activation cycle for each group.
Herein, owing to coherent signal MAT is active, therefore the data of data wire A0, A1, A2 and A3 are passed respectively Deliver to C0, C1, C2 and C3.It addition, the data at multiple first kind data wire A0 to A3 are loaded into multiple transmission line C0 extremely After C3 is upper, data D8 and the D9 of multiple Second Type data wire B0 and B1 are loaded into the transmission chosen by coherent signal MAT On line C0 and C1.
Meanwhile, the data being loaded on the second transmission line C1 and the 4th transmission line C3 are delayed by 0.5 clock (CLK).Figure 5A illustrates the waveform of the length of delay reflecting transmission line C1 and C3.The data of multiple transmission line C0 to C3 are at data outputting unit Sequentially it is directed in 330, and exports to output lead S.
The operation relevant with Fig. 5 B explained below is partially illustrated by what dotted line indicated.
Fig. 5 B is shown in the life inputted after the input of the activationary time point output of CK2 and the previous order CMD of Fig. 5 A Make the operation of initial data D0 (that is, D0 ') corresponding for CMD.
D0 ' to D7 ' is loaded into the operation on multiple first kind data wire A0 to A3, and D8 ' and D9 ' is loaded into one or more Operation on multiple Second Type data wire B0 and B1, and produce the operation of multiple pulse signal P0 to P4 and the operation of Fig. 5 A It is substantially the same.
Owing to coherent signal MAT is in deactivation status, therefore the data of A0, A1, A2 and A3 be respectively sent to C2, C3, C0 and C1.It addition, after the data of multiple first kind data wire A0 to A3 are loaded on multiple transmission line C0 to C3, multiple Data D8 of data wire B0 and B1 of Second Type ' and D9 ' be loaded on transmission line C2 and C3 chosen by coherent signal MAT.
0.5 clock (CLK) of data delay being loaded on the second transmission line C1 and the 4th transmission line C3.Fig. 5 B illustrates instead Mirror the waveform during length of delay of transmission line C0 to C3.The data of multiple transmission line C0 to C3 are suitable in data outputting unit 330 It is directed at secondaryly and exports to output lead S.
The operation relevant with Fig. 5 A is partially illustrated by what dotted line indicated.
It is repeated in Fig. 5 A and the aforesaid operations of Fig. 5 B afterwards.Operate through these, the most when commands are entered, the ten of data Individual bit is output as one group.
Fig. 6 is to illustrate the oscillogram of the operation of integrated circuit when burst-length is 8 (that is, the first operator scheme).
In the first mode of operation, every four clocks input a subcommand CMD.D0 is extremely for first kind data (output data) D7 lights to the time point of subsequent command CMD input retained from the time of order CMD input.In the first mode of operation, no Produce Second Type data (CRC data) D8 and D9.
In the first mode of operation, as input order CMD, P0 to P3 is sequentially activated.Retouched as discussed above concerning Fig. 5 Stating, multiple first pulse signal P0 to P3 are by being combined by signal produced by order CMD delay constant interval And obtain.Now, instead of before one or more second pulse signal P4 is activated, inputs order CMD, described one Individual or more second pulse signal P4 are not activated, and multiple first pulse signal P0 to P3 is sequentially activated.This Time, D0 to D7 was loaded on multiple first kind data wire A0 to A3 in the activation cycle of multiple first pulse signal P0 to P3. Although being shown as D0 to D7 forming a group, even if they have identical activation cycle also can be loaded into different lines On.
In figure 6, when coherent signal MAT is active, the data of A0, A1, A2 and A3 be respectively sent to C0, C1, C2 and C3.Such dependency relation can constantly maintain.If coherent signal MAT is in deactivation status, A0, A1, A2 and The data of A3 are respectively sent to C2, C3, C0 and C1.Such dependency relation can constantly maintain.
Compared with the data division being loaded on transmission line C0 and C1, it is loaded into and is not initially chosen by coherent signal MAT 0.5 clock (CLK) of data delay on transmission line C2 and C3 is selected.Fig. 6 illustrates and reflects prolonging of transmission line C0 to C3 Waveform during value late.The data of multiple transmission line C0 to C3 are directed at serially in data outputting unit 330 and export to output Line S.
Repeat Fig. 5 A and the aforesaid operations of Fig. 5 B afterwards.Operated by these, the most when commands are entered, eight ratios of data Spy is outputted as one group.When burst-length is 8, the output initial data D0 when transmitting signal CK0 (or CK2) and being activated.
Fig. 7 is the simplified block diagram of an example electronic system of the integrated circuit including the present invention.
Seeing Fig. 7, electronic system 700 can correspond to computer system, Process Control System or other use any Include the processor of integrated circuit of the present invention and the system of relational storage.
Electronic system 700 can include processor or arithmetic/logic unit (ALU) 702, control unit 704, memory device Unit 706 and input/output (I/O) device 708.
Electronic system 700 by have specifically note will by the processor 702 native instruction set to the operation that data perform, with And other between processor 702, memory device unit 706 and I/O device 708 is mutual.
Control unit 704 controls processor 702, memory device unit by circulating continuously via the set of operation The all operations of 706 and I/O devices 708, the set of described operation causes from memory device 706 acquisition instruction and performs instruction. In various embodiments, memory device unit 706 include random access memory (RAM) device, read-only storage (ROM) device and Peripheral components, such as floppy disk and compact disk CD-ROM drive.
According to the exemplary embodiment of the present invention, use the latent time value specified and the logical value of transmission signal, really Making transmission signal, the first data are in response to described transmission signal and export.
According to an exemplary embodiment, the quantity in the multiple data exported in response to individual command is 2NSituation And the quantity of the multiple data exported in response to individual command is not 2NIn the case of, use relatively simple configuration and The control parallel to serial conversion to multiple data can be appropriately carried out while control.
Although having been incorporated with specific embodiment to describe the present invention, but it should be apparent to those skilled in the art that Be, in the case of the spirit and scope of the invention limited without departing from claims, can carry out various amendment and Modification.

Claims (23)

1. an integrated circuit, including:
Multiple data wires, the data being directed at by multiple pulse signals are loaded on the plurality of data wire;
Multiple transmission lines;
Data transfer unit, described data transfer unit is configured to respond to coherent signal and by the number of the plurality of data wire According to being sent to the plurality of transmission line;
Data outputting unit, described data outputting unit is configured to the transmission letter being activated among output and multiple transmission signals The data of number corresponding transmission line;
Coherent signal generating unit, described coherent signal generating unit is configured as order input and occurs to described coherent signal Utilize the logical value of one of latent time value and the plurality of transmission signal to produce coherent signal during unit;And
Pulse signal generating unit, described pulse signal generating unit is configured to the most sequentially to activate described many Individual pulse signal.
2. integrated circuit as claimed in claim 1, wherein said multiple data wires include multiple first kind data wire and One or more Second Type data wire, and the plurality of pulse signal includes and the plurality of first kind data wire phase Corresponding multiple first pulse signals, and corresponding with one or more Second Type data wire one or more Individual second pulse signal.
3. integrated circuit as claimed in claim 2, wherein said integrated circuit has two operator schemes, and N is natural number, rings Order the quantity of the data exported by described integrated circuit equal to 2 described in Ying YuNOperator scheme be said two operator scheme In the first operator scheme, the quantity of the data exported by described integrated circuit in response to described order is not equal to 2NOperation mould Formula is the second operator scheme in said two operator scheme.
4. integrated circuit as claimed in claim 3, wherein, in described first operator scheme, described pulse signal occurs single Unit is configured to sequentially activate one or more first pulse signal and deexcitation one or more second Pulse signal, in described second operator scheme, described pulse signal generating unit is configured to sequentially activate one Or more first pulse signal and sequentially activate one or more second pulse signal.
5. integrated circuit as claimed in claim 1, wherein, believes in response to the corresponding pulse in the plurality of pulse signal Number, the data of the plurality of data wire through with door being loaded on the plurality of data wire.
6. integrated circuit as claimed in claim 3, wherein, in described first operator scheme, aligned data are loaded into It is not added with being downloaded on one or more Second Type data wire, described second on the plurality of first kind data wire In operator scheme, aligned data are loaded into the plurality of first kind data wire and one or more Equations of The Second Kind On type data wire.
7. integrated circuit as claimed in claim 1, wherein said order is the order for data output, and whenever to ring When order exports the data of respective numbers described in Ying Yu, input described order.
8. integrated circuit as claimed in claim 1, a part for wherein said multiple transmission lines is configured to delay and is sent to Its data.
9. integrated circuit as claimed in claim 1, wherein said latent time value represents from described order input to described phase The time point of OFF signal generating unit to described data outputting unit starts to export the time of the time point of data.
10. integrated circuit as claimed in claim 3, wherein said coherent signal generating unit is configured as the plurality of biography Defeated signal utilizes the first activation transmission letter in described latent time value and the plurality of transmission signal when being sequentially activated Number logical value produce described coherent signal.
11. integrated circuits as claimed in claim 10, wherein, when described coherent signal is activated, described data transmit single The data that unit is configured on first data wire will being loaded in the plurality of first kind data wire are sent to described many Individual transmission line activates the transmission line that transmission signal is corresponding with described first, when described coherent signal is deactivated, described The data that data transfer unit is configured on another data wire that will be loaded in described first kind data wire are sent to The plurality of transmission line activates the transmission line that transmission signal is corresponding with described first.
12. integrated circuits as claimed in claim 3, wherein, in described first operator scheme, described Second Type data wire Data be not transferred into the plurality of transmission line, in described second operator scheme, at the number of described first kind data wire After being sent to one or more transmission line of being chosen among the plurality of transmission line by described coherent signal, described second The data of categorical data line are transmitted.
13. integrated circuits as claimed in claim 2, are wherein loaded on one or more Second Type data wire Data are cyclic redundancy check data, and described cyclic redundancy check data is to being loaded into one or the more first kind The error check result of the data on data wire.
14. integrated circuits as claimed in claim 1, wherein said data transfer unit include with in the plurality of data wire At least one multiplexer that two data wires couple, for selecting one of two data wires to be loaded into selected number with output According to the data on line;And first gate, described first gate is coupled to receive at least one multiplexer described Output and be loaded in the plurality of data wire and be different from the data on the 3rd data wire of said two data wire.
15. integrated circuits as claimed in claim 14, also include that the second gate, described second gate are configured to receive Described coherent signal and the data of described 3rd data wire, at least one multiplexer wherein said is configured to receive institute Stating coherent signal, described first gate is configured to receive the output of described second gate.
16. integrated circuits as claimed in claim 1, wherein said data outputting unit is configured to receive the plurality of transmission Signal, and the data exporting the transmission line corresponding with the transmission signal activated in response to the transmission signal activated.
17. 1 kinds of integrated circuits, including:
Multiple data wires;
Multiple transmission lines;
Data transfer unit, described data transfer unit is configured to respond to coherent signal and by the number of the plurality of data wire According to being sent to the plurality of transmission line;
Data outputting unit, described data outputting unit is configured in output and multiple transmission signals the transmission signal being activated The data of corresponding transmission line;And
Coherent signal generating unit, described coherent signal generating unit is configured to occur to described coherent signal in order input The logical value of one of latent time value and the plurality of transmission signal is used to produce described coherent signal during unit.
18. integrated circuits as claimed in claim 17, wherein, believe in response to the corresponding pulse in the plurality of pulse signal Number, the data of the plurality of data wire through with door being loaded on the plurality of data wire.
19. integrated circuits as claimed in claim 17, wherein said order is the order for data output, and whenever wanting When exporting the data of respective numbers in response to described order, input described order.
20. integrated circuits as claimed in claim 17, a part for wherein said multiple transmission lines is configured to postpone to transmit Data to it.
21. integrated circuits as claimed in claim 17, wherein said latent time value represents from described order input to described The time point of coherent signal generating unit to described data outputting unit starts to export the time of the time point of data.
22. integrated circuits as claimed in claim 17, wherein said coherent signal generating unit is configured as the plurality of Transmission signal utilizes the first activation transmission in described latent time value and the plurality of transmission signal when being sequentially activated The logical value of signal produces described coherent signal.
23. integrated circuits as claimed in claim 22, wherein, when described coherent signal is activated, described data transmit single The data that unit is configured on first data wire will being loaded in the plurality of first kind data wire are sent to described many Individual transmission line activates the transmission line that transmission signal is corresponding with described first, when described coherent signal is deactivated, described The data that data transfer unit is configured on another data wire that will be loaded in described first kind data wire are sent to The plurality of transmission line activates the transmission line that transmission signal is corresponding with described first.
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1983228A (en) * 2005-12-12 2007-06-20 群康科技(深圳)有限公司 System for transmitting control signal by internal IC bus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1983228A (en) * 2005-12-12 2007-06-20 群康科技(深圳)有限公司 System for transmitting control signal by internal IC bus

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