CN115171601A - Display driving chip, display module and display screen control cascade method - Google Patents

Abstract

The invention relates to a display driving chip, a display module and a display screen control cascade method; the device comprises a clock input interface, a signal input interface, a command signal input interface, a clock output interface, a signal output interface and a command signal output interface; the invention integrates the functions of signal receiving, cascading, sending and the like by a chip, and cascades a plurality of chips in a serial mode, so that the PCB has simple wiring, the components of the system are greatly reduced, the internal functions of the chip can be controlled by only a plurality of signal wires, and the internal data of the chip is sent back to the host computer, and the signals are common digital logic signals; the CPU is easy to process and not easy to be interfered, thereby reducing the power consumption of the system and enabling the data interaction effect of the host and the slave to be more ideal.

Description

Display driving chip, display module and display screen control cascade method

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a display driving chip, a display module and a display screen control cascade method.

Background

In the electronic products applied in the world today, there are a large number of data interactions, and the completion of these data interactions requires the specification of corresponding data communication protocols. The existing communication protocols are various in types, wired and wireless; or short distance, medium distance, long distance; or low speed, medium speed, high speed, etc.; each protocol has a certain characteristic application scene, a relatively proper protocol is defined according to the scene, and a plurality of factors such as hardware cost, assembly and the like are also considered.

At present, the chip has higher and higher integration level and stronger functions, so that the data volume processed inside the chip is large, and the data volume interacted with the outside is also larger and larger. Like large-scale display screens (such as LED outdoor screens and mini display screens), images need to be displayed in real time, the refresh rate is high, and a single chip cannot control the display of the whole screen (as shown in FIG. 1).

At present, a single LED driving chip on the market can control 64 rows and 16 columns of dot matrixes, if one screen is 1024 dot matrixes, 1024 dots are needed for the whole display chip, and if signal lines of each chip are sent from a host, the single host cannot complete the processing, so that a plurality of hosts and other external chips are needed for assisting the processing. The optical touch screen (commonly called as an electronic whiteboard) is more and more popular in application at present, is more and more controlled and used in a large screen, gradually replaces the traditional blackboard in teaching, is also popular in meeting rooms, and is slowly extended to families. In order to achieve the effect of writing with a common soft pen, hundreds of pairs of LEDs and PDs are used on the whole set of touch screen, and the LEDs emit light and the PDs receive the light; the pen falling positions are judged by shielding light rays, the pen can be quickly captured during writing, and the refresh rate controlled by the whole screen is very high; resulting in a dramatic increase in the communication data between the host and the control chip. Since each chip controls multiple pairs (typically 8-16 pairs) of LEDs and PDs, the entire touch screen needs to have approximately 100 control chips.

Like the two applications that are referred to above require a large amount of data interaction, the display screen needs to refresh the display data in real time, and the electronic whiteboard needs to read the PD sensing data in real time, so that a communication interface protocol is needed to communicate the host and the control chip. The signal communication interfaces commonly used in the market at present are: I2C (two-wire serial) interface, SPI (serial peripheral) interface, LVDS (low voltage differential signaling) interface.

I2c (two-wire serial) interface;

as shown in fig. 3, the master controls a plurality of slaves, and since the I2C supports 127 addresses, the number of slaves can be 127 at most, but the whole touch screen control part is considered to be mounted around the whole screen, so that the signal line routing reaches more than 4 meters, and then the load of the signal line and the chip is considered, so that the data transmission speed of the I2C is very slow; because the interactive data volume is huge, the data volume of the control chip end is very large, and therefore the communication requirement cannot be met.

An SPI (Serial peripheral) interface;

as shown in fig. 4A, the master controls a plurality of slaves, and the slave is gated through the CS signal line of each slave, so that N slave will have N signal lines, and these signal lines all occupy the PCB routing space, thereby increasing the PCB layout difficulty; and a plurality of slaves are hung on the SCK and the SDIO buses, so that the data transmission speed is slow.

In order to increase the transmission speed, as shown in fig. 4B, a 245 (enhanced signal driver) chip is inserted in the middle of the signal trace, which can increase the speed of the host for downlink data, but the whole system control becomes complicated and the hardware cost is greatly increased, which cannot be realized if the data of the slave is to be transmitted back to the host.

Lvds (low voltage differential signaling) interface;

as shown in fig. 5A, the host and the multiple slaves communicate via LVDS interfaces, and since there are tens to thousands of control chips, the same number of LVDS interfaces is required, and since the LVDS interfaces are relatively complex and occupy a large area in a chip, it is impossible to integrate tens of LVDS interfaces on the host chip, and in addition, the LVDS transmission distance is short, and thus, the LVDS cannot be transmitted to all chips on the entire screen.

As shown in fig. 5B, the LVDS input and output interfaces are integrated in the control chip, so that the problem of data cascade can be solved, but the chip integrates the input and output interfaces, which greatly increases the difficulty of chip design, and the area occupied by the LVDS module in the chip is large, thereby increasing the cost of the chip; in addition, a plurality of LVDS signals are cascaded, and because the LVDS data transmission frequency is very high, in order to ensure that the control chip can accurately receive data, a crystal oscillator is required to be added, so that the peripheral cost of the chip is increased; the LVDS signal is weak, only a short distance can be transmitted, and if the distance is long, the driving capability needs to be increased, so that the power consumption of the chip is increased.

In summary, the following problems exist in the three schemes:

1. the communication speed cannot be reached by adopting an I2C or SPI interface.

2.LVDS scheme, the chip design is complicated, the chip cost is increased, and the number of peripheral devices is increased.

3. The communication protocol is complex, increasing the design and scheme debugging difficulty.

And 4, the PCB wiring is not optimized, and the PCB layout difficulty is increased.

5. The signal transmission driving strength is not large, and the system is easily interfered by random noise.

Disclosure of Invention

The technical problem to be solved by the invention is that in the three schemes, the problems of low communication speed, complex PCB layout, more peripheral devices, higher system power consumption, easy interference and the like exist. In order to solve these problems, a communication protocol needs to be redefined, one chip is integrated with the functions of signal receiving, cascading, sending and the like, and a method for realizing serial cascading is used to cascade a plurality of chips.

The technical scheme adopted by the invention for solving the technical problems is as follows: a display driving chip comprises a clock input interface, a signal input interface, a command signal input interface, a clock output interface, a signal output interface and a command signal output interface; the clock input interface inputs a clock signal, and the clock signal is transmitted to the clock output interface through a first Schmitt trigger; the instruction signal input interface inputs an instruction signal of chip data, and when the instruction signal is 1, the signal input interface inputs instruction information; when the indication signal is 0, the signal input interface inputs parameter or data information; the indication signal is respectively transmitted to the instruction signal output interface and the signal output interface through a second Schmitt trigger; when the instruction signal input interface is 1 or the chip data is not read, the signal input interface inputs data to be gated to the signal output interface for output; when reading the data in the chip, the display driving chip gates the data in the chip to the signal output interface for output;

the display driving chip is an LED screen driving chip or a touch screen driving chip;

the invention also discloses a display module, which comprises a display screen and the display driving chip, wherein the display screen is controlled by the display driving chip to display;

according to the display module, when the display driving chip is an LED screen driving chip, the display screen is an LED display screen, a display control module for driving the LED display screen is arranged on the LED screen driving chip, and display data sent by the display control module is stored in an SRAM (static random access memory) of the LED screen driving chip;

when the display driving chip is a touch screen driving chip, the display screen is an optical touch screen, an LED driving module and a PD sampling module are arranged on the touch screen driving chip, the LED driving module controls LED exposure, meanwhile, the PD sampling module samples the voltage of a PD and carries out AD conversion, and the result data is stored in an internal SRAM of the touch screen driving chip;

the display module is characterized in that an internal register for receiving clock signals and data input and reading and writing chip addresses and an image processing module for transmitting image data to the LED display screen are further arranged on the display driving chip;

the display module of the invention is characterized in that the display driving chip is also provided with an input module for receiving data signals and an output module for outputting the data signals.

The display module comprises an input module, a display module and a display module, wherein the input module comprises a clock input module, an instruction input module and a data input module; the output module comprises a clock output module, an instruction output module and a data output module.

The invention also discloses a display screen control cascade method, which comprises a host and a plurality of display screen driving chips, wherein two adjacent display screen driving chips are sequentially connected in series through a cascade transmission line; and the host transmits the data commands to the plurality of cascaded display screen driving chips in sequence through the cascade transmission line and then sends the data commands back to the host.

The cascade control method of the display screen comprises the following steps that when a display screen driving chip is an LED screen driving chip, a plurality of LED screen driving chips are distributed in a matrix; when the display screen driving chip is a touch screen driving chip, a plurality of touch screen driving chips are distributed along the periphery of the display screen.

The invention discloses a display screen control cascade method, wherein a host sends an address configuration instruction and two same original addresses to a first chip, the first chip adds 1 to one of the original addresses to form a first address of the first chip and sends the two same first addresses to a second chip, the second chip receives the address configuration instruction, the original addresses and the two first addresses in sequence, the second chip adds 1 to one of the first addresses to form a second address of the second chip and sends the two same second addresses to a third chip, the Nth chip receives the address configuration instruction, the original addresses, the first address, the second address and two (N-1) addresses in sequence, and the Nth chip adds 1 to one of the (N-1) addresses to form an Nth address of the Nth chip and sends the two same N addresses to the host;

before the host sends a data instruction, an internal register instruction is written to configure the head address of the SRAM, the chip address parameter is an effective address, the SRAM is directly written into an internal register according to the selected chip and the configured head address, the next data is written into the next SRAM address until the instruction is switched or the clock is stopped to be sent, meanwhile, the SRAM data is output from a signal output interface of the driving chip and is directly cascaded to the host, and if the instruction is not switched or the clock is stopped, the next SRAM data is sent out, and the SRAM data of the driving chip can be continuously read.

The invention has the beneficial effects that: the invention integrates the functions of signal receiving, cascading, sending and the like by one chip, and cascades a plurality of chips in a serial mode, so that the PCB has simple wiring, the components of the system are greatly reduced, only a plurality of signal wires are needed to control the internal functions of the chips, and the internal data of the chips are sent back to a host computer, and the signals are common digital logic signals; the CPU is easy to process and is not easy to be interfered, thereby reducing the power consumption of the system and leading the data interaction effect of the host and the slave to be more ideal.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be further described with reference to the accompanying drawings and embodiments, wherein the drawings in the following description are only part of the embodiments of the present invention, and for those skilled in the art, other drawings can be obtained without inventive efforts according to the accompanying drawings:

FIG. 1 is a schematic diagram of a single chip control display screen in the prior art;

FIG. 2 is a schematic diagram of the connection of a plurality of chip control display screens in the prior art;

FIG. 3 is a schematic diagram of a prior art I2C connection;

FIG. 4 is a schematic diagram of the connection of a background art SPI;

fig. 5 is a schematic diagram of LVDS connection in the background art;

fig. 6 is a schematic connection diagram of a display driver chip according to embodiment 1 of the present invention;

fig. 7 is a functional schematic diagram of an LED screen display module according to embodiment 2 of the present invention;

fig. 8 is a functional schematic diagram of an optical touch display module according to embodiment 2 of the present invention;

FIG. 9 is a schematic cascade diagram of a cascade control method for LED panels according to embodiment 3 of the present invention;

fig. 10 is a cascade schematic diagram of an optical touch screen control cascade method of embodiment 3 of the present invention;

FIG. 11 is a timing chart of instruction parameter configuration according to embodiment 3 of the present invention;

FIG. 12 is a timing chart of the cascade chip address fetch according to embodiment 3 of the present invention;

fig. 13 is a timing chart of reading the contents of the multichip and the internal address in embodiment 3 of the invention.

Detailed description of the invention

The terms "first," "second," "third," and "fourth," etc. in the description and claims of the invention and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.

"plurality" means two or more. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, a and/or B, which may indicate: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Also, the terms "upper, lower, front, rear, left, right, upper, lower, longitudinal" and the like, which denote orientation, are used with reference to the attitude and position of the device or apparatus in the present disclosure during normal use.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without inventive step, are within the scope of the present invention.

Example 1:

a display driver chip according to a preferred embodiment of the present invention is shown in fig. 6, which includes a clock input interface CKI, a signal input interface DI, a command signal input interface CMDI, a clock output interface CKO, a signal output interface DO, and a command signal output interface CMDO; the clock input interface CKI inputs a clock signal, and the clock signal is transmitted to the clock output interface CKO through the first Schmitt trigger S1; the instruction signal input interface CMDI inputs an instruction signal of chip data, and when the instruction signal is 1, the signal input interface DI inputs instruction information; when the indication signal is 0, the signal input interface DI inputs parameters or data information; it should be noted that, when the indication signal may also be 0, the signal input interface DI inputs the instruction information; when the indication signal is 1, the signal input interface DI inputs parameters or data information; the mutual substitution of 0 or 1 of the indication signal is a direct substitution of the conventional means, and the above simple substitution is all within the protection scope of the present invention.

The indication signal is respectively transmitted to the command signal output interface CMDO and the signal output interface DO through the second Schmitt trigger S3; when the command signal input interface CMDI is 1 or chip data is not read, the signal input interface DI inputs data to be gated to the signal output interface DO for output; when reading the internal data of the chip, the display driving chip gates the internal data of the chip to the signal output interface DO for output;

it is worth to be noted that the display driving chip is an LED screen driving chip or a touch screen driving chip.

The invention integrates the functions of signal receiving, cascading, sending and the like on a chip, and the signals are common digital logic signals; the CPU is easy to process and is not easy to be interfered, thereby reducing the power consumption of the system and leading the data interaction effect of the host and the slave to be more ideal.

Example 2:

the invention discloses a display module, which comprises a display screen and a display driving chip, wherein the display screen is controlled by the display driving chip to display;

as shown in fig. 7, when the display driving chip is an LED screen driving chip, the display screen is an LED display screen, a display control module 12 for driving the LED display screen 11 is disposed on the LED screen driving chip, and the display control module 12 sends display data to be stored in an internal SRAM of the LED screen driving chip.

In another specific application, as shown in fig. 8, when the display driving chip is a touch screen driving chip, the display screen is an optical touch screen 21, the touch screen driving chip is provided with an LED driving module 22 and a PD (infrared receiving) sampling module 23, the LED driving module 22 controls LED exposure, and the PD sampling module 23 samples the voltage of the PD and performs AD (analog-to-digital) conversion, and the result data is stored in an internal SRAM of the touch screen driving chip.

Specifically, an internal register 13 for receiving clock signals and data input and reading and writing chip addresses and an image processing module 14 for transmitting image data to the display screen are also arranged on the display screen driving chip; it should be noted that the internal register 13 and the image processing module 14 are both prior art.

Specifically, the display screen driving chip is further provided with an input module 15 for receiving a data signal, and an output module 16 for outputting the data signal.

Specifically, the input module includes a clock input port CKI, an instruction input port CMDI, and a data input port DI; when the input module inputs data, the bit width of the DI can be configured according to the requirement of the data transmission speed, so that the host configures the function register and the control instruction in the chip through the CKI, the CMDO and the DI. The output module 16 comprises a clock output port CKO, a command output port CMDO and a data output port DO. These output signals will be sent to the next chip or back to the host.

Example 3:

a display screen control cascade method comprises a host and a plurality of display screen driving chips, wherein two adjacent display screen driving chips are sequentially connected in series through a cascade transmission line; and the host transmits the data commands to the plurality of cascaded display screen driving chips in sequence through the cascaded transmission lines and then sends the data commands back to the host again.

The chips are sequentially connected in series, and the host can access and control each chip in a cascade mode without additional other devices, so that peripheral devices are greatly reduced; it should be noted that the cascade transmission lines are all digital lines, and the system is not easily interfered; and the chip can cascade according to the size of the screen, can adapt to the screen of different sizes.

Specifically, as shown in fig. 9, when the display screen driving chip is an LED screen driving chip, the LED screen driving chips are distributed in a matrix; the host sends the output signal to the chip 1, the chip 1 is connected with the chip 2, cascade connection is carried out until the last chip m × k, and the signal is sent back to the host again after cascade connection;

in another specific application, as shown in fig. 10, when the display screen driving chip is a touch screen driving chip, a plurality of touch screen driving chips are distributed along the periphery of the display screen; the plurality of touch screen driving chips surround the whole touch screen and consist of 2x +2y chips, the host sends output signals to the chip 1, the chip 1 is connected with the chip 2 and is cascaded all the time until the last chip 2x +2y, and the signals are cascaded and then sent back to the host again; the PCB is simple in wiring and convenient to process and assemble.

In order to realize cascade connection and read-write of chip internal control registers and SRAM data, the following definitions are carried out on signal control:

instruction name	Instruction description
		CFG_RST	Chip reset
CFG_VSYNC	Frame synchronization
		CFG_LSYNC	Line synchronization
CFG_ADDR	Address configuration
		CFG_WR_REG	Writing internal registers
CFG_RD_REG	Reading internal registers
		CFG_WR_SRAM	Writing internal SRAM
CFG_RD_SRAM	Reading internal SRAM

As shown in fig. 11, CMDI has 1 data content as a command and 0 data content as a parameter, and the subsequent parameter functions are different according to different commands.

The method specifically comprises the following functions:

resetting the chip: the instruction resets the internal register and SRAM of the chip, including the chip address obtained by the chip;

frame synchronization: when the instruction is received, starting the display of the next frame, and returning all the displays to the initial line;

line synchronization: entering next line display when receiving the instruction;

and (3) address configuration: in the initial stage of the chip, the chip does not obtain the corresponding address, and the corresponding address is obtained through the instruction.

Specifically, the host sends an address configuration instruction and two same original addresses to the first chip; the first chip adds 1 to an original address of the first chip as a first address of the first chip, and sends two identical first addresses to the second chip; the second chip receives an address configuration instruction, an original address and two first addresses in sequence; the second chip adds 1 to a first address to be a second address of the second chip and sends two same second addresses to the third chip; the Nth chip receives an address configuration instruction, an original address, a first address, a second address and two (N-1) addresses in sequence; the Nth chip adds 1 to its (N-1) address to its Nth address and sends the same two N addresses to the host.

As shown in fig. 12, the host initiates the address configuration command and the start address, and it is worth explaining that: the starting address is generally 0, when the first chip receives the address configuration instruction and the starting address, the chip adds 1 to the obtained address and outputs the address from the DO1, the host sends out two identical addresses, after the chip 1 confirms that the two identical addresses are received, the chip address which is obtained by adding 1 to the received address is the chip address of the chip, and similarly, the first chip also sends out data which is obtained by adding 1 to the two addresses to the next chip. In the chip 2, since the host sends the address configuration instruction and the start address, the DI1 of the chip 1 is directly sent to the DO1, and at this time, in the chip 2, the DI2 receives the address configuration instruction first, then receives the start address 0, then receives the address 1, and then receives the address 1.DO2 also sends an address configuration instruction first, then sends an address 0, then sends an address 1, then sends an address 2, and then sends an address 2, like chip 1, when the address 1 is received twice continuously, the chip is locked to be the address 2, and so on, until the last chip n, DIn receives the address configuration instruction first, then the address 0, the address 1, the address 2, and the address 3.. . Address (n-1), address (n-1), receives address (n-1) twice in succession, so chip n locks address n, and DOn outputs an address configuration instruction, then address 0, address 1, address 2, address 3.. . The address (n-1), the address n and the DOn are sent back to the host, when the host receives the address n twice, the host knows that n chips are cascaded on the whole screen, and at the moment, the address configuration of the whole chip is finished, and each chip obtains the corresponding address of the chip; the host computer control chip has simple time sequence and is convenient for the development of host computer programs.

Specifically, before the host sends a data instruction, the head address of the SRAM is configured by writing an internal register instruction, and the chip address parameter is an effective address, according to the selected chip and the configured head address, the internal register is directly written, the next data is written into the next SRAM address until a command is switched or a clock is stopped to be sent, and at the same time, the SRAM data is output from a signal output interface of a driver chip and is directly cascaded to the host, and if no command is switched or the clock is stopped, the next SRAM data is sent out, and the SRAM data of the driver chip can be continuously read.

Writing an internal register: the instruction set is (chip address + chip internal address + write configuration content); the host configures the parameters of the internal functional registers of the chip according to the application requirements. When the chip address sent by the host is 0, the global configuration is realized, and the parameters of the register addresses corresponding to all the chips are rewritten; if the host does not switch the configuration command and continues to clock, then the contents of the next register address will be overwritten (colloquially referred to as a continuous write).

Reading an internal register: the instruction set is (chip address + chip internal address + read configuration content); the host reads the internal functional parameters and results of the chip according to the application requirements. The command can be read singly and read continuously, and when the host reads a datum, the host stops sending a clock or switches the command into single reading; two types of continuous readings are adopted: 1. when the chip address is 0, the address content in all chips is read, each chip sends data to the DO data line according to the position of the address,

as shown in fig. 13, 2, when the chip address is not 0, the read content is the selected chip, the register address data configured by the host is read for the first time, then the register address is added by 1, the address data added by 1 is sent, and so on until the command is switched or the clock is stopped.

Writing an internal SRAM: before sending the instruction, firstly, configuring the first address of the SRAM by writing an internal register instruction, wherein the chip address parameter must be an effective address (which cannot be 0); according to the selected chip and the configured first address, the next data is directly written into the internal SRAM, the next data is written into the next SRAM address (the address is automatically added by 1), and the like until the command is switched or the sending clock is stopped.

Reading an internal SRAM: before sending the instruction, firstly, configuring the first address of the SRAM by writing an internal register instruction, wherein the chip address parameter must be an effective address (which cannot be 0); according to the selected chip and the configured first address, SRAM data is output from the chip DO and is directly cascaded to a host; if there is no switching command or clock stop, the next SRAM address data is sent out immediately, and so on, the SRAM data of the chip can be read continuously.

Thus, the components of the system are greatly reduced, the internal functions of the chip can be controlled only by a plurality of signal wires, and the internal data of the chip is sent back to the host computer, wherein the signals are common digital logic signals; thus, the PCB is simple in wiring, and the CPU is easy to process and not easy to interfere. Therefore, the power consumption of the system is reduced, and the data interaction effect between the host and the slave is more ideal.

It will be appreciated that modifications and variations are possible to those skilled in the art in light of the above teachings, and it is intended to cover all such modifications and variations as fall within the scope of the appended claims.

Claims (10)

1. A display driving chip is characterized by comprising a clock input interface, a signal input interface, a command signal input interface, a clock output interface, a signal output interface and a command signal output interface; the clock input interface inputs a clock signal, and the clock signal is transmitted to the clock output interface through a first Schmitt trigger; the instruction signal input interface inputs an instruction signal of chip data, and when the instruction signal is 1, the signal input interface inputs instruction information; when the indication signal is 0, the signal input interface inputs parameter or data information; the indication signal is respectively transmitted to the instruction signal output interface and the signal output interface through a second Schmitt trigger; when the instruction signal input interface is 1 or the chip data is not read, the signal input interface inputs data to be gated to the signal output interface for output; when reading the data in the chip, the display driving chip gates the data in the chip to the signal output interface for output.

2. The display driver chip of claim 1, wherein the display driver chip is an LED screen driver chip or a touch screen driver chip.

3. A display module comprising a display screen and the display driver chip as claimed in claim 1, wherein the display screen is controlled by the display driver chip to display.

4. The display module according to claim 3, wherein: when the display driving chip is an LED screen driving chip, the display screen is an LED display screen, a display control module for driving the LED display screen is arranged on the LED screen driving chip, and display data sent by the display control module is stored in an SRAM (static random access memory) in the LED screen driving chip;

when display driver chip is touch-sensitive screen driver chip, the display screen is optical touch-sensitive screen, be provided with LED drive module and PD sampling module on the touch-sensitive screen driver chip, LED drive module control LED exposes, simultaneously PD sampling module samples the voltage of PD and carries out AD conversion, and its result data memory is in touch-sensitive screen driver chip's inside SRAM.

5. The display module according to claim 3, wherein: the display driving chip is also provided with an internal register for receiving clock signals and data input and reading and writing chip addresses, and an image processing module for transmitting image data to the LED display screen.

6. The display module according to claim 5, wherein: the display driving chip is also provided with an input module for receiving data signals and an output module for outputting the data signals.

7. The display module according to claim 6, wherein: the input module comprises a clock input module, an instruction input module and a data input module; the output module comprises a clock output module, an instruction output module and a data output module.

8. A cascade control method for display screens comprises a host and a plurality of display screen driving chips according to claim 1, wherein two adjacent display screen driving chips are connected in series in sequence through a cascade transmission line; and the host transmits the data instructions to the plurality of cascaded display screen driving chips in sequence through the cascade transmission line and then sends the data instructions back to the host again.

9. The display screen control cascade method according to claim 8, wherein when the display screen driving chips are LED screen driving chips, a plurality of the LED screen driving chips are distributed in a matrix; when the display screen driving chip is a touch screen driving chip, a plurality of touch screen driving chips are distributed around the display screen.

10. The cascade control method according to claim 9, wherein the host sends an address configuration command and two identical original addresses to a first chip, the first chip adds 1 to one of the original addresses as a first address thereof and sends two identical first addresses to a second chip, the second chip receives the address configuration command, the original addresses and the two first addresses in sequence, the second chip adds 1 to one of the first addresses as a second address thereof and sends two identical second addresses to a third chip, the nth chip receives the address configuration command, the original addresses, the first address, the second address and two (N-1) addresses in sequence, the nth chip adds 1 to one of the (N-1) addresses as an nth address thereof and sends two identical N addresses to the host;

before the host sends a data instruction, an internal register instruction is written to configure the head address of the SRAM, the chip address parameter is an effective address, the SRAM is directly written into an internal register according to the selected chip and the configured head address, the next data is written into the next SRAM address until the instruction is switched or the clock is stopped to be sent, meanwhile, the SRAM data is output from a signal output interface of the driving chip and is directly cascaded to the host, and if the instruction is not switched or the clock is stopped, the next SRAM data is sent out, and the SRAM data of the driving chip can be continuously read.

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