KR101490823B1 - Apparatus of universal inter-integrated circuit interface for controlling devices using fpga and communication method for using the same - Google Patents

Abstract

The present invention relates to a general-purpose I2C interface device for controlling a device using an FPGA and a communication method using the same, and a general-purpose I2C interface device for controlling the device using an FPGA includes a serial data signal from a peripheral device connected to an I2C (Inter- An FPGA receiving unit for receiving the data and converting the data into a data structure that can be processed by a microcontroller unit (MCU) and outputting the converted data structure, an FPGA transmitter for receiving data from the MCU, converting the received data to a serial data signal, And a control unit connected to the MCU and receiving a transmission / reception command from the connected MCU to control operation of the FPGA receiving unit and the FPGA transmitting unit, generating a clock for synchronizing the MCU and the peripheral device, and outputting the clock through the I2C bus, Wherein the FPGA receiving unit and the FPGA transmitting unit transmit the serial data signal to the clock And an FPGA control unit for controlling transmission and reception of the data. According to the general-purpose I2C interface device for controlling the device using the FPGA and the communication method using the FPGA, there is an effect that the hardware stability and compatibility that can be applied to all systems are compatible through a simple configuration and an interactive protocol.

Description

Field of the Invention [0001] The present invention relates to a general-purpose I2C interface device for controlling a device using an FPGA and a communication method using the same. [0002]

The present invention relates to an I2C interface device, and more particularly, to a general purpose I2C interface device for controlling a device using an FPGA.

The connection between the microprocessor and other peripherals generally uses an address / data bus scheme. However, this method requires many pins for each device, which makes it difficult to downsize the PCB.

To address this difficulty, the I2C (Inter-Integrated Circuit) proposed by Philips in the 1980s requires only two bus lines for data transmission with a serial interface for a short distance. With only two I / O pins, data can be exchanged at speeds up to 400kb / s. In addition, because it supports multi-point rather than point-to-point, devices can be connected continuously to the I2C bus. Originally developed to enable easy communication between CPUs and peripherals on TV boards, today many embedded systems are used for communication with controllers and low-speed peripherals (external EEPROMs, digital sensors, LCD drivers, etc.).

However, in spite of its many advantages, communication using the I2C bus can be used only by a controller equipped with a specific I2C communication module, so that it is often difficult to ensure compatibility that can be universally applied to various devices. Therefore, a controller that does not have an I2C module needs a general-purpose interface device that converts and transmits / receives data according to the I2C protocol so that communication using the I2C bus can be performed. In addition, in order to meet the characteristics of I2C communication using only two lines, it is necessary to make a general-purpose I2C interface device with a small-sized circuit having a simple configuration.

An object of the present invention is to provide a general-purpose I2C interface device for controlling a device using an FPGA.

It is another object of the present invention to provide a communication method using a general-purpose I2C interface device for controlling a device using an FPGA.

The general-purpose I2C interface device for controlling devices using the FPGA according to the above-described object of the present invention receives serial data signals from a peripheral device connected to an I2C (Inter-Integrated Circuit) bus and outputs data An FPGA transmitter for receiving data from the MCU and converting the received data to a serial data signal and transmitting the serial data signal to the peripheral device; and an FPGA transmitter connected to the MCU, And outputs the serial data signal to the FPGA receiver and the FPGA transmitter through the I2C bus, and controls the operation of the FPGA receiver and the FPGA transmitter to generate a clock for synchronizing the MCU and the peripheral device, And an FPGA control unit for controlling the transmission and reception of the signals in synchronization with each other.

The general purpose I2C interface device for controlling a device using the FPGA is preferably configured such that the MCU operates as an I2C master device and one or more peripheral devices operate as a slave device of the I2C . Here, the peripheral device may be an internal memory, a sensor, or an output device.

Another object of the present invention is to provide a communication method using a general-purpose I2C interface device for controlling a device using an FPGA, in which a FPGA control unit receives a data transmission / reception instruction from an MCU (Micro Controller Unit), synchronizes the MCU with the peripheral device Outputting the serial data signal from the peripheral device connected to the I2C bus and receiving a data transmission command from the MCU when the data receiving instruction is received from the MCU; When the transmitter receives data from the MCU and receives a data reception command from the MCU, the FPGA receiver synchronizes the received serial data signal with the clock to convert the received serial data signal into a data structure that can be processed by the MCU, , And when receiving a data transmission command from the MCU, Converting the clocked data into a serial data signal, and synchronizing the serial data signal with the clock signal and transmitting the serial data signal to the peripheral device.

In addition, a communication method using a general-purpose I2C interface device for device control using an FPGA is characterized in that the MCU operates as a master device of I2C and one or more peripheral devices operate as a slave device of I2C . Here, the peripheral device may be an internal memory, a sensor, or an output device.

According to the general-purpose I2C interface device for controlling the device using the FPGA and the communication method using the same, by designing the general-purpose I2C interface using the FPGA, the hardware stability and the interactive protocol There is an effect of compatibility. Therefore, controllers without an I2C communication module can easily communicate with many peripherals using an I2C bus with only two lines.

In addition, it is possible to minimize the hardware circuit by using the general-purpose I2C interface device for device control using the FPGA, thereby minimizing the development cost and time.

1 is a block diagram of a general purpose I2C interface device for controlling a device using an FPGA according to an embodiment of the present invention.
2 is a block diagram of an I2C communication system using a general-purpose I2C interface device for controlling a device using an FPGA according to an embodiment of the present invention.
3 is a flowchart of a communication method using a general-purpose I2C interface device for controlling a device using an FPGA according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, A, B, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a general purpose I2C interface device for controlling a device using an FPGA according to an embodiment of the present invention.

1, a general purpose I 2 C (Inter-Integrated Circuit) interface device 100 for controlling a device using an FPGA may be configured to include an FPGA receiving unit 110, an FPGA transmitting unit 120, and an FPGA controlling unit 130 . Here, the FPGA receiving unit 110, the FPGA transmitting unit 120, and the FPGA controlling unit 130 are all modules designed using the FPGA. The general-purpose I2C interface device 100 is connected to an MCU (Micro Controller Unit) 300 having no I2C module and communicates with the peripheral device 400 via an I2C bus 200 having two lines of SDA and SCL It is a device that converts data to be able to do. The serial data for I2C bus consists of 7 bit address, R / W (read or write signal), transmission data, Acknowledge signal to receive data, START and STOP signals to inform start and end .

The FPGA receiving unit 110 receives the serial data signal from the peripheral device 400 connected to the I2C bus 200, converts the serial data signal into a data structure that can be processed by the MCU 300, and outputs the converted data.

The FPGA transmission unit 120 receives data from the MCU 300, converts the received data into a serial data signal, and transmits the serial data signal to the peripheral device 400 via the SDA line of the I2C bus 200.

 The FPGA control unit 130 is connected to the MCU 300 and controls the operation of the FPGA receiving unit 110 and the FPGA transmitting unit 120 by receiving data, an address and a transmission / reception instruction (RD / WR) from the MCU 300. The FPGA transmitting unit 120 stops the operation and controls the FPGA receiving unit 110 to receive the serial data signal from the peripheral device corresponding to the address received from the MCU 300. [ When receiving the transmission command, the FPGA receiving unit 110 stops the operation and controls the FPGA transmitting unit 120 to transmit data to the peripheral device corresponding to the address received from the MCU 300. Since the I2C bus 200 transmits and receives data to and from only one SDA line, the FPGA receiver 110 and the FPGA transmitter 1230 must be controlled not to operate at the same time.

The FPGA control unit 130 generates a clock for synchronizing the MCU 300 and the peripheral device 400 and outputs the clock through the SCL line of the I2C bus 200. The FPGA receiving unit 110 and the FPGA transmitting unit 120 The serial data signal is controlled to be transmitted and received in synchronization with the clock.

2 is a block diagram of an I2C communication system using a general-purpose I2C interface device for controlling a device using an FPGA according to an embodiment of the present invention.

2, the general purpose I2C interface device 100 for controlling a device using an FPGA is configured such that the MCU 300 operates as an I2C master device and one or more peripheral devices 400 are connected to the I2C slave (Slave) device. Here, the peripheral device may be an internal memory 410, a sensor 420, or an output device 430.

Since both the SDA line and the SCL line of the I2C bus 200 are open drain, a pull-up resistor 500 should be connected to each of the two lines. The peripheral devices 400 connected to the I2C bus 200 have respective addresses, so that the master can call the desired slave, i.e., the peripheral device, with this address. At this time, no matter how many devices are connected to the I2C bus 200, only one master and one slave can communicate at a time.

3 is a flowchart of a communication method using a general-purpose I2C interface device for controlling a device using an FPGA according to an embodiment of the present invention

In the communication method using the general-purpose I2C interface device for controlling devices using the FPGA, the FPGA control unit 130 receives a data transmission / reception instruction from the MCU (Micro Controller Unit) 300 (S110). Then, a clock for synchronizing the MCU 300 and the peripheral device 400 is generated and output through the I2C bus 200 (S110).

The control unit determines the data transmission / reception instruction received from the MCU 300 in step S120 and receives the data reception instruction from the MCU 300. The control unit receives the serial data from the peripheral device 400 connected to the I2C bus 200, (S131). When receiving a data transmission command from the MCU 300, the FPGA transmission unit 120 receives data from the MCU 300 (S132).

Next, when receiving the data reception instruction from the MCU 300, the FPGA receiving unit 110 synchronizes the received serial data signal with the clock, converts the received serial data signal into a data structure that can be processed by the MCU 300, , The FPGA transmission unit 120 converts the received data into a serial data signal and transmits the serial data signal to the peripheral device 300 in synchronization with the clock (S142).

At this time, in the communication method using the general-purpose I2C interface device for device control using the FPGA, the MCU 300 operates as the master device of the I2C and one or more peripheral devices are connected to the slave device of the I2C It is desirable to be configured to operate. Here, the peripheral device may be an internal memory, a sensor, or an output device.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

100: general-purpose I2C interface device 110: FPGA receiver
120: FPGA transmission unit 130: FPGA control unit
200: I2C bus 300: MCU
400: peripheral device 410: internal memory
420: sensor 430: output device

Claims (6)

An FPGA receiving unit for receiving a serial data signal from a peripheral device connected to an I2C (Inter-Integrated Circuit) bus and converting the parallel data signal into a parallel data signal having a data structure that can be processed by an MCU (Micro Controller Unit);
An FPGA transmitting unit receiving a parallel data signal from the MCU, converting the received parallel data signal into a serial data signal, and transmitting the parallel data signal to the peripheral device;
And a controller for controlling operation of the FPGA receiving unit and the FPGA transmitting unit by receiving data, address and transmission / reception command from the connected MCU, generating a clock for synchronizing the MCU and the peripheral device, And an FPGA control unit for controlling the FPGA receiving unit and the FPGA transmitting unit to synchronize the serial data signal with the clock and transmit and receive the serial data signal through the SDA line of the I2C bus,
Wherein the FPGA control unit comprises:
When receiving a reception command from the MCU, stops the operation of the FPGA transmitter and controls the FPGA receiver to receive a serial data signal from a peripheral device corresponding to an address received from the MCU, And controls the FPGA receiving unit and the FPGA transmitting unit to not operate at the same time, and controls the FPGA transmitting unit to transmit a serial data signal to a peripheral device corresponding to an address received from the MCU, A general-purpose I2C interface device for controlling the utilized device. The general-purpose I2C interface device for controlling a device using the FPGA according to claim 1,
Wherein the MCU operates as a master device of an I2C and one or more peripheral devices operate as a slave device of an I2C. 3. The apparatus of claim 2,
Wherein the I2C interface device is an internal memory, a sensor, or an output device. Receiving a data, address, and transmission / reception command from an MCU (Micro Controller Unit), generating a clock for synchronizing the MCU with a peripheral device, and outputting the generated clock through the I2C bus;
Receiving a serial data signal from a peripheral device connected to the I2C bus and receiving an instruction to transmit data from the MCU when the FPGA receiving unit receives the data receiving command from the MCU;
When receiving a data reception instruction from the MCU, the FPGA receiving unit synchronizes the received serial data signal with the clock to convert the received serial data signal into a data structure that can be processed by the MCU, and outputs the data structure, And the FPGA transmitter converts the received data into a serial data signal and transmits the serial data signal to the peripheral device in synchronization with the clock,
When receiving a data reception instruction from the MCU, the FPGA receiving unit synchronizes the received serial data signal with the clock to convert the received serial data signal into a data structure that can be processed by the MCU, and outputs the data structure, Wherein the step of converting the received data into a serial data signal and transmitting the serial data signal to the peripheral device in synchronization with the clock,
And the FPGA control unit controls the FPGA receiving unit and the FPGA transmitting unit to not operate simultaneously. The communication method using the general-purpose I2C interface apparatus for controlling a device using an FPGA. The communication method according to claim 4, wherein the general-purpose I2C interface device for device control using an FPGA is used,
A communication method using a general-purpose I2C interface device for controlling a device using an FPGA, wherein the MCU operates as a master device of an I2C and one or more peripheral devices operate as a slave device of an I2C . 6. The apparatus of claim 5,
Wherein the I2C interface device is an internal memory, a sensor, or an output device.

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