CN1979879A - Semiconductor device and method of fabricating the same - Google Patents

Semiconductor device and method of fabricating the same Download PDF

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Publication number
CN1979879A
CN1979879A CN 200610164165 CN200610164165A CN1979879A CN 1979879 A CN1979879 A CN 1979879A CN 200610164165 CN200610164165 CN 200610164165 CN 200610164165 A CN200610164165 A CN 200610164165A CN 1979879 A CN1979879 A CN 1979879A
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China
Prior art keywords
semiconductor layer
semiconductor
layer
exposed division
gate electrode
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CN 200610164165
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Chinese (zh)
Inventor
加藤树理
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

An insulating film (21) is formed on an upper/lower face in a hollow portion (20) between a semiconductor substrate (11) of a first region (R1) and a second semiconductor layer (13), an embedded insulating film (22) is formed in the hollow portion (20) and a groove (19) in which the insulating film (21) is formed, and an insulating film (23) is formed on an upper/lower face between a semiconductor substrate (11) of a second region (R2) and the second semiconductor layer (13), then with a medium of the insulating film (23), an embedded insulating film (24) is embedded between the semiconductor substrate (11) of the second region (R2) and the second semiconductor layer (13). Depravation of crystallizability of a semiconductor layer which forms a field effect type transistor can be restrained so as to improve controllability of a threshold using a back gate electrode.

Description

The manufacture method of semiconductor device and semiconductor device
Technical field
[0001]
The present invention relates to the manufacture method of semiconductor device and semiconductor device, particularly be applicable to the technology of imbedding the transistorized rear side of SOI (Silicon On Insulator), forming the semiconductor device of insulating barrier.
Background technology
[0002]
The FET that forms on SOI (Silicon On Insulator) substrate is because of easiness, locking freedom, the source/miss and close advantages such as electric capacity is little of its element separation, so its serviceability is noticeable.
In addition, for example in patent documentation 1, announced on large-area dielectric film, the silicon thin film that forms crystallinity and have good uniformity, and be radiated at noncrystalline or the polysilicon layer that forms on the dielectric film with making ultraviolet wave beam pulse type, thereby on dielectric film, form the go plate-like and arrange polysilicon film, adopt CMP (grinding of chemical mechanicalness) again, the method for the flattening surface of this polysilicon film near foursquare unijunction crystal grain.
Patent documentation 1: the spy opens flat 10-261799 communique
[0003]
, in the silicon thin film that on dielectric film, forms, exist granule boundary, miniature twin and other various small defectives.Therefore, the FET that forms on this silicon thin film is compared with the FET that forms on complete single crystal silicon, exists the low problem of transistor characteristic.
In addition, when being layered in the FET that forms on the silicon thin film, FET is present in lower floor.Therefore, exist the problem of flatness deterioration of the underlying insulation film of the silicon thin film that forms the upper strata, also exist the restriction of heat-treat condition when the silicon thin film that is subjected to forming the upper strata etc. simultaneously, the problem that the crystallinity of the silicon thin film on upper strata is lower than the crystallinity of the silicon thin film of lower floor.
[0004]
And then, in the semiconductor integrated circuit of prior art, be accompanied by transistorized granular, after raceway groove length shortens, the rising characteristic deterioration of the leakage current in subthreshold value zone.Therefore, exist following problems: when hindering transistorized low-voltage action, the leakage current when disconnecting is increased, thereby when not only causing moving and the power consumption during standby increase, but also become the damaged main cause of transistorized heat.And then, in order to suppress the short-channel effect that threshold value control and punch-through cause, and improve the impurity concentration of soi layer matrix, make the soi layer filming of channel region, perhaps in order to obtain precipitous subthreshold value, and often make the soi layer filming of channel region.The increase of this SOI filming and soi layer matrix impurity concentration has brought following problems: when the deviation that makes transistor characteristic increases, also cause mobility deterioration, transistorized making current to descend.
Summary of the invention
[0005]
Therefore, purpose of the present invention, be to provide the crystalline deterioration of the semiconductor layer that suppresses the formation FET, do not rely on the height of threshold value, the deterioration that does not have mobility, the stable transistor characteristic of realization, perhaps can utilize back of the body grid (back gate) electrode to improve the controlled semiconductor device of dynamic threshold and the manufacture method of semiconductor device.
[0006]
In order to solve above-mentioned problem, the semiconductor device that adopts a kind of sample attitude of the present invention to relate to, it is characterized in that: possess semiconductor layer (this semiconductor layer forms) after epitaxial growth on the semiconductor substrate, the 1st buried insulating layer (the 1st buried insulating layer is imbedded the 1st zone between described semiconductor substrate and the described semiconductor layer), the 2nd buried insulating layer (the 2nd buried insulating layer is imbedded the 2nd zone between described semiconductor substrate and the described semiconductor layer); Described the 1st buried insulating layer and described the 2nd buried insulating layer, at least one in effective efficiency function or the fixed charge amount is different.
[0007]
Like this, even the tagma of semiconductor layer (body region) when being mixed by intrinsic or low concentration ground, also can mix year different FET of threshold value on same substrate.Because can be irrelevant with the height of threshold voltage, reduce the concentration of the dopant of semiconductor layer, so during the FET that mixed year threshold value is different on same substrate, also can improve the degree of excursion that mixes all FETs that carry, increase its making current.In addition, owing to can in the scope that short-channel effect is allowed, reduce the impurity concentration of semiconductor layer, so during with the semiconductor layer thick film, also can obtain precipitous subthreshold value, make the threshold value optimization of each FET, reduce the characteristic deviation, can also improve rate of finished products simultaneously, reduce manufacturing cost.
[0008]
In addition, the semiconductor device that adopts a kind of sample attitude of the present invention to relate to, it is characterized in that: described the 1st buried insulating layer or described the 2nd buried insulating layer are made of silicon nitride film, the silicon oxide film that contains Al, the Hf oxide that contains Al, the Zr oxide that contains Al, the Zr oxide that does not contain the silicon oxide film of Al, do not contain the Hf oxide of Al or do not contain Al.For example: described the 1st buried insulating layer can be made of silicon nitride film, the silicon oxide film that contains Al, the Hf oxide that contains Al, the Zr oxide that contains Al; Described the 2nd buried insulating layer can be made of the silicon oxide film that does not contain Al, the Zr oxide that do not contain the Hf oxide of Al or do not contain Al.
[0009]
Like this, can guarantee the flatness at the interface of the gate insulating film of semiconductor layer surface and raceway groove, reduce interface benchmark density, can also reduce the impurity concentration of the semiconductor layer of channel region simultaneously, can mix and carry a plurality of FETs with different threshold values.Therefore, can suppress the deterioration of carrier mobility, suppress the deviation of transistor characteristic, obtain precipitous subthreshold value, the power consumption when reducing action, the high speed of realization FET.
[0010]
In addition, the semiconductor device that adopts a kind of sample attitude of the present invention to relate to, it is characterized in that: possess semiconductor layer (this semiconductor layer forms) on the 1st and the 2nd insulating barrier, (the 1st back-gate electrode is situated between described the 1st insulating barrier to the 1st back-gate electrode, be configured under the described semiconductor layer), (the 2nd back-gate electrode is situated between described the 2nd insulating barrier to the 2nd back-gate electrode, be configured under the described semiconductor layer), the 1st gate electrode (the 1st gate electrode forms on the described semiconductor layer on described the 1st insulating barrier), the 2nd gate electrode (the 2nd gate electrode forms on the described semiconductor layer on described the 2nd insulating barrier); The the described the 1st and the 2nd insulating barrier, at least one in effective efficiency function or the fixed charge amount is different.
In addition, described the 1st back-gate electrode and described the 2nd back-gate electrode both can be made of same material, also can be formed by the different materials with different work functions.And then described the 1st electrode and described the 2nd gate electrode both can be made of same material, also can be formed by the different materials with different work functions.
[0011]
Like this, can not be subjected to the restriction of the configuration of gate electrode and source/drain contact etc., with the current potential of the transistorized active region of back-gate electrode controlling filed effect type.Therefore, can suppress the complicated of manufacturing process, dynamically the transistorized threshold value of controlling filed effect type.In addition, when the gate electrode of described back-gate electrode and FET is connected, the rising characteristic of the leakage current in subthreshold value zone can be improved, the electric field of the raceway groove end of drain side can also be relaxed.Therefore, transistor is moved under low-voltage, the leakage current when reduce disconnecting when reducing action and the power consumption during standby, is realized high withstand voltageization of FET.
[0012]
In addition, in the 1st insulating barrier and the 2nd insulating barrier, after in its effective efficiency function or the fixed charge amount at least one set differently, when even the tagma of semiconductor layer is mixed fixedly by intrinsic or low concentration ground, also can on same substrate, mix and carry the different FET of threshold value.Because can be irrelevant with the height of threshold voltage, reduce the concentration of the dopant of semiconductor layer, so during the FET that mixed year threshold value is different on same substrate, also can improve the degree of excursion of FET, increase and mix all transistorized making current of carrying.In addition, owing to can reduce the impurity concentration of semiconductor layer, so in the scope that short-channel effect is allowed during with the semiconductor layer thick film, also can obtain precipitous subthreshold value, make the threshold value optimization of each FET, reduce the characteristic deviation, can also improve rate of finished products simultaneously, reduce manufacturing cost.
[0013]
In addition, the semiconductor device that adopts a kind of sample attitude of the present invention to relate to, it is characterized in that: described the 1st insulating barrier or described the 2nd insulating barrier are made of silicon nitride film, the silicon oxide film that contains Al, the Hf oxide that contains Al, the Zr oxide that contains Al, the Zr oxide that does not contain the silicon oxide film of Al, do not contain the Hf oxide of Al or do not contain Al.For example: described the 1st insulating barrier can be made of silicon nitride film, the silicon oxide film that contains Al, the Hf oxide that contains Al, the Zr oxide that contains Al; Described the 2nd insulating barrier can be made of the silicon oxide film that does not contain Al, the Zr oxide that do not contain the Hf oxide of Al or do not contain Al.
[0014]
Like this, the gate electrode film of FET and gate electrode, even be made of same material, the concentration in the semiconductor layer tagma of FET is certain, also can form the FET with different threshold values on the 1st dielectric film with on described the 2nd dielectric film.And then, can mediate by back-gate electrode, with the dynamically independent transistorized threshold value of controlling filed effect type of low-voltage.
[0015]
In addition, the semiconductor device that adopts a kind of sample attitude of the present invention to relate to is characterized in that: also possess respectively the wiring layer that the described the 1st and the 2nd gate electrode and the described the 1st and the 2nd back-gate electrode are electrically connected.
Like this, the inboard of the channel region of FET the current potential same with gate electrode can be controlled to, the ascendant of channel region electromotive force can be improved.Therefore,, also can obtain precipitous subthreshold value, can reduce the Leakage Current when disconnecting, can reduce the characteristic deviation even during with the semiconductor layer thick film.
[0016]
In addition, the semiconductor device that adopts a kind of sample attitude of the present invention to relate to is characterized in that possessing: the operation that forms the 1st semiconductor layer on semiconductor substrate; On described 1 semiconductor layer, form the operation of etching speed 2nd semiconductor layer littler than described the 1st semiconductor layer; Form the operation of the 1st exposed division, connecting described the 1st semiconductor layer and the 2nd semiconductor layer, when described semiconductor substrate is exposed, also described 1 semiconductor layer and the 2nd semiconductor layer branch are broken into the 1st and the 2nd zone in this operation; Form the operation of support, this support is done media by described the 1st exposed division, supports described the 2nd semiconductor layer on described semiconductor substrate; Form the operation of the 2nd exposed division, the 2nd exposed division makes the part of the 1st semiconductor layer in described the 1st zone, exposes from described the 2nd semiconductor layer; Form the operation of the 1st blank part, this operation is done media by described the 2nd exposed division, the 1st semiconductor layer in described the 1st zone of etching optionally, thus under described the 2nd semiconductor layer, form the 1st blank part of the 1st semiconductor layer of having removed described the 1st zone; The operation of the 1st buried insulating layer in described the 1st blank part is imbedded in formation; Form the operation of the 3rd exposed division, the 3rd exposed division makes the part of the 1st semiconductor layer in described the 2nd zone, exposes from described the 2nd semiconductor layer; Form the operation of the 2nd blank part, this operation is done media by described the 3rd exposed division, the 1st semiconductor layer in described the 2nd zone of etching optionally, thus under described the 2nd semiconductor layer, form the 2nd blank part of the 1st semiconductor layer of having removed described the 2nd zone; The operation of the 2nd buried insulating layer in described the 2nd blank part is imbedded in formation; Described the 1st buried insulating layer and described the 2nd buried insulating layer, at least one in effective efficiency function or the fixed charge amount is different.
[0017]
Like this, on the 1st semiconductor layer during stacked the 2nd semiconductor layer, also can do media by the 2nd groove, make the 1st semiconductor layer contact etch gas or etching solution, under the state that keeps the 2nd semiconductor layer, utilize the difference of the etching speed between the 1st and the 2nd semiconductor layer, remove the 1st semiconductor layer, can also form the buried insulating layer in the blank part of imbedding under the 2nd semiconductor layer simultaneously.In addition, be arranged on the semiconductor substrate support of supporting the 2nd semiconductor layer after, even when under the 2nd semiconductor layer, forming blank part, can prevent that also the 2nd semiconductor layer is shed on the semiconductor substrate.And then, in the 1st buried insulating layer and the 2nd buried insulating layer, after in its effective efficiency function or the fixed charge amount at least one set differently, even when mixed by intrinsic or low concentration ground in the tagma of the 2nd semiconductor layer, also can on same substrate, mix and carry the different FET of threshold value.
Therefore, can not use the SOI substrate, on the 2nd semiconductor layer, form the different a plurality of SOI transistors of threshold voltage.
[0018]
In addition, the semiconductor device that adopts a kind of sample attitude of the present invention to relate to is characterized in that possessing: on semiconductor substrate, form the operation of the 1st semiconductor layer; On described the 1st semiconductor layer, form the etching speed 2nd semiconductor layer operation littler than described the 1st semiconductor layer; On described the 2nd semiconductor layer, formation and described the 1st semiconductor layer have the operation of the 3rd semiconductor layer of same composition; On described the 3rd semiconductor layer, formation and described the 2nd semiconductor layer have the operation of the 4th semiconductor layer of same composition; Form the operation of the 1st exposed division, the 1st exposed division connects described the 1st～the 4th semiconductor layer, when described semiconductor substrate is exposed, also described the 1st semiconductor layer～the 4th semiconductor layer branch is broken into the 1st and the 2nd zone; Form the operation of support, this support is done media by described the 1st exposed division, supports the described the 2nd and the 4th semiconductor layer on described semiconductor substrate; Form the operation of the 2nd exposed division, the 2nd exposed division makes at least a portion of the 1st and the 3rd semiconductor layer in described the 1st zone, exposes from the described the 2nd and the 4th semiconductor layer; Form the operation of the 1st and the 2nd blank part, this operation is done media by described the 2nd exposed division, optionally etching the described the 1st and the 3rd semiconductor layer, thus form the 1st and the 2nd blank part of the 1st and the 3rd semiconductor layer of having removed described the 1st zone respectively; Form the operation of imbedding the 1st buried insulating layer in the described the 1st and the 2nd blank part respectively; Form the operation of the 3rd exposed division, the 3rd exposed division makes at least a portion of the 1st and the 3rd semiconductor layer in described the 2nd zone, exposes from the described the 2nd and the 4th semiconductor layer; Form the operation of the 3rd and the 4th blank part, this operation is done media by described the 3rd exposed division, optionally etching the 1st and the 3rd semiconductor layer, thus form the 3rd and the 4th blank part of the 1st and the 3rd semiconductor layer of having removed described the 2nd zone respectively; The operation of the 2nd buried insulating layer in the described the 3rd and the 4th blank part is imbedded in formation; Described the 1st buried insulating layer and described the 2nd buried insulating layer, at least one in effective efficiency function or the fixed charge amount is different.
[0019]
Like this, even respectively on the 1st and the 3rd semiconductor layer during the stacked the 2nd and the 4th semiconductor layer, also can do media by the 2nd groove, make the 1st and the 3rd semiconductor layer contact etch gas or etching solution, under the state that keeps the 2nd and the 4th semiconductor layer, remove the 1st and the 3rd semiconductor layer, can also form the buried insulating layer in the 1st and the 2nd blank part of imbedding under the 2nd and the 4th semiconductor layer simultaneously.In addition, form imbed the support of the 1st groove after, even when under the 2nd and the 4th semiconductor layer, forming the 1st and the 2nd blank part respectively, also can on semiconductor substrate, support the 2nd and the 4th semiconductor layer.
[0020]
Therefore, can reduce the generation of the defective of the 2nd and the 4th semiconductor layer, can on buried insulating layer, dispose the 2nd and the 4th semiconductor layer, can not use the SOI substrate, on the 4th semiconductor layer, form the SOI transistor, can also under the SOI transistor, dispose the back-gate electrode that constitutes by the 2nd semiconductor layer.
In addition, in the 1st buried insulating layer and the 2nd buried insulating layer, after in its effective efficiency function or the fixed charge amount at least one set differently, even when mixed by intrinsic or low concentration ground in the tagma of the 4th semiconductor layer, also can on same substrate, mix and carry the different FET of threshold value, can make the changes of threshold of FET.Therefore, can be irrelevant with the height of threshold voltage, reduce the concentration of the dopant of the 4th semiconductor layer, even on same substrate, mix when carrying the different FET of threshold value, also can improve the degree of excursion of FET, increase and mix all transistorized making current of carrying.
[0021]
In addition, adopt the manufacture method of the semiconductor device that a kind of sample attitude of the present invention relates to, it is characterized in that: also possessed before forming the 1st or the 2nd buried insulating layer, with the operation of the rear side of ammonia+hydrogen peroxide water washing the described the 2nd that contains Al and the 4th semiconductor layer.
Like this, can make buried insulating layer have negative fixed charge, when being mixed by intrinsic or low concentration ground, also can make the threshold value of FET that three ten-day period of hot season spy's variation takes place in the tagma of semiconductor layer.
[0022]
In addition, adopt the manufacture method of the semiconductor device that a kind of sample attitude of the present invention relates to, it is characterized in that: also possessed before forming the 1st or the 2nd buried insulating layer, wash the described the 2nd and the operation of the rear side of the 4th semiconductor layer with fluoric acid.
Like this, can make buried insulating layer have positive fixed charge, when being mixed by intrinsic or low concentration ground, also can make the changes of threshold of FET in the tagma of semiconductor layer.
[0023]
In addition, adopt the manufacture method of the semiconductor device that a kind of sample attitude of the present invention relates to, it is characterized in that: described semiconductor substrate and the described the 2nd and the 4th semiconductor layer are single crystals Si, and the described the 1st and the 3rd semiconductor layer is single crystals SiGe.
Like this, the lattice that can obtain between semiconductor substrate, the 1st～the 4th semiconductor layer is integrated, and can make the etching speed of the 1st and the 3rd semiconductor layer bigger than semiconductor substrate, the 2nd and the 4th semiconductor layer.Therefore, can form the 2nd and the 4th good semiconductor layer of crystalline quality respectively on the 1st and the 3rd semiconductor layer, the quality ground that can not damage the 2nd and the 4th semiconductor layer is with insulation between the 2nd and the 4th semiconductor layer and the semiconductor substrate 11.
[0024]
In addition, in order to solve above-mentioned problem, the semiconductor device that adopts a kind of sample attitude of the present invention to relate to, it is characterized in that: possess semiconductor layer (this semiconductor layer forms) after epitaxial growth on the semiconductor substrate, buried insulating layer (this buried insulating layer is imbedded between described semiconductor substrate and the described semiconductor layer), (this gate electrode is on described semiconductor layer for gate electrode, doing media by gate insulating film forms), source/drop ply (this source/drop ply forms on described semiconductor layer, is configured in a side of described gate electrode respectively); Described buried insulating layer and described gate insulating film, at least one in effective efficiency function or the fixed charge amount is different.
[0025]
Like this, when being mixed by intrinsic or low concentration ground, also can make the threshold value of FET that three ten-day period of hot season spy's variation takes place in the tagma of semiconductor layer.Therefore, can be irrelevant with the height of threshold voltage, reduce the concentration of the dopant of semiconductor layer, so during the FET that mixed year threshold value is different on same substrate, also can improve the degree of excursion of FET, improve the degree of excursion of FET, increase making current.In addition, owing to can reduce the impurity concentration of semiconductor layer,, reduce the characteristic deviation, can also improve rate of finished products simultaneously, reduce manufacturing cost so in the scope that short-channel effect is allowed, during with the semiconductor layer thick film, also can obtain precipitous subthreshold value.
[0026]
In addition, the semiconductor device that adopts a kind of sample attitude of the present invention to relate to, it is characterized in that: described gate insulating film and described buried insulating layer, their effective efficiency function or in the fixed charge amount at least one are different, are made of silicon oxide film, silicon oxynitride film, the silicon oxide film that contains Al, the Hf oxide that contains Al or Y or HfSi oxide, the Zr oxide that contains Al or Y or ZrSi oxide, the Hf oxide that does not contain Al or Y or HfSi oxide or the Zr oxide or the ZrSi oxide that do not contain Al or Y.
[0027]
For example, described gate insulating film is made of silicon oxide film or silicon oxynitride film; Described buried insulating layer, by silicon nitride film, the silicon oxide film that contains Al, the Hf oxide that contains Al, the Zr oxide that contains Al, when the Zr oxide that do not contain the Hf oxide of Al or do not contain Al constitutes, can guarantee the flatness at the interface of gate insulating film and raceway groove, reduce interface benchmark bit density, simultaneously can also be when the semiconductor layer filming of channel region, reduce impurity concentration, can the transistorized threshold value of controlling filed effect type.Therefore, can suppress the deterioration of carrier mobility, carry out the low-voltage action, can also suppress the deviation of transistor characteristic, obtain precipitous subthreshold value, the power consumption when reducing action, the high speed of realization FET.
[0028]
In addition, the semiconductor device that adopts a kind of sample attitude of the present invention to relate to, it is characterized in that: possess semiconductor layer (this semiconductor layer forms) on insulating barrier, (this back-gate electrode is situated between described insulating barrier to back-gate electrode, be configured under the described semiconductor layer), gate electrode (this gate electrode forms on described semiconductor layer), source/drop ply (this source/drop ply forms on described semiconductor layer, is configured in a side of described gate electrode respectively); Described insulating barrier and described gate insulating film, at least one in effective efficiency function or the fixed charge amount is different.
[0029]
Like this, can not be subjected to the restriction of the configuration of gate electrode and source/drain contact etc., with the current potential of the transistorized active region of back-gate electrode controlling filed effect type.Therefore, can suppress the complicated of manufacturing process, can improve the rising characteristic of the leakage current in subthreshold value zone, can also relax the electric field of the raceway groove end of drain side.Therefore, transistor is moved under low-voltage, the leakage current when reduce disconnecting when reducing action and the power consumption during standby, is realized high withstand voltageization of FET.
[0030]
In addition, in insulating barrier and gate insulating film, after in its effective efficiency function or the fixed charge amount at least one set differently,, also can make the threshold value of FET that three ten-day period of hot season spy's variation takes place even when mixed by intrinsic or low concentration ground in the tagma of semiconductor layer.Therefore, can be irrelevant with the height of threshold voltage, reduce the concentration of the dopant of semiconductor layer, improve the degree of excursion of FET, increase making current.In addition, owing to can reduce the impurity concentration of semiconductor layer,, reduce the characteristic deviation, can also improve rate of finished products simultaneously, reduce manufacturing cost so in the scope that short-channel effect is allowed, during with the semiconductor layer thick film, also can obtain precipitous subthreshold value.
[0031]
In addition, the semiconductor device that adopts a kind of sample attitude of the present invention to relate to, it is characterized in that: described gate insulating film and described buried insulating layer, in its effective efficiency function or the fixed charge amount at least one is different, is made of silicon oxide film, silicon oxynitride film, silicon nitride film, the silicon oxide film that contains Al, the Hf oxide that contains Al and Y and HfSi oxide, the Zr oxide that contains Al and Y and ZrSi oxide, the Hf oxide that does not contain Al and Y and HfSi oxide or the Zr oxide and the ZrSi oxide that do not contain Al and Y.The semiconductor device postpone of adopting a kind of sample attitude of the present invention to relate to, described gate insulator is made of silicon oxide film or silicon nitride film; Described insulating barrier is made of silicon nitride film, the silicon oxide film that contains Al, the Hf oxide that contains Al, the Zr oxide that contains Al, the Zr oxide that does not contain the Hf oxide of Al or do not contain Al.
[0032]
Like this, can guarantee the flatness at the interface of gate insulating film and raceway groove, reduce interface order density, can also do media by back-gate electrode simultaneously, with the transistorized threshold value of low-voltage controlling filed effect type.Therefore, can suppress the deterioration of carrier mobility, can carry out the low-voltage action, can also suppress the deviation of transistor characteristic, obtain precipitous subthreshold value, the power consumption when reducing action, the high speed of realization FET.
[0033]
In addition, the semiconductor device that adopts a kind of sample attitude of the present invention to relate to is characterized in that: also possess respectively the wiring layer that described gate electrode and described back-gate electrode are electrically connected.
Like this, the inboard of the channel region of FET the current potential same with gate electrode can be controlled to, the ascendant of channel region electromotive force can be improved.Therefore,, also can obtain precipitous subthreshold value, can reduce the Leakage Current when disconnecting, can reduce the characteristic deviation of the electric property that the thick deviation of soi semiconductor tunic causes even during with the semiconductor layer thick film.
[0034]
In addition, adopt the manufacture method of the semiconductor device that a kind of sample attitude of the present invention relates to, it is characterized in that possessing: the operation that on semiconductor substrate, forms the 1st semiconductor layer; On described 1 semiconductor layer, form the operation of etching speed 2nd semiconductor layer littler than described the 1st semiconductor layer; Form the operation of the 1st exposed division, the 1st exposed division connects described the 1st semiconductor layer and the 2nd semiconductor layer, and described semiconductor substrate is exposed; Form the operation of support, this support is done media by described the 1st exposed division, supports described the 2nd semiconductor layer on described semiconductor substrate; Form the operation of the 2nd exposed division, the 2nd exposed division makes the part of the 1st semiconductor layer in described the 1st zone, exposes from described the 2nd semiconductor layer; Form the operation of blank part, this operation is done media by described the 2nd exposed division, described the 1st semiconductor layer of etching optionally, thus under described the 2nd semiconductor layer, form the blank part of having removed described the 1st semiconductor layer; The operation of the buried insulating layer in the described blank part is imbedded in formation; On the surface of described the 2nd semiconductor layer, form the operation of gate insulating film; By the described media of doing, form the operation that is configured in the gate electrode on described the 2nd semiconductor layer; Described buried insulating layer and described gate insulating film, at least one in effective efficiency function or the fixed charge amount is different.
[0035]
Like this, on the 1st semiconductor layer during stacked the 2nd semiconductor layer, also can do media by the 2nd groove, make the 1st semiconductor layer contact etch gas or etching solution, under the state that keeps the 2nd semiconductor layer, utilize the difference of the etching speed between the 1st and the 2nd semiconductor layer, remove the 1st semiconductor layer, can also form the buried insulating layer in the blank part of imbedding under the 2nd semiconductor layer simultaneously.In addition, be arranged on the semiconductor substrate support of supporting the 2nd semiconductor layer after, even when under the 2nd semiconductor layer, forming blank part, can prevent that also the 2nd semiconductor layer is shed on the semiconductor substrate.And then, in buried insulating layer and gate insulating film, after in its effective efficiency function or the fixed charge amount at least one set differently,, also can make about the changes of threshold three ten-day period of hot season spy of FET even when mixed by intrinsic or low concentration ground in the tagma of the 2nd semiconductor layer.
[0036]
Therefore, can not use the SOI substrate, on the 2nd semiconductor layer, form the different a plurality of SOI transistors of threshold voltage, simultaneously can also obtain precipitous subthreshold value, can reduce the Leakage Current when disconnecting, so can realize the transistorized low price of SOI, low voltage driveization, low consumption electrification and high speed.
[0037]
In addition, adopt the manufacture method of the semiconductor device that a kind of sample attitude of the present invention relates to, it is characterized in that possessing: on semiconductor substrate, form the operation of the 1st semiconductor layer; On described the 1st semiconductor layer, form the etching speed 2nd semiconductor layer operation littler than described the 1st semiconductor layer; Form the operation of the 1st exposed division, the 1st exposed division connects described the 1st semiconductor layer and the 2nd semiconductor layer, and described semiconductor substrate is exposed; Form the operation of support, this support is done media by described the 1st exposed division, supports described the 2nd semiconductor layer on described semiconductor substrate; Form the operation of the 2nd exposed division, the 2nd exposed division makes at least a portion of described the 1st semiconductor layer, exposes from described the 2nd semiconductor layer; Form the operation of blank part, this operation is done media by described the 2nd exposed division, the described semiconductor layer of etching optionally, thus form the blank part of having removed described the 1st semiconductor layer; In the top and bottom of described blank part, form the operation of dielectric film; Formed the operation of imbedding in the described blank part of imbedding back-gate electrode up and down by described dielectric film with clipping; On the surface of described the 2nd semiconductor layer, form the operation of gate insulating film; Do media by described gate insulating film, form the operation that is configured in the gate electrode on described the 2nd semiconductor layer; Described buried insulating layer and described gate insulating film, at least one in effective efficiency function or the fixed charge amount is different.
[0038]
In addition, adopt the manufacture method of the semiconductor device that a kind of sample attitude of the present invention relates to, it is characterized in that: also possessed before the insulating barrier of the top and bottom that form described blank part, with the operation of the rear side of ammonia+hydrogen peroxide water washing the described the 2nd that contains Al and the 4th semiconductor layer.
In addition, adopt the manufacture method of the semiconductor device that a kind of sample attitude of the present invention relates to, it is characterized in that: also possessed before forming described buried insulating layer, wash the described the 2nd and the operation of the rear side of the 4th semiconductor layer with fluoric acid.
[0039]
Like this, can be in the blank part under forming transistorized the 2nd semiconductor layer of SOI, form by what described dielectric film was clamped and imbed back-gate electrode.In addition, at described dielectric film with in the gate insulating film that described the 2nd semiconductor layer surface forms, after in its effective efficiency function or the fixed charge amount at least one set differently, even when mixed by intrinsic or low concentration ground in the tagma of the 2nd semiconductor layer, also can make about the changes of threshold three ten-day period of hot season spy of FET.Therefore, can be irrelevant with the height of threshold voltage, in the scope that short-channel effect is allowed, reduce the concentration of the dopant of the 2nd semiconductor layer, improve the degree of excursion of FET, increase making current.
[0040]
In addition, adopt the manufacture method of the semiconductor device that a kind of sample attitude of the present invention relates to, it is characterized in that possessing: on semiconductor substrate, form the operation of the 1st semiconductor layer; On described the 1st semiconductor layer, form the etching speed 2nd semiconductor layer operation littler than described the 1st semiconductor layer; On described the 2nd semiconductor layer, formation and described the 1st semiconductor layer have the operation of the 3rd semiconductor layer of same composition; On described the 3rd semiconductor layer, formation and described the 2nd semiconductor layer have the operation of the 4th semiconductor layer of same composition; Form the operation of the 1st exposed division, the 1st exposed division connects described the 1st～the 4th semiconductor layer, and described semiconductor substrate is exposed; Form the operation of support, this support is done media by described the 1st exposed division, supports the described the 2nd and the 4th semiconductor layer on described semiconductor substrate; Form the operation of the 2nd exposed division, the 2nd exposed division makes at least a portion of the described the 1st and the 3rd semiconductor layer of described support formation, exposes from the described the 2nd and the 4th semiconductor layer; Form the operation of the 1st and the 2nd blank part, this operation is done media by described the 2nd exposed division, and optionally etching the described the 1st and the 3rd semiconductor layer have removed the described the 1st and the 1st and the 2nd blank part of the 3rd semiconductor layer respectively thereby form; Form the operation of imbedding the buried insulating layer in the described the 1st and the 2nd blank part respectively; On the surface of described the 4th semiconductor layer, form the operation of gate insulating film; Do media by described gate insulating film, form the operation that is configured in the gate electrode on described the 4th semiconductor layer; Described buried insulating layer and described gate insulating film, at least one in effective efficiency function or the fixed charge amount is different.
[0041]
Like this, even respectively on the 1st and the 3rd semiconductor layer during the stacked the 2nd and the 4th semiconductor layer, also can do media by the 2nd groove, make the 1st and the 3rd semiconductor layer contact etch gas or etching solution, under the state that keeps the 2nd and the 4th semiconductor layer, remove the 1st and the 3rd semiconductor layer, can also form the buried insulating layer in the 1st and the 2nd blank part of imbedding under the 2nd and the 4th semiconductor layer simultaneously.In addition, form imbed the support of the 1st groove after, even when under the 2nd and the 4th semiconductor layer, forming the 1st and the 2nd blank part respectively, also can on semiconductor substrate, support the 2nd and the 4th semiconductor layer.
[0042]
Therefore, can reduce the generation of the defective of the 2nd and the 4th semiconductor layer, can on buried insulating layer, dispose the 2nd and the 4th semiconductor layer, can not use the SOI substrate, on the 4th semiconductor layer, form the SOI transistor, can also under the SOI transistor, dispose the back-gate electrode that constitutes by the 2nd semiconductor layer.
In addition, in the 1st buried insulating layer and the 2nd buried insulating layer, after in its effective efficiency function or the fixed charge amount at least one set differently, even when mixed by intrinsic or low concentration ground in the tagma of the 4th semiconductor layer, also can on same substrate, mix and carry the different FET of threshold value, can make the changes of threshold of FET.Therefore, can be irrelevant with the height of threshold voltage, reduce the concentration of the dopant of the 4th semiconductor layer, even on same substrate, mix when carrying the different FET of threshold value, also can improve the degree of excursion of FET, increase and mix all transistorized making current of carrying.
[0043]
In addition, adopt the manufacture method of the semiconductor device that a kind of sample attitude of the present invention relates to, it is characterized in that: also possessed before forming described buried insulating layer, with the operation of the rear side of ammonia+hydrogen peroxide water washing the described the 2nd that contains Al and the 4th semiconductor layer.
Like this, can make buried insulating layer have negative fixed charge, when being mixed by intrinsic or low concentration ground, also can make about the changes of threshold three ten-day period of hot season spy of FET in the tagma of semiconductor layer.
[0044]
In addition, adopt the manufacture method of the semiconductor device that a kind of sample attitude of the present invention relates to, it is characterized in that: also possessed before forming described buried insulating layer, wash the described the 2nd and the operation of the rear side of the 4th semiconductor layer with fluoric acid.
Like this, can make buried insulating layer have positive fixed charge, when being mixed by intrinsic or low concentration ground, also can make about the changes of threshold three ten-day period of hot season spy of FET in the tagma of semiconductor layer.
[0045]
In addition, adopt the manufacture method of the semiconductor device that a kind of sample attitude of the present invention relates to, it is characterized in that: described semiconductor substrate and described the 2nd semiconductor layer are single crystals Si, and the described the 1st and the 3rd semiconductor layer is single crystals SiGe.
In addition, adopt the manufacture method of the semiconductor device that a kind of sample attitude of the present invention relates to, it is characterized in that: described semiconductor substrate and the described the 2nd and the 4th semiconductor layer are single crystals Si, and the described the 1st and the 3rd semiconductor layer is single crystals SiGe.
[0046]
Like this, the lattice that can obtain between the 1st～the 2nd semiconductor layer is integrated, and can make the etching speed of the 1st and the 3rd semiconductor layer bigger than semiconductor substrate, the 2nd and the 4th semiconductor layer.Therefore, can form the 2nd and the 4th good semiconductor layer of crystalline quality respectively on the 1st and the 3rd semiconductor layer, the quality ground that can not damage the 2nd and the 4th semiconductor layer is with insulation between the 2nd and the 4th semiconductor layer and the semiconductor substrate 11.
Description of drawings
Fig. 1 is the figure of the manufacture method of the semiconductor device that relates to of expression the 1st execution mode of the present invention.
Fig. 2 is the figure of the manufacture method of the semiconductor device that relates to of expression the 1st execution mode of the present invention.
Fig. 3 is the figure of the manufacture method of the semiconductor device that relates to of expression the 1st execution mode of the present invention.
Fig. 4 is the figure of the manufacture method of the semiconductor device that relates to of expression the 1st execution mode of the present invention.
Fig. 5 is the figure of the manufacture method of the semiconductor device that relates to of expression the 1st execution mode of the present invention.
Fig. 6 is the figure of the manufacture method of the semiconductor device that relates to of expression the 1st execution mode of the present invention.
Fig. 7 is the figure of the manufacture method of the semiconductor device that relates to of expression the 1st execution mode of the present invention.
Fig. 8 is the figure of the manufacture method of the semiconductor device that relates to of expression the 1st execution mode of the present invention.
Fig. 9 is the figure of the manufacture method of the semiconductor device that relates to of expression the 2nd execution mode of the present invention.
Figure 10 is the figure of the manufacture method of the semiconductor device that relates to of expression the 2nd execution mode of the present invention.
Figure 11 is the figure of the manufacture method of the semiconductor device that relates to of expression the 2nd execution mode of the present invention.
Figure 12 is the figure of the manufacture method of the semiconductor device that relates to of expression the 2nd execution mode of the present invention.
Figure 13 is the figure of the manufacture method of the semiconductor device that relates to of expression the 2nd execution mode of the present invention.
Figure 14 is the figure of the manufacture method of the semiconductor device that relates to of expression the 2nd execution mode of the present invention.
Figure 15 is the figure of the manufacture method of the semiconductor device that relates to of expression the 2nd execution mode of the present invention.
Figure 16 is the figure of the manufacture method of the semiconductor device that relates to of expression the 2nd execution mode of the present invention.
Figure 17 is the figure of the manufacture method of the semiconductor device that relates to of expression the 3rd execution mode of the present invention.
Figure 18 is the figure of the manufacture method of the semiconductor device that relates to of expression the 3rd execution mode of the present invention.
Figure 19 is the figure of the manufacture method of the semiconductor device that relates to of expression the 3rd execution mode of the present invention.
Figure 20 is the figure of the manufacture method of the semiconductor device that relates to of expression the 3rd execution mode of the present invention.
Figure 21 is the figure of the manufacture method of the semiconductor device that relates to of expression the 3rd execution mode of the present invention.
Figure 22 is the figure of the manufacture method of the semiconductor device that relates to of expression the 3rd execution mode of the present invention.
Figure 23 is the figure of the manufacture method of the semiconductor device that relates to of expression the 3rd execution mode of the present invention.
Figure 24 is the figure of the manufacture method of the semiconductor device that relates to of expression the 3rd execution mode of the present invention.
Figure 25 is the figure of the manufacture method of the semiconductor device that relates to of expression the 3rd execution mode of the present invention.
Figure 26 is the figure of the manufacture method of the semiconductor device that relates to of expression the 3rd execution mode of the present invention.
Figure 27 is the figure of the manufacture method of the semiconductor device that relates to of expression the 4th execution mode of the present invention.
Figure 28 is the figure of the manufacture method of the semiconductor device that relates to of expression the 4th execution mode of the present invention.
Figure 29 is the figure of the manufacture method of the semiconductor device that relates to of expression the 4th execution mode of the present invention.
Figure 30 is the figure of the manufacture method of the semiconductor device that relates to of expression the 4th execution mode of the present invention.
Figure 31 is the figure of the manufacture method of the semiconductor device that relates to of expression the 4th execution mode of the present invention.
Figure 32 is the figure of the manufacture method of the semiconductor device that relates to of expression the 4th execution mode of the present invention.
Figure 33 is the figure of the manufacture method of the semiconductor device that relates to of expression the 4th execution mode of the present invention.
Figure 34 is the figure of the manufacture method of the semiconductor device that relates to of expression the 4th execution mode of the present invention.
Figure 35 is the figure of the manufacture method of the semiconductor device that relates to of expression the 4th execution mode of the present invention.
Embodiment
[0047]
Below, with reference to accompanying drawing, tell about semiconductor device and manufacture method thereof that embodiments of the present invention relate to.
(1) the 1st execution mode
Fig. 1 (a)～Fig. 8 (a) is the vertical view of the manufacture method of the semiconductor device that relates to of expression the 1st execution mode of the present invention, Fig. 1 (b)～Fig. 8 (b) is the profile that the A1-A1 ' that uses Fig. 1 (a)～Fig. 8 (a) respectively～A8-A8 ' line cuts off, and Fig. 1 (c)～Fig. 8 (c) is the profile that B1-B1 '～B8-B8 ' line of using Fig. 1 (a)～Fig. 8 (a) respectively cuts off.
[0048]
In Fig. 1, epitaxial growth forms the 1st semiconductor layer 12 on semiconductor substrate 11, and epitaxial growth forms the 2nd semiconductor layer 13 on the 1st semiconductor layer 12.In addition, the 1st semiconductor layer 12 can use etching speed than semiconductor substrate 11 and the big material of the 2nd semiconductor layer 13, as the material of semiconductor substrate the 11, the 1st semiconductor layer 12 and the 2nd semiconductor layer 13, for example can use the combination of from Si, Ge, SiGe, SiC, SiSn, PbS, GaAS, InP, GaP, GaN or ZnSe etc., selecting.When particularly semiconductor substrate 11 is single crystals Si,, preferably use single crystals SiGe (Ge is 10-50%) as the 1st semiconductor layer 12; As the 2nd semiconductor layer 13, preferably use single crystals Si.Like this, the lattice that can obtain between the 1st semiconductor layer 12 and the 2nd semiconductor layer 13 is integrated, and can guarantee the selection ratio between the 1st semiconductor layer 12 and the 2nd semiconductor layer 13.In addition, as the 1st semiconductor layer 12, except mono crystalline semiconductor layer, can also use many crystalline semiconductor layer, amorphous semiconductor layer or porous matter semiconductor layer.In addition, can also replace the 1st semiconductor layer 12, use can epitaxial growth forms the metal oxide film of the r-aluminium oxide of mono crystalline semiconductor layer etc.In addition, the thickness of the 1st semiconductor layer 12 and the 2nd semiconductor layer 13 for example can be decided to be about 1～200nm.
[0049]
Then, adopt the thermal oxidation of the 2nd semiconductor layer 13, form substrate oxide-film 14 on the surface of the 2nd semiconductor layer 13.Again then, by methods such as CVD, on whole on the substrate oxide-film 14, form oxidation and prevent film 15.In addition,, for example can use silicon nitride film,, can also play a role as the barrier layer of adopting CMP (grinding of chemical mechanicalness) to carry out in the flatening process except making it prevents that as oxidation film from playing a role as anti-oxidation surface diaphragm 15.
[0050]
Then, as shown in Figure 2, use figure etching art and etching technique, prevent Butut on film 15, substrate oxide-film the 14, the 2nd semiconductor layer 13 and the 1st semiconductor layer 12 in oxidation, thereby when forming the part make semiconductor substrate 11 and expose, also the 2nd semiconductor layer 13 and the 1st semiconductor layer were broken into the groove 16 of the 1st region R 1 and the 2nd region R 2 in 12 minutes.In addition, when the part of semiconductor substrate 11 is exposed, both can be in the surface barrier etching of semiconductor substrate 11, also can over etching semiconductor substrate 11 after, on semiconductor substrate 11, form recess.In addition, the allocation position of groove 16 can make the part of element separated region of the 2nd semiconductor layer 13 corresponding.
[0051]
Then, as shown in Figure 3, adopt methods such as CVD, form the support of imbedding in the groove 16 18, so that cover on the semiconductor substrate 11 whole.In addition, form on the 1st semiconductor layer 12 that support 18 also can be in groove 16 and the sidewall of the 2nd semiconductor layer 13, on semiconductor substrate 11, support the 2nd semiconductor layer 13.Cover the support 18 that integrally forms of semiconductor substrate 11, need the deflection of inhibition the 2nd semiconductor layer 13 etc., under the state that keeps flatness, support the 2nd semiconductor layer 13.Therefore, in order to ensure its mechanical strength, preferably become than smallest elements and separate the thick thickness of width.In addition, as the material of support 18, can use insulators such as silicon oxide film.
[0052]
Then, as shown in Figure 4, use figure etching art and etching technique, prevent Butut on film 15, substrate oxide-film the 14, the 2nd semiconductor layer 13 and the 1st semiconductor layer 12, thereby form the groove 19 that the part of the 1st semiconductor layer 12 that makes the 1st region R 1 is exposed in support 18, the oxidation of the 1st region R 1.Here, when formation makes the groove 19 that the part of the 1st semiconductor layer 12 of the 1st region R 1 exposes, in addition, when the part of semiconductor substrate 11 is exposed, can under the state of the 1st semiconductor layer 12 that covers the 2nd region R 2 with support 18, the 2nd semiconductor layer 13 of the 2nd region R 2 and the part of the 1st semiconductor layer 12 be exposed.In addition, the allocation position of groove 19 can make the part of element separated region of the 2nd semiconductor layer 13 of the 1st region R 1 corresponding.
[0053]
In addition, when the part of the 1st semiconductor layer 12 is exposed, both can be with the surface barrier etching of the 1st semiconductor layer 12, also can over etching the 1st semiconductor layer 12 after, on the 1st semiconductor layer 12, form recess.Perhaps, the 1st semiconductor layers 12 in the groove 19 are connected after, the surface of semiconductor substrate 11 is exposed.Behind the 1st semiconductor layer 12 that stops etching halfway, can prevent that the surface of the semiconductor substrate 11 in the groove 19 from exposing here.Therefore, when the 1st semiconductor layer 12 is removed in etching, the exposure time of semiconductor substrate 11 in etching solution or etching gas in the groove 19 can be reduced, the semiconductor substrate 11 in the over etching groove 19 can be suppressed.
[0054]
Then, as shown in Figure 5, do media, etching gas or etching solution are contacted with the 1st semiconductor layer 12 of the 1st region R 1 by groove 19, thereby the 1st semiconductor layer 12 of the 1st region R 1 is removed in etching, forms blank part 20 between the semiconductor substrate 11 of the 1st region R 1 and the 2nd semiconductor layer 13.
Here, after support 18 is set in groove 16, even when having removed the 1st semiconductor layer 12, also can on semiconductor substrate 11, support the 2nd semiconductor layer 13, simultaneously, after outside the groove 16 groove 19 being set separately, etching gas or etching solution are contacted with the 1st semiconductor layer 12 under the 2nd semiconductor layer 13.Therefore, can not damage the quality ground of the 2nd semiconductor layer 13 with insulation between the 2nd semiconductor layer 13 and the semiconductor substrate 11.
[0055]
In addition, semiconductor substrate 11 and the 2nd semiconductor layer 13 are Si, when the 1st semiconductor layer 12 is SiGe, as the etching solution of the 1st semiconductor layer 12, preferably uses and fluoridize nitric acid (mixed liquor of fluoric acid, nitric acid, water).Like this, over etching semiconductor substrate 11 and the 2nd semiconductor layer 13 can be suppressed, the 1st semiconductor layer 12 can be removed.In addition, as the etching solution of the 1st semiconductor layer 12, can also use and fluoridize nitric acid+aquae hydrogenii dioxidi, ammonia+aquae hydrogenii dioxidi or fluoridize acetic acid+aquae hydrogenii dioxidi etc.
[0056]
In addition, before the 1st semiconductor layer 12 is removed in etching, methods such as anodic oxidation both can have been adopted, make the 1st semiconductor layer 12 porous materializations, also can inject ion to the 1st semiconductor layer 12, thereby,, can also use the P type semiconductor substrate as semiconductor substrate 11 with the 1st semiconductor layer 12 amorphousization.Like this, can increase the etching speed of the 1st semiconductor layer 12, enlarge the etching area of the 1st semiconductor layer 12.
[0057]
Then, as shown in Figure 6, adopt methods such as CVD, the top and bottom in the blank part 20 between semiconductor substrate 11 and the 2nd semiconductor layer 13 form dielectric film 21.Then, adopt methods such as CVD, in the blank part 20 and groove 19 that form dielectric film 21, form buried insulating layer 22.In Fig. 6, behind the formation buried insulating layer 22, adopt CMP to handle or do not use the etch processes of mask, remove the buried insulating layer of on the whole surface of semiconductor, putting aside 22.
[0058]
Then, as shown in Figure 7,, carry out and processing that Fig. 4～Fig. 6 is same,, form dielectric film 23 in the semiconductor substrate 11 of the 2nd region R 2 and the top and bottom between the 2nd semiconductor layer 13 for the 2nd region R 2 on the semiconductor substrate 11.Then, do media, between the semiconductor substrate ll and the 2nd semiconductor layer 13 of the 2nd region R 2, when imbedding buried insulating layer 24, in the groove at the both ends of the 2nd semiconductor layer 13 of the 2nd region R 2, imbed buried insulating layer 24 by dielectric film 23.Here, dielectric film 21,23 or buried insulating layer 22,24, at least one in effective efficiency function or the fixed charge amount set differently.For example: as dielectric film 21, can use silicon nitride film, contain Al silicon oxide film, contain Al the Hf oxide, contain the Zr oxide of Al; As dielectric film 23, the Zr oxide that can use the silicon oxide film that does not contain Al, the Hf oxide that does not contain Al or not contain Al etc.Specifically, as dielectric film 21, can use silicon nitride film; As buried insulating layer 22,24, can use silicon oxide film; As dielectric film 23, can use HfAlO X
[0059]
In addition, as the material of dielectric film 21,23 and buried insulating layer 22,24, for example except silicon oxide film, can also use silicon nitride film etc.Perhaps, as the material of dielectric film 21,23 and buried insulating layer 22,24, for example can use HfO 2, HfON, HfAlO, HfAlON, HfSiO, HfSiON, ZrO 2, ZrON, ZrAlO, ZrAlON, ZrSiO, ZrSiON, Ta 2O 5, Y 2O 3, (Sr, Ba) TiO 3, LaAlO 3, SrBi 2Ta 2O 9, Bi 4Ti 3O 12, Pb (Zi, Ti) O 3Deng dielectric.
[0060]
Like this, can set the threshold value of a plurality of FETs separately.For example, as dielectric film 21,23 and buried insulating layer 22,24, when using silicon nitride film, P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn can both make threshold value move to negative direction.In addition, as dielectric film 21,23 and buried insulating layer 22,24, use HfAlO XThe time, being accompanied by the increase of Al concentration, P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn can both make threshold value move to positive direction.
[0061]
Therefore, even when mixed by intrinsic or low concentration ground in the tagma of the 2nd semiconductor layer 13, also can on same semiconductor substrate 11, mix and carry the different FET of threshold value, can be irrelevant with the height of the threshold value of FET, improve the degree of excursion of FET, increase its making current.In addition, owing to can reduce the impurity concentration of the 2nd semiconductor layer 13, so during with the 2nd semiconductor layer 13 thick films, also can obtain precipitous subthreshold value, when on the 2nd semiconductor layer 13, forming FET, also can make the threshold value optimization of each FET, can reduce resulting from the characteristic deviation of thickness deviation of the 2nd semiconductor layer 13, simultaneously can also improve rate of finished products, reduce manufacturing cost.
[0062]
In addition,, can pass through preceding washing procedure, make dielectric film 21,23 and buried insulating layer 22,24 have negative electrical charge or positive charge for the transistorized threshold value of controlling filed effect type.Here, when making dielectric film 21,23 and buried insulating layer 22,24 have negative electrical charge, can be before forming dielectric film 21,23 and buried insulating layer 22,24, with the rear side of ammonia+hydrogen peroxide water washing the 2nd semiconductor layer 13 that contains Al.In addition, when making dielectric film 21,23 and buried insulating layer 22,24 have positive charge, can be before forming dielectric film 21,23 and buried insulating layer 22,24, the rear side of washing the 2nd semiconductor layer 13 with fluoric acid.
Then, adopt CMP or do not use the methods such as etch processes of mask, in the time of with dielectric film 21,23 and buried insulating layer 22,24 and support 18 filmings, also oxidation is prevented film as the barrier layer, the planarization that stops CMP to produce.Then, remove substrate oxide-film 14 and oxidation and prevent film 15, the surface of the 2nd semiconductor layer 13 of the 1st region R 1 and the 2nd region R 2 is exposed.
[0063]
Then, as shown in Figure 8, the thermal oxidation, ALD or the CVD that carry out the surface of the 2nd semiconductor layer 13 handle, thereby on the surface of the 2nd semiconductor layer 13 of the 1st region R 1 and the 2nd region R 2, form gate insulating film 25a, 25b respectively.Then, adopt methods such as CVD, on the 2nd semiconductor layer 13 that forms gate insulating film 25a, 25b, form polysilicon layer, silicon oxide layer or metal level.Then, use figure etching art and etching technique, Butut on polysilicon layer, silicon oxide layer or metal level, thus on gate insulating film 25a, 25b, form gate electrode 26a, 26b respectively.
[0064]
Then, as mask, ion injects impurity such as As, P, B in the 2nd semiconductor layer 13 with gate electrode 26a, 26b, thus the LDD layer that forms the both sides that are configured in gate electrode 26a, 26b respectively, constitutes by the low concentration impurity implanted layer.Then, adopt methods such as CVD, on the 2nd semiconductor layer 13 that forms the LDD layer, form insulating barrier, use anisotropic etchings such as RIE, insulating barrier is not used the etching of mask, thereby, form sidewall 27a, 27b respectively at the sidewall of gate electrode 26a, 26b.Then, with gate electrode 26a, 26b and sidewall 27a, 27b as mask, ion injects impurity such as As, P, B in the 2nd semiconductor layer 13, thus source layer 28a, the 28b and drain electrode layer 29a, the 29b that on the 2nd semiconductor layer 13, form the both sides that are configured in sidewall 27a, 27b respectively, constitute by the high concentration impurities implanted layer.
Like this, can reduce the generation of the defective of the 2nd semiconductor layer 13, can on buried insulating layer 22,24, dispose the 2nd semiconductor layer 13, can on the basis that suppresses the cost increase, can also form the mutually different SOI transistor of threshold value.
[0065]
(2) the 2nd execution modes
Fig. 9 (a)～Figure 16 (a) is the vertical view of the manufacture method of the semiconductor device that relates to of expression the 2nd execution mode of the present invention, Fig. 9 (b)～Figure 16 (b) is the profile that the A21-A21 ' that uses Fig. 9 (a)～Figure 16 (a) respectively～A28-A28 ' line cuts off, and Fig. 9 (c)～Figure 16 (c) is the profile that B21-B21 '～B28-B28 ' line of using Fig. 9 (a)～Figure 16 (a) respectively cuts off.
[0066]
In Fig. 9, on semiconductor substrate 131, stack gradually to epitaxial growth semiconductor layer 151,133,152,135.Here, semiconductor layer 151,152 can use the etching speed material bigger than semiconductor substrate 131 and semiconductor layer 133,135.When particularly semiconductor substrate 131 is single crystals Si,, preferably use SiGe as semiconductor layer 151,152; As semiconductor layer 133,135, preferably use Si.
Then, methods such as the thermal oxidation of employing semiconductor layer 135 or CVD form substrate oxide-film 153 on the surface of semiconductor layer 135.Again then, by methods such as CVD, on whole of substrate oxide-film 153, form oxidation and prevent film 154.
[0067]
Then, as shown in figure 10, use figure etching art and etching technique, prevent Butut on film 154, substrate oxide-film 153, the semiconductor layer 135,152,133,151 in oxidation, thereby form when semiconductor substrate 131 is exposed, also, form the groove 136 that semiconductor layer was broken into the 1st region R 11 and the 2nd region R 12 in 135,152,133,151 minutes along the direction of regulation.
[0068]
Then, as shown in figure 11, adopt methods such as CVD, on whole of semiconductor substrate 131, form the support 156 of imbedding in the groove 136, on semiconductor substrate 131, supporting semiconductor layer 133,135.In addition, as the material of support 156, can use insulators such as silicon oxide film.
Follow again, as shown in figure 12, use figure etching art and etching technique, oxidation in the 1st region R 11 prevents Butut on film 154, substrate oxide-film 153, the semiconductor layer 135,152,133,151, thereby along with the direction of groove 136 quadratures, form the groove 138 that the semiconductor layer 151,152 that makes the 1st region R 11 exposes.
[0069]
Then, as shown in figure 13, do media by groove 138, etching gas or etching solution are contacted with semiconductor layer 151,152, thereby the semiconductor layer 151,152 of the 1st region R 11 is removed in etching, between the semiconductor substrate 131 of the 1st region R 11 and semiconductor layer 133, form in the blank part 157a, also between semiconductor layer 133,135, form blank part 157b.
[0070]
Follow again, as shown in figure 14, adopt methods such as CVD, in the semiconductor substrate 131 of the 1st region R 11 and blank part 157a, 157b between the semiconductor layer 133,135 and the top and bottom in the groove 138, formation buried insulating layer 158., in blank part, express the example of imbedding with 2 dielectric films here, but have only 1 layer good.In Figure 14, behind the buried insulating layer 157,158 of formation blank part, adopt CMP to handle and do not use the etch processes of mask, remove the buried insulating layer of on the whole surface of semiconductor, putting aside 157,158.
[0071]
Then, as shown in figure 15,, carry out and processing that Figure 12～Figure 14 is same, thereby, form dielectric film 159 in the semiconductor substrate 131 of the 2nd region R 12 and the top and bottom between the semiconductor layer 133,135 for the 2nd region R 12 on the semiconductor substrate 131.Then, do media by dielectric film 159, between the semiconductor substrate 131 and semiconductor layer 133,135 of the 2nd region R 12, when imbedding buried insulating layer 160, in the groove at the both ends of the semiconductor layer 133,135 of the 2nd region R 12, imbed buried insulating layer 160.Here, dielectric film 157,159 or buried insulating layer 158,160 preferably make in effective efficiency function or the fixed charge amount at least one set differently.For example: as dielectric film 157, can use silicon nitride film, contain Al silicon oxide film, contain Al the Hf oxide, contain the Zr oxide of Al; As dielectric film 159, the Zr oxide that can use the silicon oxide film that does not contain Al, the Hf oxide that does not contain Al or not contain Al etc.Specifically, as dielectric film 157, can use HfO XAs buried insulating layer 158,160, can use silicon oxide film; As dielectric film 159, can use HfAlO X
[0072]
Then, adopt CMP or do not use the methods such as etching of mask, in the time of with dielectric film 157,159, buried insulating layer 158,160 and support 156 filmings, remove deoxidation and prevent film 154 and substrate oxide-film 153, thereby the surface of the semiconductor layer 135 of the 1st region R 11 and the 2nd region R 12 is exposed.Here, with suitable acceleration energy, ion injects suitable element ion, optionally dopant is poured into semiconductor layer 133, adopts annealing in process to make the dopant electrical activityization.
[0073]
Then, as shown in figure 16, the thermal oxidation, ALD or the CVD that carry out the surface of semiconductor layer 135 handle, thereby on the surface of the semiconductor layer 135 of the 1st region R 11 and the 2nd region R 12, form gate insulating film 161a, 161b respectively.Then, adopt methods such as CVD, on the semiconductor layer 135 that forms gate insulating film 161a, 161b, form polysilicon layer, silicon oxide layer or metal level.Then, use figure etching art and etching technique, Butut on polysilicon layer, silicon oxide layer or metal level, thus on gate insulating film 161a, 161b, form gate electrode 162a, 162b respectively.Then, as mask, ion injects impurity such as As, P, B in semiconductor layer 135 with gate electrode 162a, 162b, thus the LDD layer that on semiconductor layer 135, forms the both sides that are configured in gate electrode 162a, 162b respectively, constitutes by the low concentration impurity implanted layer.Then, adopt methods such as CVD, on the semiconductor layer 135 that forms the LDD layer, form insulating barrier, re-use anisotropic etchings such as RIE, insulating barrier is not used the etching of mask, thereby, form sidewall 163a, 163b respectively at the sidewall of gate electrode 162a, 162b.
[0074]
Then, as mask, ion injects As, P, B, BF in semiconductor layer 135 with gate electrode 162a, 162b 2Deng impurity, thereby on semiconductor layer 135, form source layer 164a, 164b and drain electrode layer 165a, the 165b that clamps gate electrode 162a, the configuration of 162b ground respectively.
Like this, semiconductor layer 133 can be used as back-gate electrode, not contact by gate electrode 142 and the restriction of the configuration of drain contact etc., the current potential of the transistorized active region of usefulness back-gate electrode controlling filed effect type with the source.Therefore, the complicated of manufacturing process can be suppressed, the transistorized threshold value of the dynamic controlling filed effect type of back-gate electrode can be utilized.In addition, when described back-gate electrode is connected with gate electrode, the rising characteristic of the leakage current in subthreshold value zone can be improved, the electric field of the raceway groove end of drain electrode layer 165a, 165b side can also be relaxed.Therefore, transistor is moved under low-voltage, the leakage current when reduce disconnecting when reducing action and the power consumption during standby, is realized high withstand voltageization of FET.
[0075]
(3) the 3rd execution modes
Figure 17 (a)～Figure 26 (a) is the vertical view of the manufacture method of the semiconductor device that relates to of expression the 3rd execution mode of the present invention, Figure 17 (b)～Figure 26 (b) is the profile that the A31-A31 ' that uses Figure 17 (a)～Figure 26 (a) respectively～A40-A40 ' line cuts off, and Figure 17 (c)～Figure 26 (c) is the profile that B31-B31 '～B40-B40 ' line of using Figure 17 (a)～Figure 26 (a) respectively cuts off.
[0076]
In Figure 17, epitaxial growth forms the 1st semiconductor layer 212 on semiconductor substrate 211, and epitaxial growth forms the 2nd semiconductor layer 213 on the 1st semiconductor layer 212.In addition, the 1st semiconductor layer 212 can use etching speed than semiconductor substrate 211 and the big material of the 2nd semiconductor layer 213, as the material of semiconductor substrate the 211, the 1st semiconductor layer 212 and the 2nd semiconductor layer 213, for example can use the combination of from Si, Ge, SiGe, SiC, SiSn, PbS, GaAS, InP, GaP, GaN or ZnSe etc., selecting.When particularly semiconductor substrate 211 is Si,, preferably use SiGe as the 1st semiconductor layer 212; As the 2nd semiconductor layer 213, preferably use Si.Like this, the lattice that can obtain between the 1st semiconductor layer 212 and the 2nd semiconductor layer 213 is integrated, and can guarantee the selection ratio between the 1st semiconductor layer 212 and the 2nd semiconductor layer 213.
[0077]
In addition, as the 1st semiconductor layer 212, except mono crystalline semiconductor layer, can also use many crystalline semiconductor layer, amorphous semiconductor layer or porous matter semiconductor layer.In addition, can also replace the 1st semiconductor layer 212, use can epitaxial growth forms the metal oxide film of the r-aluminium oxide of mono crystalline semiconductor layer etc.In addition, the thickness of the 1st semiconductor layer 212 and the 2nd semiconductor layer 213 for example can be decided to be about 1～200nm.
[0078]
Then, adopt the thermal oxidation of the 2nd semiconductor layer 213, form substrate oxide-film 214 on the surface of the 2nd semiconductor layer 213.Again then, by methods such as CVD, on whole on the substrate oxide-film 214, form oxidation and prevent film 215.In addition,, for example can use silicon nitride film,, can also play a role as the barrier layer of adopting CMP (grinding of chemical mechanicalness) to carry out in the flatening process except making it prevents that as oxidation film from playing a role as anti-oxidation surface diaphragm 215.
[0079]
Then, as shown in figure 18, use figure etching art and etching technique, prevent Butut on film 215, substrate oxide-film the 214, the 2nd semiconductor layer 213 and the 1st semiconductor layer 212 in oxidation, thus the groove 216 that formation is exposed the part of semiconductor substrate 211.In addition, when the part of semiconductor substrate 211 is exposed, both can be in the surface barrier etching of semiconductor substrate 211, also can over etching semiconductor substrate 211 after, on semiconductor substrate 11, form recess.In addition, the allocation position of groove 216 can make the part of element separated region of the 2nd semiconductor layer 213 corresponding.
[0080]
Then, as shown in figure 19, adopt selectable extension or CVD method, at the sidewall formation leading-out end layer 217 of the 1st semiconductor layer 212 and the 2nd semiconductor layer 213.As leading-out end layer 217, can use silicon fiml etc. here.Then, the sidewall at the 1st semiconductor layer 212 and the 2nd semiconductor layer 213 forms under the state of leading-out end layer 217, with a part of thermal oxidation of the 1st semiconductor layer 212 and the 2nd semiconductor layer 213.
[0081]
Here, after forming leading-out end layer 217, implement the thermal oxidation of the 1st semiconductor layer 212 and the 2nd semiconductor layer 213, can suppress the composition that the 1st semiconductor layer 212 comprises and spread, can also be at least form the less semiconductor/interfacial oxide film in benchmark position, interface at the sidewall of the 2nd semiconductor layer 213 to foreign side.Simultaneously, can prevent that composition that the 1st semiconductor layer 212 comprises from polluting around.
[0082]
Then, as shown in figure 20, adopt methods such as CVD, form the support of imbedding in the groove 216 218, so that cover on the semiconductor substrate 211 whole.In addition, form on the 1st semiconductor layer 212 that support 218 also can be in groove 216 and the sidewall of the 2nd semiconductor layer 213, on semiconductor substrate 211, support the 2nd semiconductor layer 213., cover the support 218 that integrally forms of semiconductor substrate 211 here, need the deflection of inhibition the 2nd semiconductor layer 213 etc., under the state that keeps flatness, support the 2nd semiconductor layer 213.Therefore, in order to ensure its mechanical strength, preferably become than smallest elements and separate the thick thickness of width.In addition, as the material of support 218, can use element isolation insulators such as silicon oxide film.
[0083]
Then, as shown in figure 21, use figure etching art and etching technique, prevent Butut on film 215, substrate oxide-film the 214, the 2nd semiconductor layer 213 and the 1st semiconductor layer 212 in support 218, oxidation, thus the groove 219 that formation is exposed the part of the 1st semiconductor layer 212.Here, the allocation position of groove 219 can make the part of element separated region of the 2nd semiconductor layer 213 corresponding.
[0084]
In addition, when the part of the 1st semiconductor layer 212 is exposed, both can be with the surface barrier etching of the 1st semiconductor layer 212, also can over etching the 1st semiconductor layer 212 after, on the 1st semiconductor layer 212, form recess.Perhaps, the 1st semiconductor layers 212 in the groove 219 are connected after, the surface of semiconductor substrate 211 is exposed.Behind the 1st semiconductor layer 212 that stops etching halfway, can prevent that the surface of the semiconductor substrate 211 in the groove 219 from exposing here.Therefore, when the 1st semiconductor layer 212 is removed in etching, the exposure time of semiconductor substrate 211 in etching solution or etching gas in the groove 219 can be reduced, the semiconductor substrate 211 in the over etching groove 219 can be suppressed.
[0085]
Then, as shown in figure 22, do media, etching gas or etching solution are contacted with the 1st semiconductor layer 212, thereby the 1st semiconductor layer 212 is removed in etching, between semiconductor substrate 211 and the 2nd semiconductor layer 213, form blank part 220 by groove 219.
Here, after support 218 is set in groove 216, even when having removed the 1st semiconductor layer 212, also can on semiconductor substrate 211, support the 2nd semiconductor layer 213, simultaneously, after outside the groove 216 groove 219 being set separately, etching gas or etching solution are contacted with the 1st semiconductor layer 212 under the 2nd semiconductor layer 213.Therefore, can not damage the quality ground of the 2nd semiconductor layer 213 with insulation between the 2nd semiconductor layer 213 and the semiconductor substrate 211.
[0086]
In addition, semiconductor substrate 211 and the 2nd semiconductor layer 213 are Si, when the 1st semiconductor layer 212 is SiGe, as the etching solution of the 1st semiconductor layer 212, preferably uses and fluoridize nitric acid (mixed liquor of fluoric acid, nitric acid, water).Like this, over etching semiconductor substrate 211 and the 2nd semiconductor layer 213 can be suppressed, the 1st semiconductor layer 212 can be removed.In addition, as the etching solution of the 1st semiconductor layer 212, can also use and fluoridize nitric acid+aquae hydrogenii dioxidi, ammonia+aquae hydrogenii dioxidi or fluoridize acetic acid+aquae hydrogenii dioxidi etc.
[0087]
In addition, before the 1st semiconductor layer 212 is removed in etching, methods such as anodic oxidation both can have been adopted, make the 1st semiconductor layer 212 porous materializations, also can inject ion to the 1st semiconductor layer 212, thereby,, can also use the P type semiconductor substrate as semiconductor substrate 211 with the 1st semiconductor layer 212 amorphousization.Like this, can increase the etching speed of the 1st semiconductor layer 212, enlarge the etching area of the 1st semiconductor layer 212.
[0088]
Then, as shown in figure 23, adopt methods such as CVD, the top and bottom in the blank part 220 between semiconductor substrate 211 and the 2nd semiconductor layer 213 form dielectric film 221.Then, as shown in figure 24, adopt methods such as CVD, in the blank part 220 and groove 219 that form dielectric film 221, form buried insulating layer 222.In addition, as the material of dielectric film 221 and buried insulating layer 222, for example except silicon oxide film, can also use silicon nitride film etc.Perhaps, as the material of dielectric film 221 and buried insulating layer 222, for example can use HfO 2, HfON, HfAlO, HfAlON, HfSiO, HfSiON, ZrO 2, ZrON, ZrAlO, ZrAlON, ZrSiO, ZrSiON, Ta 2O 5, Y 2O 3, (Sr, Ba) TiO 3, LaAlO 3, SrBi 2Ta 2O 9, Bi 4Ti 3O 12, Pb (Zi, Ti) O 3Deng dielectric.For example:, can use silicon nitride film as dielectric film 221; As buried insulating layer 222, can use silicon oxide film.
[0089]
Like this, can control the fixed charge of dielectric film 221 and buried insulating layer 224, can be from the transistorized threshold value of rear side controlling filed effect type of the 2nd semiconductor layer 213.For example, as dielectric film 221 and buried insulating layer 224, when using silicon nitride film, P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn can both make threshold value move to negative direction.In addition, as dielectric film 221 and buried insulating layer 222, use HfAlO XThe time, being accompanied by the increase of Al concentration, P-channel field-effect transistor (PEFT) transistor npn npn and N channel field-effect transistor npn npn can both make threshold value move to positive direction.
[0090]
Therefore,, also can utilize the fixed charge of described dielectric film 221 and buried insulating layer 224, make about the changes of threshold three ten-day period of hot season spy of FET even when the tagma of the 2nd semiconductor layer 213 is mixed fixedly by intrinsic or low concentration ground.Therefore can be irrelevant with the height of threshold voltage, improve the degree of excursion of FET, increase its making current.In addition, owing to can reduce the impurity concentration of the 2nd semiconductor layer 213, so in the scope that short-channel effect is allowed during with the 2nd semiconductor layer 213 thick films, also can obtain precipitous subthreshold value, when on the 2nd semiconductor layer 213, forming FET, also can reduce the characteristic deviation, can also improve rate of finished products simultaneously, reduce manufacturing cost.
[0091]
In addition,, can pass through preceding washing procedure, make dielectric film 221 and buried insulating layer 222 have negative electrical charge or positive charge for the transistorized threshold value of controlling filed effect type.Here, when making dielectric film 221 and buried insulating layer 222 have negative electrical charge, can be before forming dielectric film 221 and buried insulating layer 222, with the rear side of ammonia+hydrogen peroxide water washing the 2nd semiconductor layer 213 that contains Al.In addition, when making dielectric film 221 and buried insulating layer 222 have positive charge, can be before forming dielectric film 221 and buried insulating layer 222, the rear side of washing the 2nd semiconductor layer 213 with fluoric acid.
[0092]
Then, as shown in figure 25, adopt CMP or do not use the methods such as etch processes of mask, in the time of with dielectric film 221 and buried insulating layer 222 and support 218 filmings, also oxidation is prevented film as the barrier layer, the planarization that stops CMP to produce.Follow again, remove substrate oxide-film 214 and oxidation and prevent film 215, the surface of the 2nd semiconductor layer 213 is exposed.
Then, as shown in figure 26, the thermal oxidation, ALD or the CVD that carry out the surface of the 2nd semiconductor layer 213 handle, thereby on the surface of the 2nd semiconductor layer 213, form gate insulating film 23.Then, adopt methods such as CVD, on the 2nd semiconductor layer 213 that forms gate insulating film 23, form polysilicon layer, silicon oxide layer or metal level.Then, use figure etching art and etching technique, Butut on polysilicon layer, silicon oxide layer or metal level, thus on the 2nd semiconductor layer 213, form gate electrode 224.
[0093]
Then, as mask, ion injects impurity such as As, P, B in the 2nd semiconductor layer 213 with gate electrode 224, thus the LDD layer that on the 2nd semiconductor layer 213, forms the both sides that are configured in gate electrode 224 respectively, constitutes by the low concentration impurity implanted layer.Then, adopt methods such as CVD, on the 2nd semiconductor layer 213 that forms the LDD layer, form insulating barrier, re-use anisotropic etchings such as RTE, insulating barrier is not used the etching of mask, thereby, form sidewall 225 respectively at the sidewall of gate electrode 224.Then, with gate electrode 224 and sidewall 225 as mask, ion injects impurity such as As, P, B in the 2nd semiconductor layer 213, thus the source layer 226a and the drain electrode layer 226b that on the 2nd semiconductor layer 213, form the both sides that are configured in sidewall 225 respectively, constitute by the high concentration impurities implanted layer.
[0094]
Then, adopt methods such as CVD, on gate electrode 224, pile up interlayer insulating film 232.Then, interlayer insulating film 232, the source electrode contact electrode 233a that is connected with source layer 226a, drain electrode layer 226b and gate electrode 224 respectively, drain electrode contact electrode 233b and grid contact electrode 233c are imbedded in formation on interlayer insulating film 232.
[0095]
Like this, can reduce the generation of the defective of the 2nd semiconductor layer 213, can on dielectric film 221, dispose the 2nd semiconductor layer 213, can on the basis that suppresses the cost increase, can also form the SOI transistor.
In addition, buried insulating layer 222 and gate insulating film 224 preferably make in its effective efficiency function or the fixed charge amount at least one set differently.For example:, can use silicon oxide film or silicon nitride film as gate insulating film 224; As buried insulating layer 222, can use silicon nitride film, contain Al silicon oxide film, contain Al the Hf oxide, contain Al the Zr oxide, do not contain Al the Hf oxide, do not contain the Zr oxide of Al etc.
[0096]
Like this, can guarantee the flatness at the interface of gate insulating film 224 and raceway groove, reduce interface benchmark density, can also when the 2nd semiconductor layer 213 filmings of channel region, reduce impurity concentration, the transistorized threshold value of controlling filed effect type simultaneously.Therefore, can suppress the deterioration of carrier mobility, suppress the deviation of transistor characteristic, obtain precipitous subthreshold value, the power consumption when reducing action, the high speed of realization FET.
[0097]
(4) the 4th execution modes
Figure 27 (a)～Figure 35 (a) is the vertical view of the manufacture method of the semiconductor device that relates to of expression the 4th execution mode of the present invention, Figure 27 (b)～Figure 35 (b) is the profile that the A41-A41 ' that uses Figure 27 (a)～Figure 35 (a) respectively～A49-A49 ' line cuts off, and Figure 27 (c)～Figure 35 (c) is the profile that B41-B41 '～B49-B49 ' line of using Figure 27 (a)～Figure 35 (a) respectively cuts off.
[0098]
In Figure 27, on semiconductor substrate 331, stack gradually to epitaxial growth semiconductor layer 351,333,352,335.Here, semiconductor layer 351,352 can use the etching speed material bigger than semiconductor substrate 331 and semiconductor layer 333,335.When particularly semiconductor substrate 331 is Si,, preferably use SiGe as semiconductor layer 351,352; As semiconductor layer 333,335, preferably use Si.
Then, methods such as the thermal oxidation of employing semiconductor layer 335 or CVD form substrate oxide-film 353 on the surface of semiconductor layer 335.Again then, by methods such as CVD, on whole of substrate oxide-film 353, form oxidation and prevent film 354.
[0099]
Then, as shown in figure 28, use figure etching art and etching technique, prevent Butut on film 354, substrate oxide-film 353, the semiconductor layer 335,352,333,351, thereby form the groove 336 that semiconductor substrate 331 is exposed along the direction of regulation in oxidation.And then, use figure etching art and etching technique, prevent Butut on film 354, substrate oxide-film 353, the semiconductor layer 335,352 in oxidation, thereby form, the width 336 stacked groove that expose semiconductor substrate 333 337 bigger than groove 336 with groove.
[0100]
Then, as shown in figure 29, adopt methods such as CVD, on whole of semiconductor substrate 131, form and imbed the support 356 of supporting semiconductor layer 333,335 in the groove 336,337, on semiconductor substrate 331.In addition, as the material of support 356, can use insulators such as silicon oxide film.
Follow again, as shown in figure 30, use figure etching art and etching technique, prevent Butut on film 354, substrate oxide-film 353, the semiconductor layer 335,352,333,351 in oxidation, thereby along with the direction of groove 336 quadratures, form the groove 338 that semiconductor layer 331 is exposed.
[0101]
Then, as shown in figure 31, do media by groove 338, etching gas or etching solution are contacted with semiconductor layer 351,352, thereby semiconductor layer 351,352 is removed in etching, between semiconductor substrate 331 and semiconductor layer 333, form in the blank part 357a, also between semiconductor layer 333,335, form blank part 357b.
Then, shown in figure 32, adopt methods such as thermal oxidation and CVD, the top and bottom in blank part 357a, the 357b between semiconductor substrate 331 and semiconductor layer 333,335 form dielectric film 334.Again then, as shown in figure 33, adopt methods such as CVD, in blank part 357a, the 357b and groove 338 that form dielectric film 334, form buried insulating layer 345.Here, with suitable acceleration energy, ion injects suitable element ion, optionally dopant is poured into semiconductor layer 333, adopts annealing in process, makes the dopant electrical activityization.
[0102]
Then, as shown in figure 34, adopt CMP or do not use the methods such as etching of mask, the time dielectric film 334, buried insulating layer 345 and support 356 filmings, remove deoxidation and prevent film 354 and substrate oxide-film 353, thereby the surface of semiconductor layer 335 is exposed.The ion that carries out with above-mentioned Figure 33 injects, and also can replace Figure 33, carries out in Figure 34.
[0103]
Then, as shown in figure 35, the thermal oxidation, ALD or the CVD that carry out the surface of semiconductor layer 335 handle, thereby on the surface of semiconductor layer 335, form gate insulating film 341.Then, adopt methods such as CVD, on the semiconductor layer 335 that forms gate insulating film 341, form polysilicon layer, silicon oxide layer or metal level.Again then, use figure etching art and etching technique, Butut on polysilicon layer, silicon oxide layer or metal level, thus on semiconductor layer 335, form gate electrode 342.
[0104]
Then, as mask, ion injects impurity such as As, P, B in semiconductor layer 335 with gate electrode 342, thereby forms source layer 343a and the drain electrode layer 343b that clamps the configuration of gate electrode 342 ground on semiconductor layer 335.
Follow again, adopt methods such as CVD, on gate electrode 342, pile up interlayer insulating film 344.Then, form on interlayer insulating film 344 in the back-gate electrode contact electrode 245a imbed interlayer insulating film 344 and support 356, to be connected with semiconductor layer 333, also interlayer insulating film 344, the source electrode contact electrode 346a that is connected with source layer 343a, drain electrode layer 343b respectively and the contact electrode 246b that drains are imbedded in formation on interlayer insulating film 344.
[0105]
Like this, semiconductor layer 333 can be used as back-gate electrode, can not be subjected to the restriction of the configuration of gate electrode 342 and source contact electrode 346a and drain electrode contact electrode 246b etc., with the current potential of the transistorized active region of back-gate electrode controlling filed effect type.Therefore, the complicated of manufacturing process can be suppressed, the transistorized threshold value of the dynamic controlling filed effect type of back-gate electrode can be utilized.In addition, when back-gate electrode 333 is connected with gate electrode 342, can make the rising characteristic of leakage current in subthreshold value zone precipitous.Therefore, transistor is moved under low-voltage, the leakage current when reduce disconnecting when reducing action and the power consumption during standby, is realized high withstand voltageization of FET.
[0106]
In addition, buried insulating layer 345 and gate insulating film 341 preferably make in its effective efficiency function or the fixed charge amount at least one set differently.For example:, can use silicon oxide film or silicon nitride film as gate insulating film 341; As buried insulating layer 345, can use silicon nitride film, contain Al silicon oxide film, contain Al the Hf oxide, contain Al the Zr oxide, do not contain Al the Hf oxide, do not contain the Zr oxide of Al etc.
[0107]
Like this, even when mixed by intrinsic or low concentration ground in the tagma of semiconductor layer 335, also can make the threshold value of FET that three ten-day period of hot season spy's variation take place by the combination of gate insulating film 341 and buried insulating layer 345.Therefore, can be irrelevant with the height of threshold voltage, reduce the concentration of the dopant of semiconductor layer 335, improve the degree of excursion of FET, increase its making current.In addition, owing to can reduce the impurity concentration of semiconductor layer 335,, reduce the characteristic deviation, can also improve rate of finished products simultaneously, reduce manufacturing cost so in the scope that short-channel effect is allowed, during with the semiconductor layer thick film, also can obtain precipitous subthreshold value.

Claims (24)

1, a kind of semiconductor device is characterized in that: possess:
The epitaxial growth and forming on semiconductor substrate of semiconductor layer, this semiconductor layer;
The 1st buried insulating layer, this layer are imbedded the 1st zone between described semiconductor substrate and the described semiconductor layer; And
The 2nd buried insulating layer, this layer are imbedded the 2nd zone between described semiconductor substrate and the described semiconductor layer,
Between described the 1st buried insulating layer and described the 2nd buried insulating layer, at least one in effective efficiency function or the fixed charge amount is different.
2, semiconductor device as claimed in claim 1, it is characterized in that: described the 1st buried insulating layer or described the 2nd buried insulating layer are made of silicon nitride film, the silicon oxide film that contains Al, the Hf oxide that contains Al, the Zr oxide that contains Al, the Zr oxide that does not contain the silicon oxide film of Al, do not contain the Hf oxide of Al or do not contain Al.
3, a kind of semiconductor device is characterized in that: possess:
Semiconductor layer, this semiconductor layer forms on the 1st and the 2nd insulating barrier;
The 1st back-gate electrode, the 1st back-gate electrode Jie has described the 1st insulating barrier and is configured under the described semiconductor layer;
The 2nd back-gate electrode, the 2nd back-gate electrode Jie has described the 2nd insulating barrier and is configured under the described semiconductor layer;
The 1st gate electrode, the 1st gate electrode are formed on the semiconductor layer on described the 1st insulating barrier; And
The 2nd gate electrode, the 2nd gate electrode are formed on the semiconductor layer on described the 2nd insulating barrier,
Between the 1st and the 2nd insulating barrier, at least one in effective efficiency function or the fixed charge amount is different.
4, semiconductor device as claimed in claim 3, it is characterized in that: described the 1st insulating barrier or described the 2nd insulating barrier are made of silicon nitride film, the silicon oxide film that contains Al, the Hf oxide that contains Al, the Zr oxide that contains Al, the Zr oxide that does not contain the silicon oxide film of Al, do not contain the Hf oxide of Al or do not contain Al.
5, as claim 3 or 4 described semiconductor devices, it is characterized in that: also possess the wiring layer that respectively the described the 1st and the 2nd gate electrode is electrically connected with the described the 1st and the 2nd back-gate electrode.
6, a kind of manufacture method of semiconductor device is characterized in that, possesses:
On semiconductor substrate, form the operation of the 1st semiconductor layer;
On described 1 semiconductor layer, form the operation of etching speed 2nd semiconductor layer littler than described the 1st semiconductor layer;
Form the operation of the 1st exposed division, the 1st exposed division also is broken into the 1st and the 2nd zone with described the 1st semiconductor layer and the 2nd semiconductor layer branch connecting when described the 1st semiconductor layer and the 2nd semiconductor layer expose described semiconductor substrate;
Form the operation of support, this support is supported described the 2nd semiconductor layer through described the 1st exposed division on described semiconductor substrate;
Form the operation of the 2nd exposed division, the 2nd exposed division makes the part of the 1st semiconductor layer in described the 1st zone, exposes from described the 2nd semiconductor layer;
Form the operation of the 1st blank part, in this operation by described the 2nd exposed division, the 1st semiconductor layer in described the 1st zone of etching optionally, thus under described the 2nd semiconductor layer, form the 1st blank part of the 1st semiconductor layer of having removed described the 1st zone;
The operation of the 1st buried insulating layer in described the 1st blank part is imbedded in formation;
Form the operation of the 3rd exposed division, the 3rd exposed division makes the part of the 1st semiconductor layer in described the 2nd zone, exposes from described the 2nd semiconductor layer;
Form the operation of the 2nd blank part, in this operation by described the 3rd exposed division, the 1st semiconductor layer in described the 2nd zone of etching optionally, thus under described the 2nd semiconductor layer, form the 2nd blank part of the 1st semiconductor layer of having removed described the 2nd zone; And
The operation of the 2nd buried insulating layer in described the 2nd blank part is imbedded in formation,
Between described the 1st buried insulating layer and described the 2nd buried insulating layer, at least one in effective efficiency function or the fixed charge amount is different.
7, a kind of manufacture method of semiconductor device is characterized in that, possesses:
On semiconductor substrate, form the operation of the 1st semiconductor layer;
On described the 1st semiconductor layer, form the etching speed 2nd semiconductor layer operation littler than described the 1st semiconductor layer;
On described the 2nd semiconductor layer, form the operation have with the 3rd semiconductor layer of the same composition of described the 1st semiconductor layer;
On described the 3rd semiconductor layer, form the operation have with the 4th semiconductor layer of the same composition of described the 2nd semiconductor layer;
Form the operation of the 1st exposed division, the 1st exposed division also is broken into the 1st and the 2nd zone with described the 1st semiconductor layer～the 4th semiconductor layer branch when described the 1st～the 4th semiconductor layer of perforation exposes described semiconductor substrate;
Form the operation of support, this support is supported the described the 2nd and the 4th semiconductor layer by described the 1st exposed division on described semiconductor substrate;
Form the operation of the 2nd exposed division, the 2nd exposed division makes at least a portion of the 1st and the 3rd semiconductor layer in described the 1st zone, exposes from the described the 2nd and the 4th semiconductor layer;
Form the operation of the 1st and the 2nd blank part, in this operation by described the 2nd exposed division, optionally etching the described the 1st and the 3rd semiconductor layer, thus form the 1st and the 2nd blank part of the 1st and the 3rd semiconductor layer of having removed described the 1st zone respectively;
Form the operation of imbedding the 1st buried insulating layer in the described the 1st and the 2nd blank part respectively;
Form the operation of the 3rd exposed division, the 3rd exposed division makes at least a portion of the 1st and the 3rd semiconductor layer in described the 2nd zone, exposes from the described the 2nd and the 4th semiconductor layer;
Form the operation of the 3rd and the 4th blank part, in this operation by described the 3rd exposed division, optionally etching the 1st and the 3rd semiconductor layer, thus form the 3rd and the 4th blank part of the 1st and the 3rd semiconductor layer of having removed described the 2nd zone respectively; And
Form the operation of imbedding the 2nd buried insulating layer in the described the 3rd and the 4th blank part respectively,
Between described the 1st buried insulating layer and described the 2nd buried insulating layer, at least one in effective efficiency function or the fixed charge amount is different.
8, the manufacture method of semiconductor device as claimed in claim 7 is characterized in that: also possess: before forming the described the 1st or the 2nd buried insulating layer, with the operation of the rear side of ammonia hydrogen peroxide water washing the described the 2nd that contains Al and the 4th semiconductor layer.
9, the manufacture method of semiconductor device as claimed in claim 7 is characterized in that: also possess: before forming the described the 1st or the 2nd buried insulating layer, wash the described the 2nd and the operation of the rear side of the 4th semiconductor layer with fluoric acid.
10, as the manufacture method of each described semiconductor device of claim 7～9, it is characterized in that: described semiconductor substrate and the described the 2nd and the 4th semiconductor layer are single crystals Si, and the described the 1st and the 3rd semiconductor layer is single crystals SiGe.
11, a kind of semiconductor device is characterized in that: possess:
Semiconductor layer, this semiconductor layer forms after epitaxial growth on the semiconductor substrate;
Buried insulating layer, this buried insulating layer are imbedded between described semiconductor substrate and the described semiconductor layer;
Gate electrode, this gate electrode is formed on the described semiconductor layer across gate insulating film; And
Source/drop ply, this source/drop ply are formed on the described semiconductor layer, are configured in the side of described gate electrode respectively,
Described buried insulating layer and described gate insulator are intermembranous, and at least one in effective efficiency function or the fixed charge amount is different.
12, semiconductor device as claimed in claim 11 is characterized in that: described gate insulating film is made of silicon oxide film or silicon oxynitride film; Described buried insulating layer is made of silicon nitride film, the silicon oxide film that contains Al, the Hf oxide that contains Al, the Zr oxide that contains Al, the Zr oxide that does not contain the Hf oxide of Al or do not contain Al.
13, a kind of semiconductor device is characterized in that: possess:
Semiconductor layer, this semiconductor layer is formed on the insulating barrier;
Back-gate electrode, this back-gate electrode Jie has described insulating barrier and is configured under the described semiconductor layer;
Gate electrode, this gate electrode are formed on the described semiconductor layer; And
Source/drop ply, this source/drop ply is formed on the described semiconductor layer, and is configured in the side of described gate electrode respectively,
Described insulating barrier and described gate insulator are intermembranous, and at least one in effective efficiency function or the fixed charge amount is different.
14, semiconductor device as claimed in claim 13 is characterized in that: described gate insulating film is made of silicon oxide film or silicon oxynitride film; Described insulating barrier is made of silicon nitride film, the silicon oxide film that contains Al, the Hf oxide that contains Al, the Zr oxide that contains Al, the Zr oxide that does not contain the Hf oxide of Al or do not contain Al.
15, as claim 13 or 14 described semiconductor devices, it is characterized in that: also possess the wiring layer that described gate electrode is electrically connected with described back-gate electrode.
16, a kind of manufacture method of semiconductor device is characterized in that, possesses:
On semiconductor substrate, form the operation of the 1st semiconductor layer;
On described 1 semiconductor layer, form the operation of etching speed 2nd semiconductor layer littler than described the 1st semiconductor layer;
Form the operation of the 1st exposed division, the 1st exposed division connects described the 1st semiconductor layer and the 2nd semiconductor layer, and described semiconductor substrate is exposed;
Form the operation of support, this support is supported described the 2nd semiconductor layer by described the 1st exposed division on described semiconductor substrate;
Form the operation of the 2nd exposed division, the 2nd exposed division makes the part of described the 1st semiconductor layer, exposes from described the 2nd semiconductor layer;
Form the operation of blank part, in this operation by described the 2nd exposed division, described the 1st semiconductor layer of etching optionally, thus under described the 2nd semiconductor layer, form the blank part of having removed described the 1st semiconductor layer;
The operation of the buried insulating layer in the described blank part is imbedded in formation;
On the surface of described the 2nd semiconductor layer, form the operation of gate insulating film; And
Across described gate insulating film, form the operation that is configured in the gate electrode on described the 2nd semiconductor layer,
Described buried insulating layer and described gate insulator are intermembranous, and at least one in effective efficiency function or the fixed charge amount is different.
17, a kind of manufacture method of semiconductor device is characterized in that, possesses:
On semiconductor substrate, form the operation of the 1st semiconductor layer;
On described the 1st semiconductor layer, form the etching speed 2nd semiconductor layer operation littler than described the 1st semiconductor layer;
Form the operation of the 1st exposed division, the 1st exposed division connects described the 1st semiconductor layer and the 2nd semiconductor layer, and described semiconductor substrate is exposed;
Form the operation of support, this support is supported described the 2nd semiconductor layer by described the 1st exposed division on described semiconductor substrate;
Form the operation of the 2nd exposed division, the 2nd exposed division makes the part of described the 1st semiconductor layer, exposes from described the 2nd semiconductor layer;
Form the operation of blank part, in this operation by described the 2nd exposed division, described the 1st semiconductor layer of etching optionally, thus under described the 2nd semiconductor layer, form the blank part of having removed described the 1st semiconductor layer;
In the top and bottom of described blank part, form the operation of dielectric film;
Formed the operation of imbedding in the described blank part of imbedding back-gate electrode up and down by described dielectric film with clipping;
On the surface of described the 2nd semiconductor layer, form the operation of gate insulating film; And
Across described gate insulating film, form the operation that is configured in the gate electrode on described the 2nd semiconductor layer;
Described insulating barrier and described gate insulator are intermembranous, and at least one in effective efficiency function or the fixed charge amount is different.
18, the manufacture method of semiconductor device as claimed in claim 17, it is characterized in that: also possess: before the insulating barrier of the top and bottom that form described blank part, with the operation of the rear side of ammonia hydrogen peroxide water washing the described the 2nd that contains Al and the 4th semiconductor layer.
19, the manufacture method of semiconductor device as claimed in claim 17 is characterized in that: also possess: before forming described buried insulating layer, wash the described the 2nd and the operation of the rear side of the 4th semiconductor layer with fluoric acid.
20, a kind of manufacture method of semiconductor device is characterized in that, possesses:
On semiconductor substrate, form the operation of the 1st semiconductor layer;
On described the 1st semiconductor layer, form the etching speed 2nd semiconductor layer operation littler than described the 1st semiconductor layer;
On described the 2nd semiconductor layer, form the operation have with the 3rd semiconductor layer of the same composition of described the 1st semiconductor layer;
On described the 3rd semiconductor layer, form the operation have with the 4th semiconductor layer of the same composition of described the 2nd semiconductor layer;
Form the operation of the 1st exposed division, the 1st exposed division connects described the 1st～the 4th semiconductor layer, and described semiconductor substrate is exposed;
Form the operation of support, this support is formed on described the 1st exposed division, supports the described the 2nd and the 4th semiconductor layer on described semiconductor substrate;
Form the operation of the 2nd exposed division, the 2nd exposed division makes at least a portion of the described the 1st and the 3rd semiconductor layer that are formed with described support, exposes from the described the 2nd and the 4th semiconductor layer;
Form the operation of the 1st and the 2nd blank part, by described the 2nd exposed division, optionally etching the described the 1st and the 3rd semiconductor layer have removed the described the 1st and the 1st and the 2nd blank part of the 3rd semiconductor layer respectively thereby form in this operation;
Form the operation of imbedding the buried insulating layer in the described the 1st and the 2nd blank part respectively;
On the surface of described the 4th semiconductor layer, form the operation of gate insulating film; And
Across described gate insulating film, form the operation that is configured in the gate electrode on described the 4th semiconductor layer,
Described buried insulating layer and described gate insulator are intermembranous, and at least one in effective efficiency function or the fixed charge amount is different.
21, the manufacture method of semiconductor device as claimed in claim 20 is characterized in that: also possess: before forming described buried insulating layer, with the operation of the rear side of ammonia hydrogen peroxide water washing the described the 2nd that contains Al and the 4th semiconductor layer.
22, the manufacture method of semiconductor device as claimed in claim 20 is characterized in that: also possess: before forming described buried insulating layer, wash the described the 2nd and the operation of the rear side of the 4th semiconductor layer with fluoric acid.
23, as the manufacture method of each described semiconductor device of claim 16～19, it is characterized in that: described semiconductor substrate and described the 2nd semiconductor layer are single crystals Si, and described the 1st semiconductor layer is single crystals SiGe.
24, as the manufacture method of each described semiconductor device of claim 20～22, it is characterized in that: described semiconductor substrate and the described the 2nd and the 4th semiconductor layer are single crystals Si, and the described the 1st and the 3rd semiconductor layer is single crystals SiGe.
CN 200610164165 2005-12-09 2006-12-06 Semiconductor device and method of fabricating the same Pending CN1979879A (en)

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JP2005355984 2005-12-09
JP2005355984 2005-12-09
JP2005361728 2005-12-15
JP2006252586 2006-09-19

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013033877A1 (en) * 2011-09-07 2013-03-14 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
CN104051468A (en) * 2013-03-15 2014-09-17 新加坡商格罗方德半导体私人有限公司 Back-gated non-volatile memory cell
CN108054132A (en) * 2017-12-13 2018-05-18 上海华虹宏力半导体制造有限公司 Semiconductor devices and preparation method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013033877A1 (en) * 2011-09-07 2013-03-14 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
US8598666B2 (en) 2011-09-07 2013-12-03 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor structure and method for manufacturing the same
CN104051468A (en) * 2013-03-15 2014-09-17 新加坡商格罗方德半导体私人有限公司 Back-gated non-volatile memory cell
US9444041B2 (en) 2013-03-15 2016-09-13 Globalfoundries Singapore Pte. Ltd. Back-gated non-volatile memory cell
CN108054132A (en) * 2017-12-13 2018-05-18 上海华虹宏力半导体制造有限公司 Semiconductor devices and preparation method thereof

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